[PATCH 0/3] Add support for the Iris codec on Milos

[PATCH 0/3] Add support for the Iris codec on Milos

[Alexander Koskovich]

This series adds the bindings, nodes and platform data for the Milos platform
for the Iris video codec, allowing Milos to use hardware‑accelerated video
encoding and decoding.

Ran v4l2-compliance and some fluster tests, though a concerning amount of them
failed. Attaching v4l2-compliance output and the full fluster results below.

~ # v4l2-compliance -d /dev/video0
v4l2-compliance 1.32.0, 64 bits, 64-bit time_t

Compliance test for iris_driver device /dev/video0:

Driver Info:
	Driver name      : iris_driver
	Card type        : Iris Decoder
	Bus info         : platform:aa00000.video-codec
	Driver version   : 7.0.0
	Capabilities     : 0x84204000
		Video Memory-to-Memory Multiplanar
		Streaming
		Extended Pix Format
		Device Capabilities
	Device Caps      : 0x04204000
		Video Memory-to-Memory Multiplanar
		Streaming
		Extended Pix Format
	Detected Stateful Decoder

Required ioctls:
	test VIDIOC_QUERYCAP: OK
	test invalid ioctls: OK

Allow for multiple opens:
	test second /dev/video0 open: OK
	test VIDIOC_QUERYCAP: OK
	test VIDIOC_G/S_PRIORITY: OK
	test for unlimited opens: OK

Debug ioctls:
	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
	test VIDIOC_LOG_STATUS: OK (Not Supported)

Input ioctls:
	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
	test VIDIOC_ENUMAUDIO: OK (Not Supported)
	test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
	test VIDIOC_G/S_AUDIO: OK (Not Supported)
	Inputs: 0 Audio Inputs: 0 Tuners: 0

Output ioctls:
	test VIDIOC_G/S_MODULATOR: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_ENUMAUDOUT: OK (Not Supported)
	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
	test VIDIOC_G/S_AUDOUT: OK (Not Supported)
	Outputs: 0 Audio Outputs: 0 Modulators: 0

Input/Output configuration ioctls:
	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
	test VIDIOC_G/S_EDID: OK (Not Supported)

Control ioctls:
	test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
	test VIDIOC_QUERYCTRL: OK
	test VIDIOC_G/S_CTRL: OK
	test VIDIOC_G/S/TRY_EXT_CTRLS: OK
	test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
	test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
	Standard Controls: 10 Private Controls: 0

Format ioctls:
	test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
	test VIDIOC_G/S_PARM: OK (Not Supported)
	test VIDIOC_G_FBUF: OK (Not Supported)
	test VIDIOC_G_FMT: OK
	test VIDIOC_TRY_FMT: OK
	test VIDIOC_S_FMT: OK
	test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
	test Cropping: OK
	test Composing: OK
	test Scaling: OK (Not Supported)

Codec ioctls:
	test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
	test VIDIOC_G_ENC_INDEX: OK (Not Supported)
	test VIDIOC_(TRY_)DECODER_CMD: OK

Buffer ioctls:
	test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
	test CREATE_BUFS maximum buffers: OK
	test VIDIOC_REMOVE_BUFS: OK
	test VIDIOC_EXPBUF: OK
	test Requests: OK (Not Supported)
	test blocking wait: OK

Total for iris_driver device /dev/video0: 48, Succeeded: 48, Failed: 0, Warnings: 0

~ # v4l2-compliance -d /dev/video1
v4l2-compliance 1.32.0, 64 bits, 64-bit time_t

Compliance test for iris_driver device /dev/video1:

Driver Info:
	Driver name      : iris_driver
	Card type        : Iris Encoder
	Bus info         : platform:aa00000.video-codec
	Driver version   : 7.0.0
	Capabilities     : 0x84204000
		Video Memory-to-Memory Multiplanar
		Streaming
		Extended Pix Format
		Device Capabilities
	Device Caps      : 0x04204000
		Video Memory-to-Memory Multiplanar
		Streaming
		Extended Pix Format
	Detected Stateful Encoder

Required ioctls:
	test VIDIOC_QUERYCAP: OK
	test invalid ioctls: OK

Allow for multiple opens:
	test second /dev/video1 open: OK
	test VIDIOC_QUERYCAP: OK
	test VIDIOC_G/S_PRIORITY: OK
	test for unlimited opens: OK

Debug ioctls:
	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
	test VIDIOC_LOG_STATUS: OK (Not Supported)

Input ioctls:
	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
	test VIDIOC_ENUMAUDIO: OK (Not Supported)
	test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
	test VIDIOC_G/S_AUDIO: OK (Not Supported)
	Inputs: 0 Audio Inputs: 0 Tuners: 0

Output ioctls:
	test VIDIOC_G/S_MODULATOR: OK (Not Supported)
	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
	test VIDIOC_ENUMAUDOUT: OK (Not Supported)
	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
	test VIDIOC_G/S_AUDOUT: OK (Not Supported)
	Outputs: 0 Audio Outputs: 0 Modulators: 0

Input/Output configuration ioctls:
	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
	test VIDIOC_G/S_EDID: OK (Not Supported)

Control ioctls:
	test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
	test VIDIOC_QUERYCTRL: OK
	test VIDIOC_G/S_CTRL: OK
	test VIDIOC_G/S/TRY_EXT_CTRLS: OK
	test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
	test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
	Standard Controls: 43 Private Controls: 0

Format ioctls:
	test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
	test VIDIOC_G/S_PARM: OK
	test VIDIOC_G_FBUF: OK (Not Supported)
	test VIDIOC_G_FMT: OK
	test VIDIOC_TRY_FMT: OK
	test VIDIOC_S_FMT: OK
	test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
	test Cropping: OK
	test Composing: OK (Not Supported)
	test Scaling: OK (Not Supported)

Codec ioctls:
	test VIDIOC_(TRY_)ENCODER_CMD: OK
	test VIDIOC_G_ENC_INDEX: OK (Not Supported)
	test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)

Buffer ioctls:
	test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
	test CREATE_BUFS maximum buffers: OK
	test VIDIOC_REMOVE_BUFS: OK
	test VIDIOC_EXPBUF: OK
	test Requests: OK (Not Supported)
	test blocking wait: OK

Total for iris_driver device /dev/video1: 48, Succeeded: 48, Failed: 0, Warnings: 0

-------------------------------

H264:
|Test|FFmpeg-H.264-v4l2m2m|
|-|-|
|TOTAL|36/135|
|TOTAL TIME|23.574s|
|-|-|
|AUD_MW_E|Pass|
|BA1_FT_C|Fail|
|BA1_Sony_D|Pass|
|BA2_Sony_F|Pass|
|BA3_SVA_C|Error|
|BA_MW_D|Fail|
|BAMQ1_JVC_C|Fail|
|BAMQ2_JVC_C|Fail|
|BANM_MW_D|Fail|
|BASQP1_Sony_C|Fail|
|CABA1_Sony_D|Fail|
|CABA1_SVA_B|Pass|
|CABA2_Sony_E|Pass|
|CABA2_SVA_B|Pass|
|CABA3_Sony_C|Fail|
|CABA3_SVA_B|Pass|
|CABA3_TOSHIBA_E|Fail|
|cabac_mot_fld0_full|Fail|
|cabac_mot_frm0_full|Pass|
|cabac_mot_mbaff0_full|Fail|
|cabac_mot_picaff0_full|Fail|
|CABACI3_Sony_B|Pass|
|CABAST3_Sony_E|Pass|
|CABASTBR3_Sony_B|Pass|
|CABREF3_Sand_D|Fail|
|CACQP3_Sony_D|Pass|
|CAFI1_SVA_C|Fail|
|CAMA1_Sony_C|Fail|
|CAMA1_TOSHIBA_B|Fail|
|cama1_vtc_c|Fail|
|cama2_vtc_b|Fail|
|CAMA3_Sand_E|Fail|
|cama3_vtc_b|Fail|
|CAMACI3_Sony_C|Fail|
|CAMANL1_TOSHIBA_B|Fail|
|CAMANL2_TOSHIBA_B|Fail|
|CAMANL3_Sand_E|Fail|
|CAMASL3_Sony_B|Fail|
|CAMP_MOT_MBAFF_L30|Fail|
|CAMP_MOT_MBAFF_L31|Fail|
|CANL1_Sony_E|Pass|
|CANL1_SVA_B|Pass|
|CANL1_TOSHIBA_G|Fail|
|CANL2_Sony_E|Fail|
|CANL2_SVA_B|Fail|
|CANL3_Sony_C|Fail|
|CANL3_SVA_B|Fail|
|CANL4_SVA_B|Fail|
|CANLMA2_Sony_C|Fail|
|CANLMA3_Sony_C|Fail|
|CAPA1_TOSHIBA_B|Fail|
|CAPAMA3_Sand_F|Fail|
|CAPCM1_Sand_E|Pass|
|CAPCMNL1_Sand_E|Fail|
|CAPM3_Sony_D|Fail|
|CAQP1_Sony_B|Pass|
|cavlc_mot_fld0_full_B|Fail|
|cavlc_mot_frm0_full_B|Pass|
|cavlc_mot_mbaff0_full_B|Fail|
|cavlc_mot_picaff0_full_B|Fail|
|CAWP1_TOSHIBA_E|Pass|
|CAWP5_TOSHIBA_E|Pass|
|CI1_FT_B|Pass|
|CI_MW_D|Pass|
|CVBS3_Sony_C|Pass|
|CVCANLMA2_Sony_C|Fail|
|CVFC1_Sony_C|Fail|
|CVFI1_Sony_D|Fail|
|CVFI1_SVA_C|Fail|
|CVFI2_Sony_H|Fail|
|CVFI2_SVA_C|Fail|
|CVMA1_Sony_D|Fail|
|CVMA1_TOSHIBA_B|Fail|
|CVMANL1_TOSHIBA_B|Fail|
|CVMANL2_TOSHIBA_B|Fail|
|CVMAPAQP3_Sony_E|Fail|
|CVMAQP2_Sony_G|Fail|
|CVMAQP3_Sony_D|Fail|
|CVMP_MOT_FLD_L30_B|Fail|
|CVMP_MOT_FRM_L31_B|Fail|
|CVNLFI1_Sony_C|Fail|
|CVNLFI2_Sony_H|Fail|
|CVPA1_TOSHIBA_B|Fail|
|CVPCMNL1_SVA_C|Fail|
|CVPCMNL2_SVA_C|Pass|
|CVSE2_Sony_B|Fail|
|CVSE3_Sony_H|Pass|
|CVSEFDFT3_Sony_E|Fail|
|CVWP1_TOSHIBA_E|Fail|
|CVWP2_TOSHIBA_E|Pass|
|CVWP3_TOSHIBA_E|Pass|
|CVWP5_TOSHIBA_E|Fail|
|FI1_Sony_E|Fail|
|FM1_BT_B|Error|
|FM1_FT_E|Error|
|FM2_SVA_C|Error|
|HCBP1_HHI_A|Pass|
|HCBP2_HHI_A|Fail|
|HCMP1_HHI_A|Fail|
|LS_SVA_D|Fail|
|MIDR_MW_D|Fail|
|MPS_MW_A|Pass|
|MR1_BT_A|Pass|
|MR1_MW_A|Fail|
|MR2_MW_A|Fail|
|MR2_TANDBERG_E|Pass|
|MR3_TANDBERG_B|Fail|
|MR4_TANDBERG_C|Fail|
|MR5_TANDBERG_C|Fail|
|MR6_BT_B|Error|
|MR7_BT_B|Error|
|MR8_BT_B|Error|
|MR9_BT_B|Fail|
|MV1_BRCM_D|Pass|
|NL1_Sony_D|Fail|
|NL2_Sony_H|Pass|
|NL3_SVA_E|Fail|
|NLMQ1_JVC_C|Fail|
|NLMQ2_JVC_C|Pass|
|NRF_MW_E|Fail|
|Sharp_MP_Field_1_B|Fail|
|Sharp_MP_Field_2_B|Fail|
|Sharp_MP_Field_3_B|Fail|
|Sharp_MP_PAFF_1r2|Fail|
|Sharp_MP_PAFF_2r|Fail|
|SL1_SVA_B|Pass|
|SP1_BT_A|Error|
|sp2_bt_b|Error|
|SVA_BA1_B|Pass|
|SVA_BA2_D|Pass|
|SVA_Base_B|Fail|
|SVA_CL1_E|Fail|
|SVA_FM1_E|Fail|
|SVA_NL1_B|Fail|
|SVA_NL2_E|Fail|
|-|-|
|Test|FFmpeg-H.264-v4l2m2m|
|TOTAL|36/135|
|TOTAL TIME|23.574s|

|-|-|
|Profile|FFmpeg-H.264-v4l2m2m|
|CONSTRAINED_BASELINE|12/33|
|BASELINE|1/7|
|EXTENDED|0/6|
|MAIN|23/89|

|TOTALS|FFmpeg-H.264-v4l2m2m|
|-|-|
|TOTAL|36/135|
|TOTAL TIME|23.574s|
|-|-|
|Profile|FFmpeg-H.264-v4l2m2m|
|BASELINE|1/7|
|CONSTRAINED_BASELINE|12/33|
|EXTENDED|0/6|
|MAIN|23/89|
|-|-|

-------------------------------

|Test|FFmpeg-H.265-v4l2m2m|
|-|-|
|TOTAL|109/147|
|TOTAL TIME|38.547s|
|-|-|
|AMP_A_Samsung_7|Pass|
|AMP_B_Samsung_7|Pass|
|AMP_D_Hisilicon_3|Pass|
|AMP_E_Hisilicon_3|Pass|
|AMP_F_Hisilicon_3|Pass|
|AMVP_A_MTK_4|Pass|
|AMVP_B_MTK_4|Fail|
|AMVP_C_Samsung_7|Pass|
|BUMPING_A_ericsson_1|Fail|
|CAINIT_A_SHARP_4|Pass|
|CAINIT_B_SHARP_4|Pass|
|CAINIT_C_SHARP_3|Pass|
|CAINIT_D_SHARP_3|Pass|
|CAINIT_E_SHARP_3|Pass|
|CAINIT_F_SHARP_3|Pass|
|CAINIT_G_SHARP_3|Pass|
|CAINIT_H_SHARP_3|Pass|
|CIP_A_Panasonic_3|Pass|
|cip_B_NEC_3|Pass|
|CIP_C_Panasonic_2|Pass|
|CONFWIN_A_Sony_1|Fail|
|DBLK_A_MAIN10_VIXS_4|Fail|
|DBLK_A_SONY_3|Pass|
|DBLK_B_SONY_3|Pass|
|DBLK_C_SONY_3|Pass|
|DBLK_D_VIXS_2|Pass|
|DBLK_E_VIXS_2|Pass|
|DBLK_F_VIXS_2|Pass|
|DBLK_G_VIXS_2|Pass|
|DELTAQP_A_BRCM_4|Pass|
|DELTAQP_B_SONY_3|Pass|
|DELTAQP_C_SONY_3|Pass|
|DSLICE_A_HHI_5|Pass|
|DSLICE_B_HHI_5|Pass|
|DSLICE_C_HHI_5|Pass|
|ENTP_A_QUALCOMM_1|Pass|
|ENTP_B_Qualcomm_1|Pass|
|ENTP_C_Qualcomm_1|Pass|
|EXT_A_ericsson_4|Pass|
|FILLER_A_Sony_1|Pass|
|HRD_A_Fujitsu_3|Pass|
|INITQP_A_Sony_1|Pass|
|INITQP_B_Main10_Sony_1|Fail|
|ipcm_A_NEC_3|Fail|
|ipcm_B_NEC_3|Pass|
|ipcm_C_NEC_3|Pass|
|ipcm_D_NEC_3|Pass|
|ipcm_E_NEC_2|Pass|
|IPRED_A_docomo_2|Pass|
|IPRED_B_Nokia_3|Pass|
|IPRED_C_Mitsubishi_3|Pass|
|LS_A_Orange_2|Pass|
|LS_B_Orange_4|Pass|
|LTRPSPS_A_Qualcomm_1|Fail|
|MAXBINS_A_TI_5|Pass|
|MAXBINS_B_TI_5|Pass|
|MAXBINS_C_TI_5|Pass|
|MERGE_A_TI_3|Pass|
|MERGE_B_TI_3|Pass|
|MERGE_C_TI_3|Fail|
|MERGE_D_TI_3|Fail|
|MERGE_E_TI_3|Pass|
|MERGE_F_MTK_4|Pass|
|MERGE_G_HHI_4|Pass|
|MVCLIP_A_qualcomm_3|Fail|
|MVDL1ZERO_A_docomo_4|Pass|
|MVEDGE_A_qualcomm_3|Fail|
|NoOutPrior_A_Qualcomm_1|Fail|
|NoOutPrior_B_Qualcomm_1|Fail|
|NUT_A_ericsson_5|Fail|
|OPFLAG_A_Qualcomm_1|Pass|
|OPFLAG_B_Qualcomm_1|Fail|
|OPFLAG_C_Qualcomm_1|Fail|
|PICSIZE_A_Bossen_1|Error|
|PICSIZE_B_Bossen_1|Error|
|PICSIZE_C_Bossen_1|Error|
|PICSIZE_D_Bossen_1|Error|
|PMERGE_A_TI_3|Pass|
|PMERGE_B_TI_3|Pass|
|PMERGE_C_TI_3|Pass|
|PMERGE_D_TI_3|Pass|
|PMERGE_E_TI_3|Pass|
|POC_A_Bossen_3|Pass|
|PPS_A_qualcomm_7|Pass|
|PS_B_VIDYO_3|Pass|
|RAP_A_docomo_6|Fail|
|RAP_B_Bossen_2|Fail|
|RPLM_A_qualcomm_4|Pass|
|RPLM_B_qualcomm_4|Pass|
|RPS_A_docomo_5|Pass|
|RPS_B_qualcomm_5|Pass|
|RPS_C_ericsson_5|Pass|
|RPS_D_ericsson_6|Pass|
|RPS_E_qualcomm_5|Pass|
|RPS_F_docomo_2|Pass|
|RQT_A_HHI_4|Pass|
|RQT_B_HHI_4|Pass|
|RQT_C_HHI_4|Pass|
|RQT_D_HHI_4|Pass|
|RQT_E_HHI_4|Pass|
|RQT_F_HHI_4|Pass|
|RQT_G_HHI_4|Pass|
|SAO_A_MediaTek_4|Fail|
|SAO_B_MediaTek_5|Pass|
|SAO_C_Samsung_5|Pass|
|SAO_D_Samsung_5|Pass|
|SAO_E_Canon_4|Pass|
|SAO_F_Canon_3|Pass|
|SAO_G_Canon_3|Pass|
|SAO_H_Parabola_1|Pass|
|SAODBLK_A_MainConcept_4|Pass|
|SAODBLK_B_MainConcept_4|Pass|
|SDH_A_Orange_4|Pass|
|SLICES_A_Rovi_3|Pass|
|SLIST_A_Sony_5|Pass|
|SLIST_B_Sony_9|Pass|
|SLIST_C_Sony_4|Pass|
|SLIST_D_Sony_9|Pass|
|SLPPLP_A_VIDYO_2|Pass|
|STRUCT_A_Samsung_7|Pass|
|STRUCT_B_Samsung_7|Pass|
|TILES_A_Cisco_2|Pass|
|TILES_B_Cisco_1|Pass|
|TMVP_A_MS_3|Pass|
|TSCL_A_VIDYO_5|Fail|
|TSCL_B_VIDYO_4|Pass|
|TSKIP_A_MS_3|Pass|
|TSUNEQBD_A_MAIN10_Technicolor_2|Error|
|TUSIZE_A_Samsung_1|Pass|
|VPSID_A_VIDYO_2|Pass|
|VPSSPSPPS_A_MainConcept_1|Fail|
|WP_A_MAIN10_Toshiba_3|Fail|
|WP_A_Toshiba_3|Pass|
|WP_B_Toshiba_3|Pass|
|WP_MAIN10_B_Toshiba_3|Fail|
|WPP_A_ericsson_MAIN10_2|Fail|
|WPP_A_ericsson_MAIN_2|Pass|
|WPP_B_ericsson_MAIN10_2|Fail|
|WPP_B_ericsson_MAIN_2|Fail|
|WPP_C_ericsson_MAIN10_2|Fail|
|WPP_C_ericsson_MAIN_2|Fail|
|WPP_D_ericsson_MAIN10_2|Error|
|WPP_D_ericsson_MAIN_2|Error|
|WPP_E_ericsson_MAIN10_2|Fail|
|WPP_E_ericsson_MAIN_2|Fail|
|WPP_F_ericsson_MAIN10_2|Fail|
|WPP_F_ericsson_MAIN_2|Pass|
|-|-|
|Test|FFmpeg-H.265-v4l2m2m|
|TOTAL|109/147|
|TOTAL TIME|38.547s|

|-|-|
|Profile|FFmpeg-H.265-v4l2m2m|
|MAIN|108/135|
|MAIN_10|0/11|
|MAIN_STILL_PICTURE|1/1|

|TOTALS|FFmpeg-H.265-v4l2m2m|
|-|-|
|TOTAL|109/147|
|TOTAL TIME|38.547s|
|-|-|
|Profile|FFmpeg-H.265-v4l2m2m|
|MAIN|108/135|
|MAIN_10|0/11|
|MAIN_STILL_PICTURE|1/1|
|-|-|

-------------------------------

|Test|FFmpeg-VP9-v4l2m2m|
|-|-|
|TOTAL|111/305|
|TOTAL TIME|77.260s|
|-|-|
|vp90-2-00-quantizer-00.webm|Pass|
|vp90-2-00-quantizer-01.webm|Pass|
|vp90-2-00-quantizer-02.webm|Pass|
|vp90-2-00-quantizer-03.webm|Fail|
|vp90-2-00-quantizer-04.webm|Fail|
|vp90-2-00-quantizer-05.webm|Pass|
|vp90-2-00-quantizer-06.webm|Pass|
|vp90-2-00-quantizer-07.webm|Pass|
|vp90-2-00-quantizer-08.webm|Fail|
|vp90-2-00-quantizer-09.webm|Pass|
|vp90-2-00-quantizer-10.webm|Pass|
|vp90-2-00-quantizer-11.webm|Pass|
|vp90-2-00-quantizer-12.webm|Pass|
|vp90-2-00-quantizer-13.webm|Pass|
|vp90-2-00-quantizer-14.webm|Pass|
|vp90-2-00-quantizer-15.webm|Pass|
|vp90-2-00-quantizer-16.webm|Fail|
|vp90-2-00-quantizer-17.webm|Pass|
|vp90-2-00-quantizer-18.webm|Pass|
|vp90-2-00-quantizer-19.webm|Pass|
|vp90-2-00-quantizer-20.webm|Pass|
|vp90-2-00-quantizer-21.webm|Pass|
|vp90-2-00-quantizer-22.webm|Pass|
|vp90-2-00-quantizer-23.webm|Pass|
|vp90-2-00-quantizer-24.webm|Pass|
|vp90-2-00-quantizer-25.webm|Fail|
|vp90-2-00-quantizer-26.webm|Fail|
|vp90-2-00-quantizer-27.webm|Pass|
|vp90-2-00-quantizer-28.webm|Pass|
|vp90-2-00-quantizer-29.webm|Fail|
|vp90-2-00-quantizer-30.webm|Pass|
|vp90-2-00-quantizer-31.webm|Pass|
|vp90-2-00-quantizer-32.webm|Fail|
|vp90-2-00-quantizer-33.webm|Pass|
|vp90-2-00-quantizer-34.webm|Pass|
|vp90-2-00-quantizer-35.webm|Pass|
|vp90-2-00-quantizer-36.webm|Pass|
|vp90-2-00-quantizer-37.webm|Pass|
|vp90-2-00-quantizer-38.webm|Pass|
|vp90-2-00-quantizer-39.webm|Pass|
|vp90-2-00-quantizer-40.webm|Pass|
|vp90-2-00-quantizer-41.webm|Pass|
|vp90-2-00-quantizer-42.webm|Pass|
|vp90-2-00-quantizer-43.webm|Pass|
|vp90-2-00-quantizer-44.webm|Fail|
|vp90-2-00-quantizer-45.webm|Pass|
|vp90-2-00-quantizer-46.webm|Pass|
|vp90-2-00-quantizer-47.webm|Pass|
|vp90-2-00-quantizer-48.webm|Pass|
|vp90-2-00-quantizer-49.webm|Pass|
|vp90-2-00-quantizer-50.webm|Fail|
|vp90-2-00-quantizer-51.webm|Pass|
|vp90-2-00-quantizer-52.webm|Pass|
|vp90-2-00-quantizer-53.webm|Pass|
|vp90-2-00-quantizer-54.webm|Pass|
|vp90-2-00-quantizer-55.webm|Pass|
|vp90-2-00-quantizer-56.webm|Pass|
|vp90-2-00-quantizer-57.webm|Pass|
|vp90-2-00-quantizer-58.webm|Pass|
|vp90-2-00-quantizer-59.webm|Fail|
|vp90-2-00-quantizer-60.webm|Pass|
|vp90-2-00-quantizer-61.webm|Pass|
|vp90-2-00-quantizer-62.webm|Pass|
|vp90-2-00-quantizer-63.webm|Fail|
|vp90-2-01-sharpness-1.webm|Pass|
|vp90-2-01-sharpness-2.webm|Pass|
|vp90-2-01-sharpness-3.webm|Pass|
|vp90-2-01-sharpness-4.webm|Pass|
|vp90-2-01-sharpness-5.webm|Pass|
|vp90-2-01-sharpness-6.webm|Pass|
|vp90-2-01-sharpness-7.webm|Pass|
|vp90-2-02-size-08x08.webm|Error|
|vp90-2-02-size-08x10.webm|Error|
|vp90-2-02-size-08x16.webm|Error|
|vp90-2-02-size-08x18.webm|Error|
|vp90-2-02-size-08x32.webm|Error|
|vp90-2-02-size-08x34.webm|Error|
|vp90-2-02-size-08x64.webm|Error|
|vp90-2-02-size-08x66.webm|Error|
|vp90-2-02-size-10x08.webm|Error|
|vp90-2-02-size-10x10.webm|Error|
|vp90-2-02-size-10x16.webm|Error|
|vp90-2-02-size-10x18.webm|Error|
|vp90-2-02-size-10x32.webm|Error|
|vp90-2-02-size-10x34.webm|Error|
|vp90-2-02-size-10x64.webm|Error|
|vp90-2-02-size-10x66.webm|Error|
|vp90-2-02-size-130x132.webm|Fail|
|vp90-2-02-size-132x130.webm|Pass|
|vp90-2-02-size-132x132.webm|Pass|
|vp90-2-02-size-16x08.webm|Error|
|vp90-2-02-size-16x10.webm|Error|
|vp90-2-02-size-16x16.webm|Error|
|vp90-2-02-size-16x18.webm|Error|
|vp90-2-02-size-16x32.webm|Error|
|vp90-2-02-size-16x34.webm|Error|
|vp90-2-02-size-16x64.webm|Error|
|vp90-2-02-size-16x66.webm|Error|
|vp90-2-02-size-178x180.webm|Fail|
|vp90-2-02-size-180x178.webm|Pass|
|vp90-2-02-size-180x180.webm|Fail|
|vp90-2-02-size-18x08.webm|Error|
|vp90-2-02-size-18x10.webm|Error|
|vp90-2-02-size-18x16.webm|Error|
|vp90-2-02-size-18x18.webm|Error|
|vp90-2-02-size-18x32.webm|Error|
|vp90-2-02-size-18x34.webm|Error|
|vp90-2-02-size-18x64.webm|Error|
|vp90-2-02-size-18x66.webm|Error|
|vp90-2-02-size-32x08.webm|Error|
|vp90-2-02-size-32x10.webm|Error|
|vp90-2-02-size-32x16.webm|Error|
|vp90-2-02-size-32x18.webm|Error|
|vp90-2-02-size-32x32.webm|Error|
|vp90-2-02-size-32x34.webm|Error|
|vp90-2-02-size-32x64.webm|Error|
|vp90-2-02-size-32x66.webm|Error|
|vp90-2-02-size-34x08.webm|Error|
|vp90-2-02-size-34x10.webm|Error|
|vp90-2-02-size-34x16.webm|Error|
|vp90-2-02-size-34x18.webm|Error|
|vp90-2-02-size-34x32.webm|Error|
|vp90-2-02-size-34x34.webm|Error|
|vp90-2-02-size-34x64.webm|Error|
|vp90-2-02-size-34x66.webm|Error|
|vp90-2-02-size-64x08.webm|Error|
|vp90-2-02-size-64x10.webm|Error|
|vp90-2-02-size-64x16.webm|Error|
|vp90-2-02-size-64x18.webm|Error|
|vp90-2-02-size-64x32.webm|Error|
|vp90-2-02-size-64x34.webm|Error|
|vp90-2-02-size-64x64.webm|Error|
|vp90-2-02-size-64x66.webm|Error|
|vp90-2-02-size-66x08.webm|Error|
|vp90-2-02-size-66x10.webm|Error|
|vp90-2-02-size-66x16.webm|Error|
|vp90-2-02-size-66x18.webm|Error|
|vp90-2-02-size-66x32.webm|Error|
|vp90-2-02-size-66x34.webm|Error|
|vp90-2-02-size-66x64.webm|Error|
|vp90-2-02-size-66x66.webm|Error|
|vp90-2-02-size-lf-1920x1080.webm|Fail|
|vp90-2-03-deltaq.webm|Fail|
|vp90-2-03-size-196x196.webm|Pass|
|vp90-2-03-size-196x198.webm|Pass|
|vp90-2-03-size-196x200.webm|Pass|
|vp90-2-03-size-196x202.webm|Pass|
|vp90-2-03-size-196x208.webm|Fail|
|vp90-2-03-size-196x210.webm|Fail|
|vp90-2-03-size-196x224.webm|Pass|
|vp90-2-03-size-196x226.webm|Fail|
|vp90-2-03-size-198x196.webm|Fail|
|vp90-2-03-size-198x198.webm|Pass|
|vp90-2-03-size-198x200.webm|Pass|
|vp90-2-03-size-198x202.webm|Pass|
|vp90-2-03-size-198x208.webm|Pass|
|vp90-2-03-size-198x210.webm|Fail|
|vp90-2-03-size-198x224.webm|Pass|
|vp90-2-03-size-198x226.webm|Fail|
|vp90-2-03-size-200x196.webm|Fail|
|vp90-2-03-size-200x198.webm|Fail|
|vp90-2-03-size-200x200.webm|Fail|
|vp90-2-03-size-200x202.webm|Pass|
|vp90-2-03-size-200x208.webm|Fail|
|vp90-2-03-size-200x210.webm|Fail|
|vp90-2-03-size-200x224.webm|Pass|
|vp90-2-03-size-200x226.webm|Fail|
|vp90-2-03-size-202x196.webm|Fail|
|vp90-2-03-size-202x198.webm|Fail|
|vp90-2-03-size-202x200.webm|Fail|
|vp90-2-03-size-202x202.webm|Fail|
|vp90-2-03-size-202x208.webm|Pass|
|vp90-2-03-size-202x210.webm|Fail|
|vp90-2-03-size-202x224.webm|Fail|
|vp90-2-03-size-202x226.webm|Pass|
|vp90-2-03-size-208x196.webm|Pass|
|vp90-2-03-size-208x198.webm|Pass|
|vp90-2-03-size-208x200.webm|Pass|
|vp90-2-03-size-208x202.webm|Pass|
|vp90-2-03-size-208x208.webm|Pass|
|vp90-2-03-size-208x210.webm|Pass|
|vp90-2-03-size-208x224.webm|Pass|
|vp90-2-03-size-208x226.webm|Pass|
|vp90-2-03-size-210x196.webm|Pass|
|vp90-2-03-size-210x198.webm|Pass|
|vp90-2-03-size-210x200.webm|Fail|
|vp90-2-03-size-210x202.webm|Pass|
|vp90-2-03-size-210x208.webm|Pass|
|vp90-2-03-size-210x210.webm|Fail|
|vp90-2-03-size-210x224.webm|Pass|
|vp90-2-03-size-210x226.webm|Fail|
|vp90-2-03-size-224x196.webm|Fail|
|vp90-2-03-size-224x198.webm|Pass|
|vp90-2-03-size-224x200.webm|Pass|
|vp90-2-03-size-224x202.webm|Fail|
|vp90-2-03-size-224x208.webm|Pass|
|vp90-2-03-size-224x210.webm|Fail|
|vp90-2-03-size-224x224.webm|Pass|
|vp90-2-03-size-224x226.webm|Pass|
|vp90-2-03-size-226x196.webm|Pass|
|vp90-2-03-size-226x198.webm|Fail|
|vp90-2-03-size-226x200.webm|Fail|
|vp90-2-03-size-226x202.webm|Fail|
|vp90-2-03-size-226x208.webm|Pass|
|vp90-2-03-size-226x210.webm|Pass|
|vp90-2-03-size-226x224.webm|Fail|
|vp90-2-03-size-226x226.webm|Fail|
|vp90-2-03-size-352x288.webm|Pass|
|vp90-2-05-resize.ivf|Fail|
|vp90-2-06-bilinear.webm|Pass|
|vp90-2-07-frame_parallel-1.webm|Pass|
|vp90-2-07-frame_parallel.webm|Fail|
|vp90-2-08-tile_1x2_frame_parallel.webm|Fail|
|vp90-2-08-tile_1x2.webm|Fail|
|vp90-2-08-tile_1x4_frame_parallel.webm|Fail|
|vp90-2-08-tile_1x4.webm|Fail|
|vp90-2-08-tile_1x8_frame_parallel.webm|Pass|
|vp90-2-08-tile_1x8.webm|Pass|
|vp90-2-08-tile-4x1.webm|Pass|
|vp90-2-08-tile-4x4.webm|Pass|
|vp90-2-09-aq2.webm|Fail|
|vp90-2-09-lf_deltas.webm|Fail|
|vp90-2-09-subpixel-00.ivf|Fail|
|vp90-2-10-show-existing-frame2.webm|Fail|
|vp90-2-10-show-existing-frame.webm|Fail|
|vp90-2-11-size-351x287.webm|Fail|
|vp90-2-11-size-351x288.webm|Fail|
|vp90-2-11-size-352x287.webm|Fail|
|vp90-2-12-droppable_1.ivf|Pass|
|vp90-2-12-droppable_2.ivf|Pass|
|vp90-2-12-droppable_3.ivf|Pass|
|vp90-2-14-resize-10frames-fp-tiles-1-2-4-8.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-1-2.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-1-4.webm|Fail|
|vp90-2-14-resize-10frames-fp-tiles-1-8.webm|Fail|
|vp90-2-14-resize-10frames-fp-tiles-2-1.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-2-4.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-2-8.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-4-1.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-4-2.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-4-8.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-8-1.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-8-2.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-8-4-2-1.webm|Timeout|
|vp90-2-14-resize-10frames-fp-tiles-8-4.webm|Timeout|
|vp90-2-14-resize-fp-tiles-1-16.webm|Fail|
|vp90-2-14-resize-fp-tiles-1-2-4-8-16.webm|Timeout|
|vp90-2-14-resize-fp-tiles-1-2.webm|Fail|
|vp90-2-14-resize-fp-tiles-1-4.webm|Timeout|
|vp90-2-14-resize-fp-tiles-16-1.webm|Error|
|vp90-2-14-resize-fp-tiles-16-2.webm|Error|
|vp90-2-14-resize-fp-tiles-16-4.webm|Error|
|vp90-2-14-resize-fp-tiles-16-8-4-2-1.webm|Error|
|vp90-2-14-resize-fp-tiles-16-8.webm|Error|
|vp90-2-14-resize-fp-tiles-1-8.webm|Fail|
|vp90-2-14-resize-fp-tiles-2-16.webm|Error|
|vp90-2-14-resize-fp-tiles-2-1.webm|Fail|
|vp90-2-14-resize-fp-tiles-2-4.webm|Fail|
|vp90-2-14-resize-fp-tiles-2-8.webm|Timeout|
|vp90-2-14-resize-fp-tiles-4-16.webm|Error|
|vp90-2-14-resize-fp-tiles-4-1.webm|Timeout|
|vp90-2-14-resize-fp-tiles-4-2.webm|Timeout|
|vp90-2-14-resize-fp-tiles-4-8.webm|Fail|
|vp90-2-14-resize-fp-tiles-8-16.webm|Error|
|vp90-2-14-resize-fp-tiles-8-1.webm|Timeout|
|vp90-2-14-resize-fp-tiles-8-2.webm|Timeout|
|vp90-2-14-resize-fp-tiles-8-4.webm|Timeout|
|vp90-2-15-segkey_adpq.webm|Fail|
|vp90-2-15-segkey.webm|Pass|
|vp90-2-16-intra-only.webm|Fail|
|vp90-2-17-show-existing-frame.webm|Pass|
|vp90-2-18-resize.ivf|Fail|
|vp90-2-19-skip-01.webm|Fail|
|vp90-2-19-skip-02.webm|Fail|
|vp90-2-19-skip.webm|Pass|
|vp90-2-20-big_superframe-01.webm|Fail|
|vp90-2-20-big_superframe-02.webm|Fail|
|vp90-2-21-resize_inter_1280x720_5_1-2.webm|Timeout|
|vp90-2-21-resize_inter_1280x720_5_3-4.webm|Timeout|
|vp90-2-21-resize_inter_1280x720_7_1-2.webm|Fail|
|vp90-2-21-resize_inter_1280x720_7_3-4.webm|Timeout|
|vp90-2-21-resize_inter_1920x1080_5_1-2.webm|Timeout|
|vp90-2-21-resize_inter_1920x1080_5_3-4.webm|Timeout|
|vp90-2-21-resize_inter_1920x1080_7_1-2.webm|Timeout|
|vp90-2-21-resize_inter_1920x1080_7_3-4.webm|Timeout|
|vp90-2-21-resize_inter_320x180_5_1-2.webm|Fail|
|vp90-2-21-resize_inter_320x180_5_3-4.webm|Fail|
|vp90-2-21-resize_inter_320x180_7_1-2.webm|Fail|
|vp90-2-21-resize_inter_320x180_7_3-4.webm|Fail|
|vp90-2-21-resize_inter_320x240_5_1-2.webm|Timeout|
|vp90-2-21-resize_inter_320x240_5_3-4.webm|Fail|
|vp90-2-21-resize_inter_320x240_7_1-2.webm|Fail|
|vp90-2-21-resize_inter_320x240_7_3-4.webm|Timeout|
|vp90-2-21-resize_inter_640x360_5_1-2.webm|Fail|
|vp90-2-21-resize_inter_640x360_5_3-4.webm|Timeout|
|vp90-2-21-resize_inter_640x360_7_1-2.webm|Fail|
|vp90-2-21-resize_inter_640x360_7_3-4.webm|Fail|
|vp90-2-21-resize_inter_640x480_5_1-2.webm|Timeout|
|vp90-2-21-resize_inter_640x480_5_3-4.webm|Fail|
|vp90-2-21-resize_inter_640x480_7_1-2.webm|Timeout|
|vp90-2-21-resize_inter_640x480_7_3-4.webm|Timeout|
|vp90-2-22-svc_1280x720_1.webm|Pass|
|vp90-2-22-svc_1280x720_3.ivf|Timeout|
|vp91-2-04-yuv422.webm|Error|
|vp91-2-04-yuv444.webm|Error|
|-|-|
|Test|FFmpeg-VP9-v4l2m2m|
|TOTAL|111/305|
|TOTAL TIME|77.260s|

|TOTALS|FFmpeg-VP9-v4l2m2m|
|-|-|
|TOTAL|111/305|
|TOTAL TIME|77.260s|
|-|-|

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
Alexander Koskovich (3):
      dt-bindings: media: qcom,milos-iris: Add Milos video codec
      media: iris: Add support for Milos (VPU v2.0)
      arm64: dts: qcom: milos: Add Iris VPU v2.0

 .../devicetree/bindings/media/qcom,milos-iris.yaml | 166 ++++++
 arch/arm64/boot/dts/qcom/milos.dtsi                |  85 +++
 .../platform/qcom/iris/iris_platform_common.h      |   1 +
 .../media/platform/qcom/iris/iris_platform_gen2.c  | 106 ++++
 .../media/platform/qcom/iris/iris_platform_milos.h | 655 +++++++++++++++++++++
 drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
 6 files changed, 1017 insertions(+)
---
base-commit: 591cd656a1bf5ea94a222af5ef2ee76df029c1d2
change-id: 20260406-milos-iris-d1a854e4cb75

Best regards,
-- 
Alexander Koskovich <akoskovich@pm.me>

[PATCH 1/3] dt-bindings: media: qcom,milos-iris: Add Milos video codec

[Alexander Koskovich]

Add binding for Qualcomm Milos Iris video codec.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 .../devicetree/bindings/media/qcom,milos-iris.yaml | 166 +++++++++++++++++++++
 1 file changed, 166 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml b/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml
new file mode 100644
index 000000000000..36f49590d7b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,milos-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Milos SoC Iris video encoder and decoder
+
+maintainers:
+  - Alexander Koskovich <akoskovich@pm.me>
+
+description:
+  The Iris video processing unit on Qualcomm Milos SoC is a video encode and
+  decode accelerator.
+
+properties:
+  compatible:
+    enum:
+      - qcom,milos-iris
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: iface
+      - const: core
+      - const: vcodec0_core
+
+  dma-coherent: true
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: cpu-cfg
+      - const: video-mem
+
+  iommus:
+    maxItems: 2
+
+  operating-points-v2: true
+  opp-table:
+    type: object
+
+  power-domains:
+    maxItems: 4
+
+  power-domain-names:
+    items:
+      - const: venus
+      - const: vcodec0
+      - const: cx
+      - const: mx
+
+  resets:
+    maxItems: 2
+
+  reset-names:
+    items:
+      - const: bus
+      - const: core
+
+required:
+  - compatible
+  - dma-coherent
+  - interconnects
+  - interconnect-names
+  - iommus
+  - power-domain-names
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: qcom,venus-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,milos-gcc.h>
+    #include <dt-bindings/clock/qcom,milos-videocc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,milos-rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    video-codec@aa00000 {
+        compatible = "qcom,milos-iris";
+        reg = <0x0aa00000 0xf0000>;
+
+        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+                 <&videocc VIDEO_CC_MVS0C_CLK>,
+                 <&videocc VIDEO_CC_MVS0_CLK>;
+        clock-names = "iface",
+                      "core",
+                      "vcodec0_core";
+
+        dma-coherent;
+        iommus = <&apps_smmu 0x1960 0>,
+                 <&apps_smmu 0x1967 0>;
+
+        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                         &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                        <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
+                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+        interconnect-names = "cpu-cfg",
+                             "video-mem";
+
+        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+        operating-points-v2 = <&iris_opp_table>;
+
+        memory-region = <&video_mem>;
+
+        power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+                        <&videocc VIDEO_CC_MVS0_GDSC>,
+                        <&rpmhpd RPMHPD_CX>,
+                        <&rpmhpd RPMHPD_MX>;
+        power-domain-names = "venus",
+                             "vcodec0",
+                             "cx",
+                             "mx";
+
+        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+                 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+        reset-names = "bus",
+                      "core";
+
+        iris_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-240000000 {
+                opp-hz = /bits/ 64 <240000000>;
+                required-opps = <&rpmhpd_opp_low_svs>,
+                                <&rpmhpd_opp_low_svs>;
+            };
+
+            opp-338000000 {
+                opp-hz = /bits/ 64 <338000000>;
+                required-opps = <&rpmhpd_opp_svs>,
+                                <&rpmhpd_opp_svs>;
+            };
+
+            opp-366000000 {
+                opp-hz = /bits/ 64 <366000000>;
+                required-opps = <&rpmhpd_opp_svs_l1>,
+                                <&rpmhpd_opp_svs_l1>;
+            };
+
+            opp-444000000 {
+                opp-hz = /bits/ 64 <444000000>;
+                required-opps = <&rpmhpd_opp_nom>,
+                                <&rpmhpd_opp_nom>;
+            };
+
+            opp-552000000 {
+                opp-hz = /bits/ 64 <552000000>;
+                required-opps = <&rpmhpd_opp_turbo>,
+                                <&rpmhpd_opp_turbo>;
+            };
+        };
+    };

-- 
2.53.0

Re: [PATCH 1/3] dt-bindings: media: qcom,milos-iris: Add Milos video codec

[Krzysztof Kozlowski]

On Mon, Apr 06, 2026 at 10:19:34AM +0000, Alexander Koskovich wrote:
> Add binding for Qualcomm Milos Iris video codec.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  .../devicetree/bindings/media/qcom,milos-iris.yaml | 166 +++++++++++++++++++++
>  1 file changed, 166 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 2/3] media: iris: Add support for Milos (VPU v2.0)

[Alexander Koskovich]

Add support for the Milos Iris codec. This only supports the variant
found on the SM7635-AB that has half of it's pipes disabled via efuse.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 .../platform/qcom/iris/iris_platform_common.h      |   1 +
 .../media/platform/qcom/iris/iris_platform_gen2.c  | 106 ++++
 .../media/platform/qcom/iris/iris_platform_milos.h | 655 +++++++++++++++++++++
 drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
 4 files changed, 766 insertions(+)

diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 5a489917580e..c8a9f122952e 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -41,6 +41,7 @@ enum pipe_type {
 	PIPE_4 = 4,
 };
 
+extern const struct iris_platform_data milos_data;
 extern const struct iris_platform_data qcs8300_data;
 extern const struct iris_platform_data sc7280_data;
 extern const struct iris_platform_data sm8250_data;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 5da90d47f9c6..78cd4656b981 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -12,6 +12,7 @@
 #include "iris_vpu_buffer.h"
 #include "iris_vpu_common.h"
 
+#include "iris_platform_milos.h"
 #include "iris_platform_qcs8300.h"
 #include "iris_platform_sm8650.h"
 #include "iris_platform_sm8750.h"
@@ -1317,3 +1318,108 @@ const struct iris_platform_data qcs8300_data = {
 	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
 	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
 };
+
+/*
+ * Shares most of SM8550 data except:
+ * - vpu_ops to iris_vpu2_ops
+ * - icc_tbl to milos_icc_table
+ * - clk_rst_tbl to sm8650_clk_reset_table
+ * - opp_pd_tbl to milos_opp_pd_table
+ * - fwname to "qcom/vpu/vpu20_2v.mbn"
+ * - inst_iris_fmts to platform_fmts_milos_dec
+ * - inst_caps to platform_inst_cap_milos
+ * - inst_fw_caps_dec to inst_fw_cap_milos_dec
+ * - inst_fw_caps_enc to inst_fw_cap_milos_enc
+ * - ubwc_config to ubwc_config_milos
+ * - num_vpp_pipe to 2
+ * - max_core_mbpf scaled for 4k@30fps dec/enc
+ * - max_core_mbps scaled for 4k@30fps dec & 1080p@30 enc
+ */
+const struct iris_platform_data milos_data = {
+	.get_instance = iris_hfi_gen2_get_instance,
+	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
+	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
+	.get_vpu_buffer_size = iris_vpu_buf_size,
+	.vpu_ops = &iris_vpu2_ops,
+	.set_preset_registers = iris_set_sm8550_preset_registers,
+	.icc_tbl = milos_icc_table,
+	.icc_tbl_size = ARRAY_SIZE(milos_icc_table),
+	.clk_rst_tbl = sm8650_clk_reset_table,
+	.clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
+	.bw_tbl_dec = sm8550_bw_table_dec,
+	.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
+	.pmdomain_tbl = sm8550_pmdomain_table,
+	.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
+	.opp_pd_tbl = milos_opp_pd_table,
+	.opp_pd_tbl_size = ARRAY_SIZE(milos_opp_pd_table),
+	.clk_tbl = sm8550_clk_table,
+	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+	.opp_clk_tbl = sm8550_opp_clk_table,
+	/* Upper bound of DMA address range */
+	.dma_mask = 0xe0000000 - 1,
+	.fwname = "qcom/vpu/vpu20_2v.mbn",
+	.pas_id = IRIS_PAS_ID,
+	.inst_iris_fmts = platform_fmts_milos_dec,
+	.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_milos_dec),
+	.inst_caps = &platform_inst_cap_milos,
+	.inst_fw_caps_dec = inst_fw_cap_milos_dec,
+	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_milos_dec),
+	.inst_fw_caps_enc = inst_fw_cap_milos_enc,
+	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_milos_enc),
+	.tz_cp_config_data = tz_cp_config_sm8550,
+	.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
+	.core_arch = VIDEO_ARCH_LX,
+	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
+	.ubwc_config = &ubwc_config_milos,
+	.num_vpp_pipe = 2,
+	.max_session_count = 16,
+	.max_core_mbpf = ((4096 * 2176) / 256) * 2,
+	.max_core_mbps = ((3840 * 2176) / 256) * 30 + ((1920 * 1088) / 256) * 30,
+	.dec_input_config_params_default =
+		sm8550_vdec_input_config_params_default,
+	.dec_input_config_params_default_size =
+		ARRAY_SIZE(sm8550_vdec_input_config_params_default),
+	.dec_input_config_params_hevc =
+		sm8550_vdec_input_config_param_hevc,
+	.dec_input_config_params_hevc_size =
+		ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
+	.dec_input_config_params_vp9 =
+		sm8550_vdec_input_config_param_vp9,
+	.dec_input_config_params_vp9_size =
+		ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+	.dec_output_config_params =
+		sm8550_vdec_output_config_params,
+	.dec_output_config_params_size =
+		ARRAY_SIZE(sm8550_vdec_output_config_params),
+
+	.enc_input_config_params =
+		sm8550_venc_input_config_params,
+	.enc_input_config_params_size =
+		ARRAY_SIZE(sm8550_venc_input_config_params),
+	.enc_output_config_params =
+		sm8550_venc_output_config_params,
+	.enc_output_config_params_size =
+		ARRAY_SIZE(sm8550_venc_output_config_params),
+
+	.dec_input_prop = sm8550_vdec_subscribe_input_properties,
+	.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
+	.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
+	.dec_output_prop_avc_size =
+		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
+	.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
+	.dec_output_prop_hevc_size =
+		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
+	.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
+	.dec_output_prop_vp9_size =
+		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+
+	.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
+	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
+	.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
+	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
+
+	.enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
+	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
+	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
+	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
+};
diff --git a/drivers/media/platform/qcom/iris/iris_platform_milos.h b/drivers/media/platform/qcom/iris/iris_platform_milos.h
new file mode 100644
index 000000000000..dacd3ad5aa7e
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_milos.h
@@ -0,0 +1,655 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __IRIS_PLATFORM_MILOS_H__
+#define __IRIS_PLATFORM_MILOS_H__
+
+#define MILOS_V1_MAX_BITRATE	100000000
+#define MILOS_V1_MAX_FPS	240
+
+static struct iris_fmt platform_fmts_milos_dec[] = {
+	[IRIS_FMT_H264] = {
+		.pixfmt = V4L2_PIX_FMT_H264,
+		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+	},
+	[IRIS_FMT_HEVC] = {
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+	},
+	[IRIS_FMT_VP9] = {
+		.pixfmt = V4L2_PIX_FMT_VP9,
+		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
+	},
+};
+
+static const struct platform_inst_fw_cap inst_fw_cap_milos_dec[] = {
+	{
+		.cap_id = PROFILE_H264,
+		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
+		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+		.hfi_id = HFI_PROP_PROFILE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_u32_enum,
+	},
+	{
+		.cap_id = PROFILE_HEVC,
+		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
+		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+		.hfi_id = HFI_PROP_PROFILE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_u32_enum,
+	},
+	{
+		.cap_id = PROFILE_VP9,
+		.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
+		.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
+				BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
+		.value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
+		.hfi_id = HFI_PROP_PROFILE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_u32_enum,
+	},
+	{
+		.cap_id = LEVEL_H264,
+		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+		.max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
+		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
+		.hfi_id = HFI_PROP_LEVEL,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_u32_enum,
+	},
+	{
+		.cap_id = LEVEL_HEVC,
+		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5),
+		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
+		.hfi_id = HFI_PROP_LEVEL,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_u32_enum,
+	},
+	{
+		.cap_id = LEVEL_VP9,
+		.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
+		.max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_0,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
+				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0),
+		.value = V4L2_MPEG_VIDEO_VP9_LEVEL_5_0,
+		.hfi_id = HFI_PROP_LEVEL,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_u32_enum,
+	},
+	{
+		.cap_id = TIER,
+		.min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
+		.max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
+		.value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
+		.hfi_id = HFI_PROP_TIER,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_u32_enum,
+	},
+	{
+		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
+		.min = DEFAULT_MAX_HOST_BUF_COUNT,
+		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
+		.step_or_mask = 1,
+		.value = DEFAULT_MAX_HOST_BUF_COUNT,
+		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
+		.flags = CAP_FLAG_INPUT_PORT,
+		.set = iris_set_u32,
+	},
+	{
+		.cap_id = STAGE,
+		.min = STAGE_1,
+		.max = STAGE_2,
+		.step_or_mask = 1,
+		.value = STAGE_2,
+		.hfi_id = HFI_PROP_STAGE,
+		.set = iris_set_stage,
+	},
+	{
+		.cap_id = PIPE,
+		/* .max, .min and .value are set via platform data */
+		.step_or_mask = 1,
+		.hfi_id = HFI_PROP_PIPE,
+		.set = iris_set_pipe,
+	},
+	{
+		.cap_id = POC,
+		.min = 0,
+		.max = 2,
+		.step_or_mask = 1,
+		.value = 1,
+		.hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
+	},
+	{
+		.cap_id = CODED_FRAMES,
+		.min = CODED_FRAMES_PROGRESSIVE,
+		.max = CODED_FRAMES_PROGRESSIVE,
+		.step_or_mask = 0,
+		.value = CODED_FRAMES_PROGRESSIVE,
+		.hfi_id = HFI_PROP_CODED_FRAMES,
+	},
+	{
+		.cap_id = BIT_DEPTH,
+		.min = BIT_DEPTH_8,
+		.max = BIT_DEPTH_8,
+		.step_or_mask = 1,
+		.value = BIT_DEPTH_8,
+		.hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
+	},
+	{
+		.cap_id = RAP_FRAME,
+		.min = 0,
+		.max = 1,
+		.step_or_mask = 1,
+		.value = 1,
+		.hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
+		.flags = CAP_FLAG_INPUT_PORT,
+		.set = iris_set_u32,
+	},
+};
+
+static const struct platform_inst_fw_cap inst_fw_cap_milos_enc[] = {
+	{
+		.cap_id = PROFILE_H264,
+		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
+				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
+		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+		.hfi_id = HFI_PROP_PROFILE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_profile,
+	},
+	{
+		.cap_id = PROFILE_HEVC,
+		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
+		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+		.hfi_id = HFI_PROP_PROFILE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_profile,
+	},
+	{
+		.cap_id = LEVEL_H264,
+		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+		.max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
+				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
+		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
+		.hfi_id = HFI_PROP_LEVEL,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_level,
+	},
+	{
+		.cap_id = LEVEL_HEVC,
+		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
+				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5),
+		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
+		.hfi_id = HFI_PROP_LEVEL,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_level,
+	},
+	{
+		.cap_id = STAGE,
+		.min = STAGE_1,
+		.max = STAGE_2,
+		.step_or_mask = 1,
+		.value = STAGE_2,
+		.hfi_id = HFI_PROP_STAGE,
+		.set = iris_set_stage,
+	},
+	{
+		.cap_id = HEADER_MODE,
+		.min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
+		.max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
+				BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
+		.value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
+		.hfi_id = HFI_PROP_SEQ_HEADER_MODE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_header_mode_gen2,
+	},
+	{
+		.cap_id = PREPEND_SPSPPS_TO_IDR,
+		.min = 0,
+		.max = 1,
+		.step_or_mask = 1,
+		.value = 0,
+	},
+	{
+		.cap_id = BITRATE,
+		.min = 1,
+		.max = MILOS_V1_MAX_BITRATE,
+		.step_or_mask = 1,
+		.value = BITRATE_DEFAULT,
+		.hfi_id = HFI_PROP_TOTAL_BITRATE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_bitrate,
+	},
+	{
+		.cap_id = BITRATE_PEAK,
+		.min = 1,
+		.max = MILOS_V1_MAX_BITRATE,
+		.step_or_mask = 1,
+		.value = BITRATE_DEFAULT,
+		.hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_peak_bitrate,
+	},
+	{
+		.cap_id = BITRATE_MODE,
+		.min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
+		.max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
+				BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
+		.value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
+		.hfi_id = HFI_PROP_RATE_CONTROL,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_bitrate_mode_gen2,
+	},
+	{
+		.cap_id = FRAME_SKIP_MODE,
+		.min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
+		.max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
+				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
+				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
+		.value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+	},
+	{
+		.cap_id = FRAME_RC_ENABLE,
+		.min = 0,
+		.max = 1,
+		.step_or_mask = 1,
+		.value = 1,
+	},
+	{
+		.cap_id = GOP_SIZE,
+		.min = 0,
+		.max = INT_MAX,
+		.step_or_mask = 1,
+		.value = 2 * DEFAULT_FPS - 1,
+		.hfi_id = HFI_PROP_MAX_GOP_FRAMES,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_u32,
+	},
+	{
+		.cap_id = ENTROPY_MODE,
+		.min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
+		.max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
+		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
+				BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
+		.value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
+		.hfi_id = HFI_PROP_CABAC_SESSION,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+		.set = iris_set_entropy_mode_gen2,
+	},
+	{
+		.cap_id = MIN_FRAME_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+		.hfi_id = HFI_PROP_MIN_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT,
+		.set = iris_set_min_qp,
+	},
+	{
+		.cap_id = MIN_FRAME_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+		.hfi_id = HFI_PROP_MIN_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT,
+		.set = iris_set_min_qp,
+	},
+	{
+		.cap_id = MAX_FRAME_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+		.hfi_id = HFI_PROP_MAX_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT,
+		.set = iris_set_max_qp,
+	},
+	{
+		.cap_id = MAX_FRAME_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+		.hfi_id = HFI_PROP_MAX_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT,
+		.set = iris_set_max_qp,
+	},
+	{
+		.cap_id = I_FRAME_MIN_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+	},
+	{
+		.cap_id = I_FRAME_MIN_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+	},
+	{
+		.cap_id = P_FRAME_MIN_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+	},
+	{
+		.cap_id = P_FRAME_MIN_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+	},
+	{
+		.cap_id = B_FRAME_MIN_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+	},
+	{
+		.cap_id = B_FRAME_MIN_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MIN_QP_8BIT,
+	},
+	{
+		.cap_id = I_FRAME_MAX_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+	},
+	{
+		.cap_id = I_FRAME_MAX_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+	},
+	{
+		.cap_id = P_FRAME_MAX_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+	},
+	{
+		.cap_id = P_FRAME_MAX_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+	},
+	{
+		.cap_id = B_FRAME_MAX_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+	},
+	{
+		.cap_id = B_FRAME_MAX_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = MAX_QP,
+	},
+	{
+		.cap_id = I_FRAME_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = DEFAULT_QP,
+		.hfi_id = HFI_PROP_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_frame_qp,
+	},
+	{
+		.cap_id = I_FRAME_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = DEFAULT_QP,
+		.hfi_id = HFI_PROP_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_frame_qp,
+	},
+	{
+		.cap_id = P_FRAME_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = DEFAULT_QP,
+		.hfi_id = HFI_PROP_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_frame_qp,
+	},
+	{
+		.cap_id = P_FRAME_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = DEFAULT_QP,
+		.hfi_id = HFI_PROP_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_frame_qp,
+	},
+	{
+		.cap_id = B_FRAME_QP_H264,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = DEFAULT_QP,
+		.hfi_id = HFI_PROP_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_frame_qp,
+	},
+	{
+		.cap_id = B_FRAME_QP_HEVC,
+		.min = MIN_QP_8BIT,
+		.max = MAX_QP,
+		.step_or_mask = 1,
+		.value = DEFAULT_QP,
+		.hfi_id = HFI_PROP_QP_PACKED,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_frame_qp,
+	},
+	{
+		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
+		.min = DEFAULT_MAX_HOST_BUF_COUNT,
+		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
+		.step_or_mask = 1,
+		.value = DEFAULT_MAX_HOST_BUF_COUNT,
+		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
+		.flags = CAP_FLAG_INPUT_PORT,
+		.set = iris_set_u32,
+	},
+	{
+		.cap_id = OUTPUT_BUF_HOST_MAX_COUNT,
+		.min = DEFAULT_MAX_HOST_BUF_COUNT,
+		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
+		.step_or_mask = 1,
+		.value = DEFAULT_MAX_HOST_BUF_COUNT,
+		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
+		.flags = CAP_FLAG_OUTPUT_PORT,
+		.set = iris_set_u32,
+	},
+	{
+		.cap_id = ROTATION,
+		.min = 0,
+		.max = 270,
+		.step_or_mask = 90,
+		.value = 0,
+		.hfi_id = HFI_PROP_ROTATION,
+		.flags = CAP_FLAG_OUTPUT_PORT,
+		.set = iris_set_rotation,
+	},
+	{
+		.cap_id = HFLIP,
+		.min = 0,
+		.max = 1,
+		.step_or_mask = 1,
+		.value = 0,
+		.hfi_id = HFI_PROP_FLIP,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_flip,
+	},
+	{
+		.cap_id = VFLIP,
+		.min = 0,
+		.max = 1,
+		.step_or_mask = 1,
+		.value = 0,
+		.hfi_id = HFI_PROP_FLIP,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_flip,
+	},
+	{
+		.cap_id = IR_TYPE,
+		.min = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+		.max = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+		.step_or_mask = BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM),
+		.value = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+	},
+	{
+		.cap_id = IR_PERIOD,
+		.min = 0,
+		.max = INT_MAX,
+		.step_or_mask = 1,
+		.value = 0,
+		.flags = CAP_FLAG_OUTPUT_PORT |
+			CAP_FLAG_DYNAMIC_ALLOWED,
+		.set = iris_set_ir_period,
+	},
+};
+
+static struct platform_inst_caps platform_inst_cap_milos = {
+	.min_frame_width = 96,
+	.max_frame_width = 4096,
+	.min_frame_height = 96,
+	.max_frame_height = 4096,
+	.max_mbpf = (4096 * 2176) / 256,
+	.mb_cycles_vpp = 200,
+	.mb_cycles_fw = 326389,
+	.mb_cycles_fw_vpp = 44156,
+	.num_comv = 0,
+	.max_frame_rate = MILOS_V1_MAX_FPS,
+	.max_operating_rate = MILOS_V1_MAX_FPS,
+};
+
+static const struct icc_info milos_icc_table[] = {
+	{ "cpu-cfg",    1000, 1000     },
+	{ "video-mem",  1000, 10000000 },
+};
+
+static const char * const milos_opp_pd_table[] = { "cx", "mx" };
+
+static struct ubwc_config_data ubwc_config_milos = {
+	.max_channels = 8,
+	.mal_length = 32,
+	.highest_bank_bit = 15,
+	.bank_swzl_level = 0,
+	.bank_swz2_level = 1,
+	.bank_swz3_level = 1,
+	.bank_spreading = 1,
+};
+
+#endif
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index ddaacda523ec..ff3f4f1dc2ff 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -348,6 +348,10 @@ static const struct dev_pm_ops iris_pm_ops = {
 };
 
 static const struct of_device_id iris_dt_match[] = {
+	{
+		.compatible = "qcom,milos-iris",
+		.data = &milos_data,
+	},
 	{
 		.compatible = "qcom,qcs8300-iris",
 		.data = &qcs8300_data,

-- 
2.53.0

Re: [PATCH 2/3] media: iris: Add support for Milos (VPU v2.0)

[Vishnu Reddy]

On 4/6/2026 3:49 PM, Alexander Koskovich wrote:
> Add support for the Milos Iris codec. This only supports the variant
> found on the SM7635-AB that has half of it's pipes disabled via efuse.
>
> Signed-off-by: Alexander Koskovich<akoskovich@pm.me>
> ---
>   .../platform/qcom/iris/iris_platform_common.h      |   1 +
>   .../media/platform/qcom/iris/iris_platform_gen2.c  | 106 ++++
>   .../media/platform/qcom/iris/iris_platform_milos.h | 655 +++++++++++++++++++++
>   drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
>   4 files changed, 766 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 5a489917580e..c8a9f122952e 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -41,6 +41,7 @@ enum pipe_type {
>   	PIPE_4 = 4,
>   };
>   
> +extern const struct iris_platform_data milos_data;
>   extern const struct iris_platform_data qcs8300_data;
>   extern const struct iris_platform_data sc7280_data;
>   extern const struct iris_platform_data sm8250_data;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 5da90d47f9c6..78cd4656b981 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -12,6 +12,7 @@
>   #include "iris_vpu_buffer.h"
>   #include "iris_vpu_common.h"
>   
> +#include "iris_platform_milos.h"
>   #include "iris_platform_qcs8300.h"
>   #include "iris_platform_sm8650.h"
>   #include "iris_platform_sm8750.h"
> @@ -1317,3 +1318,108 @@ const struct iris_platform_data qcs8300_data = {
>   	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
>   	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>   };
> +
> +/*
> + * Shares most of SM8550 data except:
> + * - vpu_ops to iris_vpu2_ops
> + * - icc_tbl to milos_icc_table
> + * - clk_rst_tbl to sm8650_clk_reset_table
> + * - opp_pd_tbl to milos_opp_pd_table
> + * - fwname to "qcom/vpu/vpu20_2v.mbn"
> + * - inst_iris_fmts to platform_fmts_milos_dec
> + * - inst_caps to platform_inst_cap_milos
> + * - inst_fw_caps_dec to inst_fw_cap_milos_dec
> + * - inst_fw_caps_enc to inst_fw_cap_milos_enc
> + * - ubwc_config to ubwc_config_milos
> + * - num_vpp_pipe to 2
> + * - max_core_mbpf scaled for 4k@30fps dec/enc
> + * - max_core_mbps scaled for 4k@30fps dec & 1080p@30 enc
> + */
> +const struct iris_platform_data milos_data = {
> +	.get_instance = iris_hfi_gen2_get_instance,
> +	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> +	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> +	.get_vpu_buffer_size = iris_vpu_buf_size,
> +	.vpu_ops = &iris_vpu2_ops,
> +	.set_preset_registers = iris_set_sm8550_preset_registers,
> +	.icc_tbl = milos_icc_table,
> +	.icc_tbl_size = ARRAY_SIZE(milos_icc_table),
> +	.clk_rst_tbl = sm8650_clk_reset_table,
> +	.clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
> +	.bw_tbl_dec = sm8550_bw_table_dec,
> +	.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> +	.pmdomain_tbl = sm8550_pmdomain_table,
> +	.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
> +	.opp_pd_tbl = milos_opp_pd_table,
> +	.opp_pd_tbl_size = ARRAY_SIZE(milos_opp_pd_table),
> +	.clk_tbl = sm8550_clk_table,
> +	.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> +	.opp_clk_tbl = sm8550_opp_clk_table,
> +	/* Upper bound of DMA address range */
> +	.dma_mask = 0xe0000000 - 1,
> +	.fwname = "qcom/vpu/vpu20_2v.mbn",

can you check how firmware names are added for earlier platforms.
It should be like this vpu20_p2.mbn

> +	.pas_id = IRIS_PAS_ID,
> +	.inst_iris_fmts = platform_fmts_milos_dec,
> +	.inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_milos_dec),
> +	.inst_caps = &platform_inst_cap_milos,
> +	.inst_fw_caps_dec = inst_fw_cap_milos_dec,
> +	.inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_milos_dec),
> +	.inst_fw_caps_enc = inst_fw_cap_milos_enc,
> +	.inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_milos_enc),
> +	.tz_cp_config_data = tz_cp_config_sm8550,
> +	.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> +	.core_arch = VIDEO_ARCH_LX,
> +	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> +	.ubwc_config = &ubwc_config_milos,
> +	.num_vpp_pipe = 2,
> +	.max_session_count = 16,
> +	.max_core_mbpf = ((4096 * 2176) / 256) * 2,
> +	.max_core_mbps = ((3840 * 2176) / 256) * 30 + ((1920 * 1088) / 256) * 30,
> +	.dec_input_config_params_default =
> +		sm8550_vdec_input_config_params_default,
> +	.dec_input_config_params_default_size =
> +		ARRAY_SIZE(sm8550_vdec_input_config_params_default),
> +	.dec_input_config_params_hevc =
> +		sm8550_vdec_input_config_param_hevc,
> +	.dec_input_config_params_hevc_size =
> +		ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
> +	.dec_input_config_params_vp9 =
> +		sm8550_vdec_input_config_param_vp9,
> +	.dec_input_config_params_vp9_size =
> +		ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
> +	.dec_output_config_params =
> +		sm8550_vdec_output_config_params,
> +	.dec_output_config_params_size =
> +		ARRAY_SIZE(sm8550_vdec_output_config_params),
> +
> +	.enc_input_config_params =
> +		sm8550_venc_input_config_params,
> +	.enc_input_config_params_size =
> +		ARRAY_SIZE(sm8550_venc_input_config_params),
> +	.enc_output_config_params =
> +		sm8550_venc_output_config_params,
> +	.enc_output_config_params_size =
> +		ARRAY_SIZE(sm8550_venc_output_config_params),
> +
> +	.dec_input_prop = sm8550_vdec_subscribe_input_properties,
> +	.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
> +	.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
> +	.dec_output_prop_avc_size =
> +		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
> +	.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
> +	.dec_output_prop_hevc_size =
> +		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
> +	.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
> +	.dec_output_prop_vp9_size =
> +		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
> +
> +	.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
> +	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
> +	.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
> +	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
> +
> +	.enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
> +	.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
> +	.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> +	.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_milos.h b/drivers/media/platform/qcom/iris/iris_platform_milos.h
> new file mode 100644
> index 000000000000..dacd3ad5aa7e
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_milos.h
> @@ -0,0 +1,655 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __IRIS_PLATFORM_MILOS_H__
> +#define __IRIS_PLATFORM_MILOS_H__
> +
> +#define MILOS_V1_MAX_BITRATE	100000000
> +#define MILOS_V1_MAX_FPS	240
> +
> +static struct iris_fmt platform_fmts_milos_dec[] = {
> +	[IRIS_FMT_H264] = {
> +		.pixfmt = V4L2_PIX_FMT_H264,
> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> +	},
> +	[IRIS_FMT_HEVC] = {
> +		.pixfmt = V4L2_PIX_FMT_HEVC,
> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> +	},
> +	[IRIS_FMT_VP9] = {
> +		.pixfmt = V4L2_PIX_FMT_VP9,
> +		.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> +	},
> +};
> +
> +static const struct platform_inst_fw_cap inst_fw_cap_milos_dec[] = {
> +	{
> +		.cap_id = PROFILE_H264,
> +		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> +		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
> +		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> +		.hfi_id = HFI_PROP_PROFILE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_u32_enum,
> +	},
> +	{
> +		.cap_id = PROFILE_HEVC,
> +		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> +		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
> +		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> +		.hfi_id = HFI_PROP_PROFILE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_u32_enum,
> +	},
> +	{
> +		.cap_id = PROFILE_VP9,
> +		.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> +		.max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
> +		.value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> +		.hfi_id = HFI_PROP_PROFILE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_u32_enum,
> +	},
> +	{
> +		.cap_id = LEVEL_H264,
> +		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> +		.max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
> +		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
> +		.hfi_id = HFI_PROP_LEVEL,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_u32_enum,
> +	},
> +	{
> +		.cap_id = LEVEL_HEVC,
> +		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> +		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5),
> +		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> +		.hfi_id = HFI_PROP_LEVEL,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_u32_enum,
> +	},
> +	{
> +		.cap_id = LEVEL_VP9,
> +		.min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
> +		.max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_0,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
> +				BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0),
> +		.value = V4L2_MPEG_VIDEO_VP9_LEVEL_5_0,
> +		.hfi_id = HFI_PROP_LEVEL,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_u32_enum,
> +	},
> +	{
> +		.cap_id = TIER,
> +		.min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
> +		.max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
> +		.value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> +		.hfi_id = HFI_PROP_TIER,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_u32_enum,
> +	},
> +	{
> +		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
> +		.min = DEFAULT_MAX_HOST_BUF_COUNT,
> +		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_MAX_HOST_BUF_COUNT,
> +		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> +		.flags = CAP_FLAG_INPUT_PORT,
> +		.set = iris_set_u32,
> +	},
> +	{
> +		.cap_id = STAGE,
> +		.min = STAGE_1,
> +		.max = STAGE_2,
> +		.step_or_mask = 1,
> +		.value = STAGE_2,
> +		.hfi_id = HFI_PROP_STAGE,
> +		.set = iris_set_stage,
> +	},
> +	{
> +		.cap_id = PIPE,
> +		/* .max, .min and .value are set via platform data */
> +		.step_or_mask = 1,
> +		.hfi_id = HFI_PROP_PIPE,
> +		.set = iris_set_pipe,
> +	},
> +	{
> +		.cap_id = POC,
> +		.min = 0,
> +		.max = 2,
> +		.step_or_mask = 1,
> +		.value = 1,
> +		.hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
> +	},
> +	{
> +		.cap_id = CODED_FRAMES,
> +		.min = CODED_FRAMES_PROGRESSIVE,
> +		.max = CODED_FRAMES_PROGRESSIVE,
> +		.step_or_mask = 0,
> +		.value = CODED_FRAMES_PROGRESSIVE,
> +		.hfi_id = HFI_PROP_CODED_FRAMES,
> +	},
> +	{
> +		.cap_id = BIT_DEPTH,
> +		.min = BIT_DEPTH_8,
> +		.max = BIT_DEPTH_8,
> +		.step_or_mask = 1,
> +		.value = BIT_DEPTH_8,
> +		.hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
> +	},
> +	{
> +		.cap_id = RAP_FRAME,
> +		.min = 0,
> +		.max = 1,
> +		.step_or_mask = 1,
> +		.value = 1,
> +		.hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
> +		.flags = CAP_FLAG_INPUT_PORT,
> +		.set = iris_set_u32,
> +	},
> +};
> +
> +static const struct platform_inst_fw_cap inst_fw_cap_milos_enc[] = {
> +	{
> +		.cap_id = PROFILE_H264,
> +		.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> +		.max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> +				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
> +		.value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> +		.hfi_id = HFI_PROP_PROFILE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_profile,
> +	},
> +	{
> +		.cap_id = PROFILE_HEVC,
> +		.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> +		.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
> +		.value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> +		.hfi_id = HFI_PROP_PROFILE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_profile,
> +	},
> +	{
> +		.cap_id = LEVEL_H264,
> +		.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> +		.max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> +				BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
> +		.value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
> +		.hfi_id = HFI_PROP_LEVEL,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_level,
> +	},
> +	{
> +		.cap_id = LEVEL_HEVC,
> +		.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> +		.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> +				BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5),
> +		.value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> +		.hfi_id = HFI_PROP_LEVEL,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_level,
> +	},
> +	{
> +		.cap_id = STAGE,
> +		.min = STAGE_1,
> +		.max = STAGE_2,
> +		.step_or_mask = 1,
> +		.value = STAGE_2,
> +		.hfi_id = HFI_PROP_STAGE,
> +		.set = iris_set_stage,
> +	},
> +	{
> +		.cap_id = HEADER_MODE,
> +		.min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
> +		.max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
> +				BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
> +		.value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> +		.hfi_id = HFI_PROP_SEQ_HEADER_MODE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_header_mode_gen2,
> +	},
> +	{
> +		.cap_id = PREPEND_SPSPPS_TO_IDR,
> +		.min = 0,
> +		.max = 1,
> +		.step_or_mask = 1,
> +		.value = 0,
> +	},
> +	{
> +		.cap_id = BITRATE,
> +		.min = 1,
> +		.max = MILOS_V1_MAX_BITRATE,
> +		.step_or_mask = 1,
> +		.value = BITRATE_DEFAULT,
> +		.hfi_id = HFI_PROP_TOTAL_BITRATE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_bitrate,
> +	},
> +	{
> +		.cap_id = BITRATE_PEAK,
> +		.min = 1,
> +		.max = MILOS_V1_MAX_BITRATE,
> +		.step_or_mask = 1,
> +		.value = BITRATE_DEFAULT,
> +		.hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_peak_bitrate,
> +	},
> +	{
> +		.cap_id = BITRATE_MODE,
> +		.min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> +		.max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
> +				BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
> +		.value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> +		.hfi_id = HFI_PROP_RATE_CONTROL,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_bitrate_mode_gen2,
> +	},
> +	{
> +		.cap_id = FRAME_SKIP_MODE,
> +		.min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> +		.max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
> +				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
> +				BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
> +		.value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +	},
> +	{
> +		.cap_id = FRAME_RC_ENABLE,
> +		.min = 0,
> +		.max = 1,
> +		.step_or_mask = 1,
> +		.value = 1,
> +	},
> +	{
> +		.cap_id = GOP_SIZE,
> +		.min = 0,
> +		.max = INT_MAX,
> +		.step_or_mask = 1,
> +		.value = 2 * DEFAULT_FPS - 1,
> +		.hfi_id = HFI_PROP_MAX_GOP_FRAMES,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_u32,
> +	},
> +	{
> +		.cap_id = ENTROPY_MODE,
> +		.min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
> +		.max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> +		.step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
> +				BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
> +		.value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> +		.hfi_id = HFI_PROP_CABAC_SESSION,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +		.set = iris_set_entropy_mode_gen2,
> +	},
> +	{
> +		.cap_id = MIN_FRAME_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +		.hfi_id = HFI_PROP_MIN_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT,
> +		.set = iris_set_min_qp,
> +	},
> +	{
> +		.cap_id = MIN_FRAME_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +		.hfi_id = HFI_PROP_MIN_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT,
> +		.set = iris_set_min_qp,
> +	},
> +	{
> +		.cap_id = MAX_FRAME_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +		.hfi_id = HFI_PROP_MAX_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT,
> +		.set = iris_set_max_qp,
> +	},
> +	{
> +		.cap_id = MAX_FRAME_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +		.hfi_id = HFI_PROP_MAX_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT,
> +		.set = iris_set_max_qp,
> +	},
> +	{
> +		.cap_id = I_FRAME_MIN_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +	},
> +	{
> +		.cap_id = I_FRAME_MIN_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +	},
> +	{
> +		.cap_id = P_FRAME_MIN_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +	},
> +	{
> +		.cap_id = P_FRAME_MIN_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +	},
> +	{
> +		.cap_id = B_FRAME_MIN_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +	},
> +	{
> +		.cap_id = B_FRAME_MIN_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MIN_QP_8BIT,
> +	},
> +	{
> +		.cap_id = I_FRAME_MAX_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +	},
> +	{
> +		.cap_id = I_FRAME_MAX_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +	},
> +	{
> +		.cap_id = P_FRAME_MAX_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +	},
> +	{
> +		.cap_id = P_FRAME_MAX_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +	},
> +	{
> +		.cap_id = B_FRAME_MAX_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +	},
> +	{
> +		.cap_id = B_FRAME_MAX_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = MAX_QP,
> +	},
> +	{
> +		.cap_id = I_FRAME_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_QP,
> +		.hfi_id = HFI_PROP_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_frame_qp,
> +	},
> +	{
> +		.cap_id = I_FRAME_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_QP,
> +		.hfi_id = HFI_PROP_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_frame_qp,
> +	},
> +	{
> +		.cap_id = P_FRAME_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_QP,
> +		.hfi_id = HFI_PROP_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_frame_qp,
> +	},
> +	{
> +		.cap_id = P_FRAME_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_QP,
> +		.hfi_id = HFI_PROP_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_frame_qp,
> +	},
> +	{
> +		.cap_id = B_FRAME_QP_H264,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_QP,
> +		.hfi_id = HFI_PROP_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_frame_qp,
> +	},
> +	{
> +		.cap_id = B_FRAME_QP_HEVC,
> +		.min = MIN_QP_8BIT,
> +		.max = MAX_QP,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_QP,
> +		.hfi_id = HFI_PROP_QP_PACKED,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_frame_qp,
> +	},
> +	{
> +		.cap_id = INPUT_BUF_HOST_MAX_COUNT,
> +		.min = DEFAULT_MAX_HOST_BUF_COUNT,
> +		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_MAX_HOST_BUF_COUNT,
> +		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> +		.flags = CAP_FLAG_INPUT_PORT,
> +		.set = iris_set_u32,
> +	},
> +	{
> +		.cap_id = OUTPUT_BUF_HOST_MAX_COUNT,
> +		.min = DEFAULT_MAX_HOST_BUF_COUNT,
> +		.max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> +		.step_or_mask = 1,
> +		.value = DEFAULT_MAX_HOST_BUF_COUNT,
> +		.hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> +		.flags = CAP_FLAG_OUTPUT_PORT,
> +		.set = iris_set_u32,
> +	},
> +	{
> +		.cap_id = ROTATION,
> +		.min = 0,
> +		.max = 270,
> +		.step_or_mask = 90,
> +		.value = 0,
> +		.hfi_id = HFI_PROP_ROTATION,
> +		.flags = CAP_FLAG_OUTPUT_PORT,
> +		.set = iris_set_rotation,
> +	},
> +	{
> +		.cap_id = HFLIP,
> +		.min = 0,
> +		.max = 1,
> +		.step_or_mask = 1,
> +		.value = 0,
> +		.hfi_id = HFI_PROP_FLIP,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_flip,
> +	},
> +	{
> +		.cap_id = VFLIP,
> +		.min = 0,
> +		.max = 1,
> +		.step_or_mask = 1,
> +		.value = 0,
> +		.hfi_id = HFI_PROP_FLIP,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_flip,
> +	},
> +	{
> +		.cap_id = IR_TYPE,
> +		.min = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
> +		.max = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
> +		.step_or_mask = BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM),
> +		.value = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
> +		.flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> +	},
> +	{
> +		.cap_id = IR_PERIOD,
> +		.min = 0,
> +		.max = INT_MAX,
> +		.step_or_mask = 1,
> +		.value = 0,
> +		.flags = CAP_FLAG_OUTPUT_PORT |
> +			CAP_FLAG_DYNAMIC_ALLOWED,
> +		.set = iris_set_ir_period,
> +	},
> +};
> +
> +static struct platform_inst_caps platform_inst_cap_milos = {
> +	.min_frame_width = 96,
> +	.max_frame_width = 4096,
> +	.min_frame_height = 96,
> +	.max_frame_height = 4096,
> +	.max_mbpf = (4096 * 2176) / 256,
> +	.mb_cycles_vpp = 200,
> +	.mb_cycles_fw = 326389,
> +	.mb_cycles_fw_vpp = 44156,
> +	.num_comv = 0,
> +	.max_frame_rate = MILOS_V1_MAX_FPS,
> +	.max_operating_rate = MILOS_V1_MAX_FPS,
> +};
> +
> +static const struct icc_info milos_icc_table[] = {
> +	{ "cpu-cfg",    1000, 1000     },
> +	{ "video-mem",  1000, 10000000 },
> +};
> +
> +static const char * const milos_opp_pd_table[] = { "cx", "mx" };
> +
> +static struct ubwc_config_data ubwc_config_milos = {
> +	.max_channels = 8,
> +	.mal_length = 32,
> +	.highest_bank_bit = 15,
> +	.bank_swzl_level = 0,
> +	.bank_swz2_level = 1,
> +	.bank_swz3_level = 1,
> +	.bank_spreading = 1,
> +};
> +
> +#endif
> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
> index ddaacda523ec..ff3f4f1dc2ff 100644
> --- a/drivers/media/platform/qcom/iris/iris_probe.c
> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
> @@ -348,6 +348,10 @@ static const struct dev_pm_ops iris_pm_ops = {
>   };
>   
>   static const struct of_device_id iris_dt_match[] = {
> +	{
> +		.compatible = "qcom,milos-iris",
> +		.data = &milos_data,
> +	},
>   	{
>   		.compatible = "qcom,qcs8300-iris",
>   		.data = &qcs8300_data,
>

[PATCH 3/3] arm64: dts: qcom: milos: Add Iris VPU v2.0

[Alexander Koskovich]

Add devicetree nodes for the Iris codec (VPU 2.0) found on the Milos
platform.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 arch/arm64/boot/dts/qcom/milos.dtsi | 85 +++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index e1a51d43943f..07aa398c9695 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,milos-dispcc.h>
 #include <dt-bindings/clock/qcom,milos-gcc.h>
 #include <dt-bindings/clock/qcom,milos-gpucc.h>
+#include <dt-bindings/clock/qcom,milos-videocc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -1517,6 +1518,90 @@ usb_1_dwc3_hs: endpoint {
 			};
 		};
 
+		iris: video-codec@aa00000 {
+			compatible = "qcom,milos-iris";
+			reg = <0 0x0aa00000 0 0xf0000>;
+
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+					<&videocc VIDEO_CC_MVS0_GDSC>,
+					<&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MX>;
+			power-domain-names = "venus",
+					     "vcodec0",
+					     "cx",
+					     "mx";
+
+			operating-points-v2 = <&iris_opp_table>;
+
+			clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+				 <&videocc VIDEO_CC_MVS0C_CLK>,
+				 <&videocc VIDEO_CC_MVS0_CLK>;
+			clock-names = "iface",
+				      "core",
+				      "vcodec0_core";
+
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "cpu-cfg",
+					     "video-mem";
+
+			memory-region = <&video_mem>;
+
+			resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+				 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+			reset-names = "bus",
+				      "core";
+
+			iommus = <&apps_smmu 0x1960 0>,
+				 <&apps_smmu 0x1967 0>;
+
+			dma-coherent;
+
+			/*
+			 * IRIS firmware is signed by vendors, only enable on
+			 * boards where the proper signed firmware is available.
+			 */
+			status = "disabled";
+
+			iris_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-240000000 {
+					opp-hz = /bits/ 64 <240000000>;
+					required-opps = <&rpmhpd_opp_low_svs>,
+							<&rpmhpd_opp_low_svs>;
+				};
+
+				opp-338000000 {
+					opp-hz = /bits/ 64 <338000000>;
+					required-opps = <&rpmhpd_opp_svs>,
+							<&rpmhpd_opp_svs>;
+				};
+
+				opp-366000000 {
+					opp-hz = /bits/ 64 <366000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>,
+							<&rpmhpd_opp_svs_l1>;
+				};
+
+				opp-444000000 {
+					opp-hz = /bits/ 64 <444000000>;
+					required-opps = <&rpmhpd_opp_nom>,
+							<&rpmhpd_opp_nom>;
+				};
+
+				opp-552000000 {
+					opp-hz = /bits/ 64 <552000000>;
+					required-opps = <&rpmhpd_opp_turbo>,
+							<&rpmhpd_opp_turbo>;
+				};
+			};
+		};
+
 		videocc: clock-controller@aaf0000 {
 			compatible = "qcom,milos-videocc";
 			reg = <0x0 0x0aaf0000 0x0 0x10000>;

-- 
2.53.0

Re: [PATCH 3/3] arm64: dts: qcom: milos: Add Iris VPU v2.0

[Krzysztof Kozlowski]

On Mon, Apr 06, 2026 at 10:19:50AM +0000, Alexander Koskovich wrote:
> Add devicetree nodes for the Iris codec (VPU 2.0) found on the Milos
> platform.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  arch/arm64/boot/dts/qcom/milos.dtsi | 85 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 85 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index e1a51d43943f..07aa398c9695 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -7,6 +7,7 @@
>  #include <dt-bindings/clock/qcom,milos-dispcc.h>
>  #include <dt-bindings/clock/qcom,milos-gcc.h>
>  #include <dt-bindings/clock/qcom,milos-gpucc.h>
> +#include <dt-bindings/clock/qcom,milos-videocc.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
> @@ -1517,6 +1518,90 @@ usb_1_dwc3_hs: endpoint {
>  			};
>  		};
>  
> +		iris: video-codec@aa00000 {
> +			compatible = "qcom,milos-iris";
> +			reg = <0 0x0aa00000 0 0xf0000>;

Hex, please.


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: milos: Add Iris VPU v2.0

[Dikshita Agarwal]

On 4/6/2026 3:49 PM, Alexander Koskovich wrote:
> Add devicetree nodes for the Iris codec (VPU 2.0) found on the Milos
> platform.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  arch/arm64/boot/dts/qcom/milos.dtsi | 85 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 85 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index e1a51d43943f..07aa398c9695 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -7,6 +7,7 @@
>  #include <dt-bindings/clock/qcom,milos-dispcc.h>
>  #include <dt-bindings/clock/qcom,milos-gcc.h>
>  #include <dt-bindings/clock/qcom,milos-gpucc.h>
> +#include <dt-bindings/clock/qcom,milos-videocc.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
> @@ -1517,6 +1518,90 @@ usb_1_dwc3_hs: endpoint {
>  			};
>  		};
>  
> +		iris: video-codec@aa00000 {
> +			compatible = "qcom,milos-iris";
> +			reg = <0 0x0aa00000 0 0xf0000>;
> +
> +			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
> +
> +			power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
> +					<&videocc VIDEO_CC_MVS0_GDSC>,
> +					<&rpmhpd RPMHPD_CX>,
> +					<&rpmhpd RPMHPD_MX>;
> +			power-domain-names = "venus",
> +					     "vcodec0",
> +					     "cx",
> +					     "mx";
> +
> +			operating-points-v2 = <&iris_opp_table>;
> +
> +			clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> +				 <&videocc VIDEO_CC_MVS0C_CLK>,
> +				 <&videocc VIDEO_CC_MVS0_CLK>;
> +			clock-names = "iface",
> +				      "core",
> +				      "vcodec0_core";
> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> +					 &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> +					<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> +			interconnect-names = "cpu-cfg",
> +					     "video-mem";
> +
> +			memory-region = <&video_mem>;
> +
> +			resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
> +				 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
> +			reset-names = "bus",
> +				      "core";
> +
> +			iommus = <&apps_smmu 0x1960 0>,
> +				 <&apps_smmu 0x1967 0>;
> +
> +			dma-coherent;
> +
> +			/*
> +			 * IRIS firmware is signed by vendors, only enable on
> +			 * boards where the proper signed firmware is available.
> +			 */
> +			status = "disabled";
> +
> +			iris_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-240000000 {
> +					opp-hz = /bits/ 64 <240000000>;
> +					required-opps = <&rpmhpd_opp_low_svs>,
> +							<&rpmhpd_opp_low_svs>;

s/rpmhpd_opp_low_svs/rpmhpd_opp_svs

> +				};
> +
> +				opp-338000000 {
> +					opp-hz = /bits/ 64 <338000000>;
> +					required-opps = <&rpmhpd_opp_svs>,
> +							<&rpmhpd_opp_svs>;
> +				};
> +
> +				opp-366000000 {
> +					opp-hz = /bits/ 64 <366000000>;
> +					required-opps = <&rpmhpd_opp_svs_l1>,
> +							<&rpmhpd_opp_svs_l1>;

s/rpmhpd_opp_svs_l1/rpmhpd_opp_svs

> +				};
> +
> +				opp-444000000 {
> +					opp-hz = /bits/ 64 <444000000>;
> +					required-opps = <&rpmhpd_opp_nom>,
> +		

					<&rpmhpd_opp_nom>;
s/rpmhpd_opp_nom/rpmhpd_opp_svs_l1

> +				};
> +
> +				opp-552000000 {
> +					opp-hz = /bits/ 64 <552000000>;
> +					required-opps = <&rpmhpd_opp_turbo>,
> +							<&rpmhpd_opp_turbo>;

s/rpmhpd_opp_turbo/rpmhpd_opp_nom

Thanks,
Dikshita
> +				};

> +			};
> +		};
> +
>  		videocc: clock-controller@aaf0000 {
>  			compatible = "qcom,milos-videocc";
>  			reg = <0x0 0x0aaf0000 0x0 0x10000>;
> 

Re: [PATCH 0/3] Add support for the Iris codec on Milos

[Vishnu Reddy]

On 4/6/2026 3:49 PM, Alexander Koskovich wrote:
> This series adds the bindings, nodes and platform data for the Milos platform
> for the Iris video codec, allowing Milos to use hardware‑accelerated video
> encoding and decoding.
>
> Ran v4l2-compliance and some fluster tests, though a concerning amount of them
> failed. Attaching v4l2-compliance output and the full fluster results below.
>
> ~ # v4l2-compliance -d /dev/video0
> v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
>
> Compliance test for iris_driver device /dev/video0:
>
> Driver Info:
> 	Driver name      : iris_driver
> 	Card type        : Iris Decoder
> 	Bus info         : platform:aa00000.video-codec
> 	Driver version   : 7.0.0
> 	Capabilities     : 0x84204000
> 		Video Memory-to-Memory Multiplanar
> 		Streaming
> 		Extended Pix Format
> 		Device Capabilities
> 	Device Caps      : 0x04204000
> 		Video Memory-to-Memory Multiplanar
> 		Streaming
> 		Extended Pix Format
> 	Detected Stateful Decoder
>
> Required ioctls:
> 	test VIDIOC_QUERYCAP: OK
> 	test invalid ioctls: OK
>
> Allow for multiple opens:
> 	test second /dev/video0 open: OK
> 	test VIDIOC_QUERYCAP: OK
> 	test VIDIOC_G/S_PRIORITY: OK
> 	test for unlimited opens: OK
>
> Debug ioctls:
> 	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> 	test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> 	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> 	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> 	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> 	test VIDIOC_ENUMAUDIO: OK (Not Supported)
> 	test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> 	test VIDIOC_G/S_AUDIO: OK (Not Supported)
> 	Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> 	test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> 	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> 	test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> 	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> 	test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> 	Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> 	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> 	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> 	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> 	test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> 	test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> 	test VIDIOC_QUERYCTRL: OK
> 	test VIDIOC_G/S_CTRL: OK
> 	test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> 	test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> 	test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> 	Standard Controls: 10 Private Controls: 0
>
> Format ioctls:
> 	test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> 	test VIDIOC_G/S_PARM: OK (Not Supported)
> 	test VIDIOC_G_FBUF: OK (Not Supported)
> 	test VIDIOC_G_FMT: OK
> 	test VIDIOC_TRY_FMT: OK
> 	test VIDIOC_S_FMT: OK
> 	test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> 	test Cropping: OK
> 	test Composing: OK
> 	test Scaling: OK (Not Supported)
>
> Codec ioctls:
> 	test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> 	test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> 	test VIDIOC_(TRY_)DECODER_CMD: OK
>
> Buffer ioctls:
> 	test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> 	test CREATE_BUFS maximum buffers: OK
> 	test VIDIOC_REMOVE_BUFS: OK
> 	test VIDIOC_EXPBUF: OK
> 	test Requests: OK (Not Supported)
> 	test blocking wait: OK
>
> Total for iris_driver device /dev/video0: 48, Succeeded: 48, Failed: 0, Warnings: 0
>
> ~ # v4l2-compliance -d /dev/video1
> v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
>
> Compliance test for iris_driver device /dev/video1:
>
> Driver Info:
> 	Driver name      : iris_driver
> 	Card type        : Iris Encoder
> 	Bus info         : platform:aa00000.video-codec
> 	Driver version   : 7.0.0
> 	Capabilities     : 0x84204000
> 		Video Memory-to-Memory Multiplanar
> 		Streaming
> 		Extended Pix Format
> 		Device Capabilities
> 	Device Caps      : 0x04204000
> 		Video Memory-to-Memory Multiplanar
> 		Streaming
> 		Extended Pix Format
> 	Detected Stateful Encoder
>
> Required ioctls:
> 	test VIDIOC_QUERYCAP: OK
> 	test invalid ioctls: OK
>
> Allow for multiple opens:
> 	test second /dev/video1 open: OK
> 	test VIDIOC_QUERYCAP: OK
> 	test VIDIOC_G/S_PRIORITY: OK
> 	test for unlimited opens: OK
>
> Debug ioctls:
> 	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> 	test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> 	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> 	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> 	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> 	test VIDIOC_ENUMAUDIO: OK (Not Supported)
> 	test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> 	test VIDIOC_G/S_AUDIO: OK (Not Supported)
> 	Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> 	test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> 	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> 	test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> 	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> 	test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> 	Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> 	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> 	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> 	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> 	test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> 	test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> 	test VIDIOC_QUERYCTRL: OK
> 	test VIDIOC_G/S_CTRL: OK
> 	test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> 	test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> 	test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> 	Standard Controls: 43 Private Controls: 0
>
> Format ioctls:
> 	test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> 	test VIDIOC_G/S_PARM: OK
> 	test VIDIOC_G_FBUF: OK (Not Supported)
> 	test VIDIOC_G_FMT: OK
> 	test VIDIOC_TRY_FMT: OK
> 	test VIDIOC_S_FMT: OK
> 	test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> 	test Cropping: OK
> 	test Composing: OK (Not Supported)
> 	test Scaling: OK (Not Supported)
>
> Codec ioctls:
> 	test VIDIOC_(TRY_)ENCODER_CMD: OK
> 	test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> 	test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls:
> 	test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> 	test CREATE_BUFS maximum buffers: OK
> 	test VIDIOC_REMOVE_BUFS: OK
> 	test VIDIOC_EXPBUF: OK
> 	test Requests: OK (Not Supported)
> 	test blocking wait: OK
>
> Total for iris_driver device /dev/video1: 48, Succeeded: 48, Failed: 0, Warnings: 0
You can run the streaming tests also using -s option.
v4l2-compliance -d /dev/video0 -s <clip>
v4l2-compliance -d /dev/video1 -s
> -------------------------------
>
> H264:
> |Test|FFmpeg-H.264-v4l2m2m|
> |-|-|
> |TOTAL|36/135|
> |TOTAL TIME|23.574s|
> |-|-|
> |AUD_MW_E|Pass|
> |BA1_FT_C|Fail|
> |BA1_Sony_D|Pass|
> |BA2_Sony_F|Pass|
> |BA3_SVA_C|Error|
> |BA_MW_D|Fail|
> |BAMQ1_JVC_C|Fail|
> |BAMQ2_JVC_C|Fail|
> |BANM_MW_D|Fail|
> |BASQP1_Sony_C|Fail|
> |CABA1_Sony_D|Fail|
> |CABA1_SVA_B|Pass|
> |CABA2_Sony_E|Pass|
> |CABA2_SVA_B|Pass|
> |CABA3_Sony_C|Fail|
> |CABA3_SVA_B|Pass|
> |CABA3_TOSHIBA_E|Fail|
> |cabac_mot_fld0_full|Fail|
> |cabac_mot_frm0_full|Pass|
> |cabac_mot_mbaff0_full|Fail|
> |cabac_mot_picaff0_full|Fail|
> |CABACI3_Sony_B|Pass|
> |CABAST3_Sony_E|Pass|
> |CABASTBR3_Sony_B|Pass|
> |CABREF3_Sand_D|Fail|
> |CACQP3_Sony_D|Pass|
> |CAFI1_SVA_C|Fail|
> |CAMA1_Sony_C|Fail|
> |CAMA1_TOSHIBA_B|Fail|
> |cama1_vtc_c|Fail|
> |cama2_vtc_b|Fail|
> |CAMA3_Sand_E|Fail|
> |cama3_vtc_b|Fail|
> |CAMACI3_Sony_C|Fail|
> |CAMANL1_TOSHIBA_B|Fail|
> |CAMANL2_TOSHIBA_B|Fail|
> |CAMANL3_Sand_E|Fail|
> |CAMASL3_Sony_B|Fail|
> |CAMP_MOT_MBAFF_L30|Fail|
> |CAMP_MOT_MBAFF_L31|Fail|
> |CANL1_Sony_E|Pass|
> |CANL1_SVA_B|Pass|
> |CANL1_TOSHIBA_G|Fail|
> |CANL2_Sony_E|Fail|
> |CANL2_SVA_B|Fail|
> |CANL3_Sony_C|Fail|
> |CANL3_SVA_B|Fail|
> |CANL4_SVA_B|Fail|
> |CANLMA2_Sony_C|Fail|
> |CANLMA3_Sony_C|Fail|
> |CAPA1_TOSHIBA_B|Fail|
> |CAPAMA3_Sand_F|Fail|
> |CAPCM1_Sand_E|Pass|
> |CAPCMNL1_Sand_E|Fail|
> |CAPM3_Sony_D|Fail|
> |CAQP1_Sony_B|Pass|
> |cavlc_mot_fld0_full_B|Fail|
> |cavlc_mot_frm0_full_B|Pass|
> |cavlc_mot_mbaff0_full_B|Fail|
> |cavlc_mot_picaff0_full_B|Fail|
> |CAWP1_TOSHIBA_E|Pass|
> |CAWP5_TOSHIBA_E|Pass|
> |CI1_FT_B|Pass|
> |CI_MW_D|Pass|
> |CVBS3_Sony_C|Pass|
> |CVCANLMA2_Sony_C|Fail|
> |CVFC1_Sony_C|Fail|
> |CVFI1_Sony_D|Fail|
> |CVFI1_SVA_C|Fail|
> |CVFI2_Sony_H|Fail|
> |CVFI2_SVA_C|Fail|
> |CVMA1_Sony_D|Fail|
> |CVMA1_TOSHIBA_B|Fail|
> |CVMANL1_TOSHIBA_B|Fail|
> |CVMANL2_TOSHIBA_B|Fail|
> |CVMAPAQP3_Sony_E|Fail|
> |CVMAQP2_Sony_G|Fail|
> |CVMAQP3_Sony_D|Fail|
> |CVMP_MOT_FLD_L30_B|Fail|
> |CVMP_MOT_FRM_L31_B|Fail|
> |CVNLFI1_Sony_C|Fail|
> |CVNLFI2_Sony_H|Fail|
> |CVPA1_TOSHIBA_B|Fail|
> |CVPCMNL1_SVA_C|Fail|
> |CVPCMNL2_SVA_C|Pass|
> |CVSE2_Sony_B|Fail|
> |CVSE3_Sony_H|Pass|
> |CVSEFDFT3_Sony_E|Fail|
> |CVWP1_TOSHIBA_E|Fail|
> |CVWP2_TOSHIBA_E|Pass|
> |CVWP3_TOSHIBA_E|Pass|
> |CVWP5_TOSHIBA_E|Fail|
> |FI1_Sony_E|Fail|
> |FM1_BT_B|Error|
> |FM1_FT_E|Error|
> |FM2_SVA_C|Error|
> |HCBP1_HHI_A|Pass|
> |HCBP2_HHI_A|Fail|
> |HCMP1_HHI_A|Fail|
> |LS_SVA_D|Fail|
> |MIDR_MW_D|Fail|
> |MPS_MW_A|Pass|
> |MR1_BT_A|Pass|
> |MR1_MW_A|Fail|
> |MR2_MW_A|Fail|
> |MR2_TANDBERG_E|Pass|
> |MR3_TANDBERG_B|Fail|
> |MR4_TANDBERG_C|Fail|
> |MR5_TANDBERG_C|Fail|
> |MR6_BT_B|Error|
> |MR7_BT_B|Error|
> |MR8_BT_B|Error|
> |MR9_BT_B|Fail|
> |MV1_BRCM_D|Pass|
> |NL1_Sony_D|Fail|
> |NL2_Sony_H|Pass|
> |NL3_SVA_E|Fail|
> |NLMQ1_JVC_C|Fail|
> |NLMQ2_JVC_C|Pass|
> |NRF_MW_E|Fail|
> |Sharp_MP_Field_1_B|Fail|
> |Sharp_MP_Field_2_B|Fail|
> |Sharp_MP_Field_3_B|Fail|
> |Sharp_MP_PAFF_1r2|Fail|
> |Sharp_MP_PAFF_2r|Fail|
> |SL1_SVA_B|Pass|
> |SP1_BT_A|Error|
> |sp2_bt_b|Error|
> |SVA_BA1_B|Pass|
> |SVA_BA2_D|Pass|
> |SVA_Base_B|Fail|
> |SVA_CL1_E|Fail|
> |SVA_FM1_E|Fail|
> |SVA_NL1_B|Fail|
> |SVA_NL2_E|Fail|
> |-|-|
> |Test|FFmpeg-H.264-v4l2m2m|
> |TOTAL|36/135|
> |TOTAL TIME|23.574s|
>
> |-|-|
> |Profile|FFmpeg-H.264-v4l2m2m|
> |CONSTRAINED_BASELINE|12/33|
> |BASELINE|1/7|
> |EXTENDED|0/6|
> |MAIN|23/89|
>
> |TOTALS|FFmpeg-H.264-v4l2m2m|
> |-|-|
> |TOTAL|36/135|
> |TOTAL TIME|23.574s|
> |-|-|
> |Profile|FFmpeg-H.264-v4l2m2m|
> |BASELINE|1/7|
> |CONSTRAINED_BASELINE|12/33|
> |EXTENDED|0/6|
> |MAIN|23/89|
> |-|-|
>
> -------------------------------
>
> |Test|FFmpeg-H.265-v4l2m2m|
> |-|-|
> |TOTAL|109/147|
> |TOTAL TIME|38.547s|
> |-|-|
> |AMP_A_Samsung_7|Pass|
> |AMP_B_Samsung_7|Pass|
> |AMP_D_Hisilicon_3|Pass|
> |AMP_E_Hisilicon_3|Pass|
> |AMP_F_Hisilicon_3|Pass|
> |AMVP_A_MTK_4|Pass|
> |AMVP_B_MTK_4|Fail|
> |AMVP_C_Samsung_7|Pass|
> |BUMPING_A_ericsson_1|Fail|
> |CAINIT_A_SHARP_4|Pass|
> |CAINIT_B_SHARP_4|Pass|
> |CAINIT_C_SHARP_3|Pass|
> |CAINIT_D_SHARP_3|Pass|
> |CAINIT_E_SHARP_3|Pass|
> |CAINIT_F_SHARP_3|Pass|
> |CAINIT_G_SHARP_3|Pass|
> |CAINIT_H_SHARP_3|Pass|
> |CIP_A_Panasonic_3|Pass|
> |cip_B_NEC_3|Pass|
> |CIP_C_Panasonic_2|Pass|
> |CONFWIN_A_Sony_1|Fail|
> |DBLK_A_MAIN10_VIXS_4|Fail|
> |DBLK_A_SONY_3|Pass|
> |DBLK_B_SONY_3|Pass|
> |DBLK_C_SONY_3|Pass|
> |DBLK_D_VIXS_2|Pass|
> |DBLK_E_VIXS_2|Pass|
> |DBLK_F_VIXS_2|Pass|
> |DBLK_G_VIXS_2|Pass|
> |DELTAQP_A_BRCM_4|Pass|
> |DELTAQP_B_SONY_3|Pass|
> |DELTAQP_C_SONY_3|Pass|
> |DSLICE_A_HHI_5|Pass|
> |DSLICE_B_HHI_5|Pass|
> |DSLICE_C_HHI_5|Pass|
> |ENTP_A_QUALCOMM_1|Pass|
> |ENTP_B_Qualcomm_1|Pass|
> |ENTP_C_Qualcomm_1|Pass|
> |EXT_A_ericsson_4|Pass|
> |FILLER_A_Sony_1|Pass|
> |HRD_A_Fujitsu_3|Pass|
> |INITQP_A_Sony_1|Pass|
> |INITQP_B_Main10_Sony_1|Fail|
> |ipcm_A_NEC_3|Fail|
> |ipcm_B_NEC_3|Pass|
> |ipcm_C_NEC_3|Pass|
> |ipcm_D_NEC_3|Pass|
> |ipcm_E_NEC_2|Pass|
> |IPRED_A_docomo_2|Pass|
> |IPRED_B_Nokia_3|Pass|
> |IPRED_C_Mitsubishi_3|Pass|
> |LS_A_Orange_2|Pass|
> |LS_B_Orange_4|Pass|
> |LTRPSPS_A_Qualcomm_1|Fail|
> |MAXBINS_A_TI_5|Pass|
> |MAXBINS_B_TI_5|Pass|
> |MAXBINS_C_TI_5|Pass|
> |MERGE_A_TI_3|Pass|
> |MERGE_B_TI_3|Pass|
> |MERGE_C_TI_3|Fail|
> |MERGE_D_TI_3|Fail|
> |MERGE_E_TI_3|Pass|
> |MERGE_F_MTK_4|Pass|
> |MERGE_G_HHI_4|Pass|
> |MVCLIP_A_qualcomm_3|Fail|
> |MVDL1ZERO_A_docomo_4|Pass|
> |MVEDGE_A_qualcomm_3|Fail|
> |NoOutPrior_A_Qualcomm_1|Fail|
> |NoOutPrior_B_Qualcomm_1|Fail|
> |NUT_A_ericsson_5|Fail|
> |OPFLAG_A_Qualcomm_1|Pass|
> |OPFLAG_B_Qualcomm_1|Fail|
> |OPFLAG_C_Qualcomm_1|Fail|
> |PICSIZE_A_Bossen_1|Error|
> |PICSIZE_B_Bossen_1|Error|
> |PICSIZE_C_Bossen_1|Error|
> |PICSIZE_D_Bossen_1|Error|
> |PMERGE_A_TI_3|Pass|
> |PMERGE_B_TI_3|Pass|
> |PMERGE_C_TI_3|Pass|
> |PMERGE_D_TI_3|Pass|
> |PMERGE_E_TI_3|Pass|
> |POC_A_Bossen_3|Pass|
> |PPS_A_qualcomm_7|Pass|
> |PS_B_VIDYO_3|Pass|
> |RAP_A_docomo_6|Fail|
> |RAP_B_Bossen_2|Fail|
> |RPLM_A_qualcomm_4|Pass|
> |RPLM_B_qualcomm_4|Pass|
> |RPS_A_docomo_5|Pass|
> |RPS_B_qualcomm_5|Pass|
> |RPS_C_ericsson_5|Pass|
> |RPS_D_ericsson_6|Pass|
> |RPS_E_qualcomm_5|Pass|
> |RPS_F_docomo_2|Pass|
> |RQT_A_HHI_4|Pass|
> |RQT_B_HHI_4|Pass|
> |RQT_C_HHI_4|Pass|
> |RQT_D_HHI_4|Pass|
> |RQT_E_HHI_4|Pass|
> |RQT_F_HHI_4|Pass|
> |RQT_G_HHI_4|Pass|
> |SAO_A_MediaTek_4|Fail|
> |SAO_B_MediaTek_5|Pass|
> |SAO_C_Samsung_5|Pass|
> |SAO_D_Samsung_5|Pass|
> |SAO_E_Canon_4|Pass|
> |SAO_F_Canon_3|Pass|
> |SAO_G_Canon_3|Pass|
> |SAO_H_Parabola_1|Pass|
> |SAODBLK_A_MainConcept_4|Pass|
> |SAODBLK_B_MainConcept_4|Pass|
> |SDH_A_Orange_4|Pass|
> |SLICES_A_Rovi_3|Pass|
> |SLIST_A_Sony_5|Pass|
> |SLIST_B_Sony_9|Pass|
> |SLIST_C_Sony_4|Pass|
> |SLIST_D_Sony_9|Pass|
> |SLPPLP_A_VIDYO_2|Pass|
> |STRUCT_A_Samsung_7|Pass|
> |STRUCT_B_Samsung_7|Pass|
> |TILES_A_Cisco_2|Pass|
> |TILES_B_Cisco_1|Pass|
> |TMVP_A_MS_3|Pass|
> |TSCL_A_VIDYO_5|Fail|
> |TSCL_B_VIDYO_4|Pass|
> |TSKIP_A_MS_3|Pass|
> |TSUNEQBD_A_MAIN10_Technicolor_2|Error|
> |TUSIZE_A_Samsung_1|Pass|
> |VPSID_A_VIDYO_2|Pass|
> |VPSSPSPPS_A_MainConcept_1|Fail|
> |WP_A_MAIN10_Toshiba_3|Fail|
> |WP_A_Toshiba_3|Pass|
> |WP_B_Toshiba_3|Pass|
> |WP_MAIN10_B_Toshiba_3|Fail|
> |WPP_A_ericsson_MAIN10_2|Fail|
> |WPP_A_ericsson_MAIN_2|Pass|
> |WPP_B_ericsson_MAIN10_2|Fail|
> |WPP_B_ericsson_MAIN_2|Fail|
> |WPP_C_ericsson_MAIN10_2|Fail|
> |WPP_C_ericsson_MAIN_2|Fail|
> |WPP_D_ericsson_MAIN10_2|Error|
> |WPP_D_ericsson_MAIN_2|Error|
> |WPP_E_ericsson_MAIN10_2|Fail|
> |WPP_E_ericsson_MAIN_2|Fail|
> |WPP_F_ericsson_MAIN10_2|Fail|
> |WPP_F_ericsson_MAIN_2|Pass|
> |-|-|
> |Test|FFmpeg-H.265-v4l2m2m|
> |TOTAL|109/147|
> |TOTAL TIME|38.547s|
>
> |-|-|
> |Profile|FFmpeg-H.265-v4l2m2m|
> |MAIN|108/135|
> |MAIN_10|0/11|
> |MAIN_STILL_PICTURE|1/1|
>
> |TOTALS|FFmpeg-H.265-v4l2m2m|
> |-|-|
> |TOTAL|109/147|
> |TOTAL TIME|38.547s|
> |-|-|
> |Profile|FFmpeg-H.265-v4l2m2m|
> |MAIN|108/135|
> |MAIN_10|0/11|
> |MAIN_STILL_PICTURE|1/1|
> |-|-|
>
> -------------------------------
>
> |Test|FFmpeg-VP9-v4l2m2m|
> |-|-|
> |TOTAL|111/305|
> |TOTAL TIME|77.260s|
> |-|-|
> |vp90-2-00-quantizer-00.webm|Pass|
> |vp90-2-00-quantizer-01.webm|Pass|
> |vp90-2-00-quantizer-02.webm|Pass|
> |vp90-2-00-quantizer-03.webm|Fail|
> |vp90-2-00-quantizer-04.webm|Fail|
> |vp90-2-00-quantizer-05.webm|Pass|
> |vp90-2-00-quantizer-06.webm|Pass|
> |vp90-2-00-quantizer-07.webm|Pass|
> |vp90-2-00-quantizer-08.webm|Fail|
> |vp90-2-00-quantizer-09.webm|Pass|
> |vp90-2-00-quantizer-10.webm|Pass|
> |vp90-2-00-quantizer-11.webm|Pass|
> |vp90-2-00-quantizer-12.webm|Pass|
> |vp90-2-00-quantizer-13.webm|Pass|
> |vp90-2-00-quantizer-14.webm|Pass|
> |vp90-2-00-quantizer-15.webm|Pass|
> |vp90-2-00-quantizer-16.webm|Fail|
> |vp90-2-00-quantizer-17.webm|Pass|
> |vp90-2-00-quantizer-18.webm|Pass|
> |vp90-2-00-quantizer-19.webm|Pass|
> |vp90-2-00-quantizer-20.webm|Pass|
> |vp90-2-00-quantizer-21.webm|Pass|
> |vp90-2-00-quantizer-22.webm|Pass|
> |vp90-2-00-quantizer-23.webm|Pass|
> |vp90-2-00-quantizer-24.webm|Pass|
> |vp90-2-00-quantizer-25.webm|Fail|
> |vp90-2-00-quantizer-26.webm|Fail|
> |vp90-2-00-quantizer-27.webm|Pass|
> |vp90-2-00-quantizer-28.webm|Pass|
> |vp90-2-00-quantizer-29.webm|Fail|
> |vp90-2-00-quantizer-30.webm|Pass|
> |vp90-2-00-quantizer-31.webm|Pass|
> |vp90-2-00-quantizer-32.webm|Fail|
> |vp90-2-00-quantizer-33.webm|Pass|
> |vp90-2-00-quantizer-34.webm|Pass|
> |vp90-2-00-quantizer-35.webm|Pass|
> |vp90-2-00-quantizer-36.webm|Pass|
> |vp90-2-00-quantizer-37.webm|Pass|
> |vp90-2-00-quantizer-38.webm|Pass|
> |vp90-2-00-quantizer-39.webm|Pass|
> |vp90-2-00-quantizer-40.webm|Pass|
> |vp90-2-00-quantizer-41.webm|Pass|
> |vp90-2-00-quantizer-42.webm|Pass|
> |vp90-2-00-quantizer-43.webm|Pass|
> |vp90-2-00-quantizer-44.webm|Fail|
> |vp90-2-00-quantizer-45.webm|Pass|
> |vp90-2-00-quantizer-46.webm|Pass|
> |vp90-2-00-quantizer-47.webm|Pass|
> |vp90-2-00-quantizer-48.webm|Pass|
> |vp90-2-00-quantizer-49.webm|Pass|
> |vp90-2-00-quantizer-50.webm|Fail|
> |vp90-2-00-quantizer-51.webm|Pass|
> |vp90-2-00-quantizer-52.webm|Pass|
> |vp90-2-00-quantizer-53.webm|Pass|
> |vp90-2-00-quantizer-54.webm|Pass|
> |vp90-2-00-quantizer-55.webm|Pass|
> |vp90-2-00-quantizer-56.webm|Pass|
> |vp90-2-00-quantizer-57.webm|Pass|
> |vp90-2-00-quantizer-58.webm|Pass|
> |vp90-2-00-quantizer-59.webm|Fail|
> |vp90-2-00-quantizer-60.webm|Pass|
> |vp90-2-00-quantizer-61.webm|Pass|
> |vp90-2-00-quantizer-62.webm|Pass|
> |vp90-2-00-quantizer-63.webm|Fail|
> |vp90-2-01-sharpness-1.webm|Pass|
> |vp90-2-01-sharpness-2.webm|Pass|
> |vp90-2-01-sharpness-3.webm|Pass|
> |vp90-2-01-sharpness-4.webm|Pass|
> |vp90-2-01-sharpness-5.webm|Pass|
> |vp90-2-01-sharpness-6.webm|Pass|
> |vp90-2-01-sharpness-7.webm|Pass|
> |vp90-2-02-size-08x08.webm|Error|
> |vp90-2-02-size-08x10.webm|Error|
> |vp90-2-02-size-08x16.webm|Error|
> |vp90-2-02-size-08x18.webm|Error|
> |vp90-2-02-size-08x32.webm|Error|
> |vp90-2-02-size-08x34.webm|Error|
> |vp90-2-02-size-08x64.webm|Error|
> |vp90-2-02-size-08x66.webm|Error|
> |vp90-2-02-size-10x08.webm|Error|
> |vp90-2-02-size-10x10.webm|Error|
> |vp90-2-02-size-10x16.webm|Error|
> |vp90-2-02-size-10x18.webm|Error|
> |vp90-2-02-size-10x32.webm|Error|
> |vp90-2-02-size-10x34.webm|Error|
> |vp90-2-02-size-10x64.webm|Error|
> |vp90-2-02-size-10x66.webm|Error|
> |vp90-2-02-size-130x132.webm|Fail|
> |vp90-2-02-size-132x130.webm|Pass|
> |vp90-2-02-size-132x132.webm|Pass|
> |vp90-2-02-size-16x08.webm|Error|
> |vp90-2-02-size-16x10.webm|Error|
> |vp90-2-02-size-16x16.webm|Error|
> |vp90-2-02-size-16x18.webm|Error|
> |vp90-2-02-size-16x32.webm|Error|
> |vp90-2-02-size-16x34.webm|Error|
> |vp90-2-02-size-16x64.webm|Error|
> |vp90-2-02-size-16x66.webm|Error|
> |vp90-2-02-size-178x180.webm|Fail|
> |vp90-2-02-size-180x178.webm|Pass|
> |vp90-2-02-size-180x180.webm|Fail|
> |vp90-2-02-size-18x08.webm|Error|
> |vp90-2-02-size-18x10.webm|Error|
> |vp90-2-02-size-18x16.webm|Error|
> |vp90-2-02-size-18x18.webm|Error|
> |vp90-2-02-size-18x32.webm|Error|
> |vp90-2-02-size-18x34.webm|Error|
> |vp90-2-02-size-18x64.webm|Error|
> |vp90-2-02-size-18x66.webm|Error|
> |vp90-2-02-size-32x08.webm|Error|
> |vp90-2-02-size-32x10.webm|Error|
> |vp90-2-02-size-32x16.webm|Error|
> |vp90-2-02-size-32x18.webm|Error|
> |vp90-2-02-size-32x32.webm|Error|
> |vp90-2-02-size-32x34.webm|Error|
> |vp90-2-02-size-32x64.webm|Error|
> |vp90-2-02-size-32x66.webm|Error|
> |vp90-2-02-size-34x08.webm|Error|
> |vp90-2-02-size-34x10.webm|Error|
> |vp90-2-02-size-34x16.webm|Error|
> |vp90-2-02-size-34x18.webm|Error|
> |vp90-2-02-size-34x32.webm|Error|
> |vp90-2-02-size-34x34.webm|Error|
> |vp90-2-02-size-34x64.webm|Error|
> |vp90-2-02-size-34x66.webm|Error|
> |vp90-2-02-size-64x08.webm|Error|
> |vp90-2-02-size-64x10.webm|Error|
> |vp90-2-02-size-64x16.webm|Error|
> |vp90-2-02-size-64x18.webm|Error|
> |vp90-2-02-size-64x32.webm|Error|
> |vp90-2-02-size-64x34.webm|Error|
> |vp90-2-02-size-64x64.webm|Error|
> |vp90-2-02-size-64x66.webm|Error|
> |vp90-2-02-size-66x08.webm|Error|
> |vp90-2-02-size-66x10.webm|Error|
> |vp90-2-02-size-66x16.webm|Error|
> |vp90-2-02-size-66x18.webm|Error|
> |vp90-2-02-size-66x32.webm|Error|
> |vp90-2-02-size-66x34.webm|Error|
> |vp90-2-02-size-66x64.webm|Error|
> |vp90-2-02-size-66x66.webm|Error|
> |vp90-2-02-size-lf-1920x1080.webm|Fail|
> |vp90-2-03-deltaq.webm|Fail|
> |vp90-2-03-size-196x196.webm|Pass|
> |vp90-2-03-size-196x198.webm|Pass|
> |vp90-2-03-size-196x200.webm|Pass|
> |vp90-2-03-size-196x202.webm|Pass|
> |vp90-2-03-size-196x208.webm|Fail|
> |vp90-2-03-size-196x210.webm|Fail|
> |vp90-2-03-size-196x224.webm|Pass|
> |vp90-2-03-size-196x226.webm|Fail|
> |vp90-2-03-size-198x196.webm|Fail|
> |vp90-2-03-size-198x198.webm|Pass|
> |vp90-2-03-size-198x200.webm|Pass|
> |vp90-2-03-size-198x202.webm|Pass|
> |vp90-2-03-size-198x208.webm|Pass|
> |vp90-2-03-size-198x210.webm|Fail|
> |vp90-2-03-size-198x224.webm|Pass|
> |vp90-2-03-size-198x226.webm|Fail|
> |vp90-2-03-size-200x196.webm|Fail|
> |vp90-2-03-size-200x198.webm|Fail|
> |vp90-2-03-size-200x200.webm|Fail|
> |vp90-2-03-size-200x202.webm|Pass|
> |vp90-2-03-size-200x208.webm|Fail|
> |vp90-2-03-size-200x210.webm|Fail|
> |vp90-2-03-size-200x224.webm|Pass|
> |vp90-2-03-size-200x226.webm|Fail|
> |vp90-2-03-size-202x196.webm|Fail|
> |vp90-2-03-size-202x198.webm|Fail|
> |vp90-2-03-size-202x200.webm|Fail|
> |vp90-2-03-size-202x202.webm|Fail|
> |vp90-2-03-size-202x208.webm|Pass|
> |vp90-2-03-size-202x210.webm|Fail|
> |vp90-2-03-size-202x224.webm|Fail|
> |vp90-2-03-size-202x226.webm|Pass|
> |vp90-2-03-size-208x196.webm|Pass|
> |vp90-2-03-size-208x198.webm|Pass|
> |vp90-2-03-size-208x200.webm|Pass|
> |vp90-2-03-size-208x202.webm|Pass|
> |vp90-2-03-size-208x208.webm|Pass|
> |vp90-2-03-size-208x210.webm|Pass|
> |vp90-2-03-size-208x224.webm|Pass|
> |vp90-2-03-size-208x226.webm|Pass|
> |vp90-2-03-size-210x196.webm|Pass|
> |vp90-2-03-size-210x198.webm|Pass|
> |vp90-2-03-size-210x200.webm|Fail|
> |vp90-2-03-size-210x202.webm|Pass|
> |vp90-2-03-size-210x208.webm|Pass|
> |vp90-2-03-size-210x210.webm|Fail|
> |vp90-2-03-size-210x224.webm|Pass|
> |vp90-2-03-size-210x226.webm|Fail|
> |vp90-2-03-size-224x196.webm|Fail|
> |vp90-2-03-size-224x198.webm|Pass|
> |vp90-2-03-size-224x200.webm|Pass|
> |vp90-2-03-size-224x202.webm|Fail|
> |vp90-2-03-size-224x208.webm|Pass|
> |vp90-2-03-size-224x210.webm|Fail|
> |vp90-2-03-size-224x224.webm|Pass|
> |vp90-2-03-size-224x226.webm|Pass|
> |vp90-2-03-size-226x196.webm|Pass|
> |vp90-2-03-size-226x198.webm|Fail|
> |vp90-2-03-size-226x200.webm|Fail|
> |vp90-2-03-size-226x202.webm|Fail|
> |vp90-2-03-size-226x208.webm|Pass|
> |vp90-2-03-size-226x210.webm|Pass|
> |vp90-2-03-size-226x224.webm|Fail|
> |vp90-2-03-size-226x226.webm|Fail|
> |vp90-2-03-size-352x288.webm|Pass|
> |vp90-2-05-resize.ivf|Fail|
> |vp90-2-06-bilinear.webm|Pass|
> |vp90-2-07-frame_parallel-1.webm|Pass|
> |vp90-2-07-frame_parallel.webm|Fail|
> |vp90-2-08-tile_1x2_frame_parallel.webm|Fail|
> |vp90-2-08-tile_1x2.webm|Fail|
> |vp90-2-08-tile_1x4_frame_parallel.webm|Fail|
> |vp90-2-08-tile_1x4.webm|Fail|
> |vp90-2-08-tile_1x8_frame_parallel.webm|Pass|
> |vp90-2-08-tile_1x8.webm|Pass|
> |vp90-2-08-tile-4x1.webm|Pass|
> |vp90-2-08-tile-4x4.webm|Pass|
> |vp90-2-09-aq2.webm|Fail|
> |vp90-2-09-lf_deltas.webm|Fail|
> |vp90-2-09-subpixel-00.ivf|Fail|
> |vp90-2-10-show-existing-frame2.webm|Fail|
> |vp90-2-10-show-existing-frame.webm|Fail|
> |vp90-2-11-size-351x287.webm|Fail|
> |vp90-2-11-size-351x288.webm|Fail|
> |vp90-2-11-size-352x287.webm|Fail|
> |vp90-2-12-droppable_1.ivf|Pass|
> |vp90-2-12-droppable_2.ivf|Pass|
> |vp90-2-12-droppable_3.ivf|Pass|
> |vp90-2-14-resize-10frames-fp-tiles-1-2-4-8.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-1-2.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-1-4.webm|Fail|
> |vp90-2-14-resize-10frames-fp-tiles-1-8.webm|Fail|
> |vp90-2-14-resize-10frames-fp-tiles-2-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-2-4.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-2-8.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-4-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-4-2.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-4-8.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-2.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-4-2-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-4.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-1-16.webm|Fail|
> |vp90-2-14-resize-fp-tiles-1-2-4-8-16.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-1-2.webm|Fail|
> |vp90-2-14-resize-fp-tiles-1-4.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-16-1.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-2.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-4.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-8-4-2-1.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-8.webm|Error|
> |vp90-2-14-resize-fp-tiles-1-8.webm|Fail|
> |vp90-2-14-resize-fp-tiles-2-16.webm|Error|
> |vp90-2-14-resize-fp-tiles-2-1.webm|Fail|
> |vp90-2-14-resize-fp-tiles-2-4.webm|Fail|
> |vp90-2-14-resize-fp-tiles-2-8.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-4-16.webm|Error|
> |vp90-2-14-resize-fp-tiles-4-1.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-4-2.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-4-8.webm|Fail|
> |vp90-2-14-resize-fp-tiles-8-16.webm|Error|
> |vp90-2-14-resize-fp-tiles-8-1.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-8-2.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-8-4.webm|Timeout|
> |vp90-2-15-segkey_adpq.webm|Fail|
> |vp90-2-15-segkey.webm|Pass|
> |vp90-2-16-intra-only.webm|Fail|
> |vp90-2-17-show-existing-frame.webm|Pass|
> |vp90-2-18-resize.ivf|Fail|
> |vp90-2-19-skip-01.webm|Fail|
> |vp90-2-19-skip-02.webm|Fail|
> |vp90-2-19-skip.webm|Pass|
> |vp90-2-20-big_superframe-01.webm|Fail|
> |vp90-2-20-big_superframe-02.webm|Fail|
> |vp90-2-21-resize_inter_1280x720_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_1280x720_5_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_1280x720_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_1280x720_7_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_5_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_7_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_7_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_320x180_5_1-2.webm|Fail|
> |vp90-2-21-resize_inter_320x180_5_3-4.webm|Fail|
> |vp90-2-21-resize_inter_320x180_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_320x180_7_3-4.webm|Fail|
> |vp90-2-21-resize_inter_320x240_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_320x240_5_3-4.webm|Fail|
> |vp90-2-21-resize_inter_320x240_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_320x240_7_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_640x360_5_1-2.webm|Fail|
> |vp90-2-21-resize_inter_640x360_5_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_640x360_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_640x360_7_3-4.webm|Fail|
> |vp90-2-21-resize_inter_640x480_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_640x480_5_3-4.webm|Fail|
> |vp90-2-21-resize_inter_640x480_7_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_640x480_7_3-4.webm|Timeout|
> |vp90-2-22-svc_1280x720_1.webm|Pass|
> |vp90-2-22-svc_1280x720_3.ivf|Timeout|
> |vp91-2-04-yuv422.webm|Error|
> |vp91-2-04-yuv444.webm|Error|
> |-|-|
> |Test|FFmpeg-VP9-v4l2m2m|
> |TOTAL|111/305|
> |TOTAL TIME|77.260s|
>
> |TOTALS|FFmpeg-VP9-v4l2m2m|
> |-|-|
> |TOTAL|111/305|
> |TOTAL TIME|77.260s|
> |-|-|
>
> Signed-off-by: Alexander Koskovich<akoskovich@pm.me>
> ---
> Alexander Koskovich (3):
>        dt-bindings: media: qcom,milos-iris: Add Milos video codec
>        media: iris: Add support for Milos (VPU v2.0)
>        arm64: dts: qcom: milos: Add Iris VPU v2.0
>
>   .../devicetree/bindings/media/qcom,milos-iris.yaml | 166 ++++++
>   arch/arm64/boot/dts/qcom/milos.dtsi                |  85 +++
>   .../platform/qcom/iris/iris_platform_common.h      |   1 +
>   .../media/platform/qcom/iris/iris_platform_gen2.c  | 106 ++++
>   .../media/platform/qcom/iris/iris_platform_milos.h | 655 +++++++++++++++++++++
>   drivers/media/platform/qcom/iris/iris_probe.c      |   4 +
>   6 files changed, 1017 insertions(+)
> ---
> base-commit: 591cd656a1bf5ea94a222af5ef2ee76df029c1d2
> change-id: 20260406-milos-iris-d1a854e4cb75
>
> Best regards,