* [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe
@ 2023-05-16 6:22 Achal Verma
2023-05-16 6:33 ` Siddharth Vadapalli
2023-05-16 13:13 ` Nishanth Menon
0 siblings, 2 replies; 5+ messages in thread
From: Achal Verma @ 2023-05-16 6:22 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, devicetree, linux-kernel, Achal Verma
From: Matt Ranostay <mranostay@ti.com>
J7200 has a limited 2x support for PCIe, and the properties should be
updated as such.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index ef352e32f19d..5e62b431d6e8 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
- num-lanes = <4>;
+ num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 6>;
clock-names = "fck";
@@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
- num-lanes = <4>;
+ num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 6>;
clock-names = "fck";
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe
2023-05-16 6:22 [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe Achal Verma
@ 2023-05-16 6:33 ` Siddharth Vadapalli
2023-05-16 9:01 ` Verma, Achal
2023-05-16 13:13 ` Nishanth Menon
1 sibling, 1 reply; 5+ messages in thread
From: Siddharth Vadapalli @ 2023-05-16 6:33 UTC (permalink / raw)
To: Achal Verma
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel, s-vadapalli
Achal,
On 16/05/23 11:52, Achal Verma wrote:
> From: Matt Ranostay <mranostay@ti.com>
>
> J7200 has a limited 2x support for PCIe, and the properties should be
> updated as such.
According to J7200 Datasheet at [0], the SoC supports up to x4 PCIe lanes. Could
you please clarify where the lanes are documented to be 2x?
[0]: https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index ef352e32f19d..5e62b431d6e8 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
> device_type = "pci";
> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
> max-link-speed = <3>;
> - num-lanes = <4>;
> + num-lanes = <2>;
> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 240 6>;
> clock-names = "fck";
> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
> interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
> max-link-speed = <3>;
> - num-lanes = <4>;
> + num-lanes = <2>;
> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 240 6>;
> clock-names = "fck";
--
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe
2023-05-16 6:33 ` Siddharth Vadapalli
@ 2023-05-16 9:01 ` Verma, Achal
0 siblings, 0 replies; 5+ messages in thread
From: Verma, Achal @ 2023-05-16 9:01 UTC (permalink / raw)
To: Siddharth Vadapalli
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel, Achal Verma
On 5/16/2023 12:03 PM, Siddharth Vadapalli wrote:
> Achal,
>
> On 16/05/23 11:52, Achal Verma wrote:
>> From: Matt Ranostay <mranostay@ti.com>
>>
>> J7200 has a limited 2x support for PCIe, and the properties should be
>> updated as such.
>
> According to J7200 Datasheet at [0], the SoC supports up to x4 PCIe lanes. Could
> you please clarify where the lanes are documented to be 2x?
>
> [0]: https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
Yes, this patch should be dropped.
No need to change lanes.
Regards,
Achal Verma
>
>>
>> Signed-off-by: Matt Ranostay <mranostay@ti.com>
>> Signed-off-by: Achal Verma <a-verma1@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> index ef352e32f19d..5e62b431d6e8 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
>> device_type = "pci";
>> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>> max-link-speed = <3>;
>> - num-lanes = <4>;
>> + num-lanes = <2>;
>> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 240 6>;
>> clock-names = "fck";
>> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
>> interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>> max-link-speed = <3>;
>> - num-lanes = <4>;
>> + num-lanes = <2>;
>> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 240 6>;
>> clock-names = "fck";
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe
2023-05-16 6:22 [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe Achal Verma
2023-05-16 6:33 ` Siddharth Vadapalli
@ 2023-05-16 13:13 ` Nishanth Menon
2023-05-16 16:24 ` Verma, Achal
1 sibling, 1 reply; 5+ messages in thread
From: Nishanth Menon @ 2023-05-16 13:13 UTC (permalink / raw)
To: Achal Verma
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel
On 11:52-20230516, Achal Verma wrote:
> From: Matt Ranostay <mranostay@ti.com>
>
> J7200 has a limited 2x support for PCIe, and the properties should be
> updated as such.
>
What commit does this fix?
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index ef352e32f19d..5e62b431d6e8 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
> device_type = "pci";
> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
> max-link-speed = <3>;
> - num-lanes = <4>;
> + num-lanes = <2>;
> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 240 6>;
> clock-names = "fck";
> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
> interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
> max-link-speed = <3>;
> - num-lanes = <4>;
> + num-lanes = <2>;
> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
> clocks = <&k3_clks 240 6>;
> clock-names = "fck";
> --
> 2.25.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe
2023-05-16 13:13 ` Nishanth Menon
@ 2023-05-16 16:24 ` Verma, Achal
0 siblings, 0 replies; 5+ messages in thread
From: Verma, Achal @ 2023-05-16 16:24 UTC (permalink / raw)
To: Nishanth Menon
Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree,
linux-kernel, Achal Verma
On 5/16/2023 6:43 PM, Nishanth Menon wrote:
> On 11:52-20230516, Achal Verma wrote:
>> From: Matt Ranostay <mranostay@ti.com>
>>
>> J7200 has a limited 2x support for PCIe, and the properties should be
>> updated as such.
>>
>
> What commit does this fix?
This patch is a mistake.
J7200 PCIe has 4 lanes, and this patch should be dropped.
Regards,
Achal Verma
>
>> Signed-off-by: Matt Ranostay <mranostay@ti.com>
>> Signed-off-by: Achal Verma <a-verma1@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> index ef352e32f19d..5e62b431d6e8 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
>> device_type = "pci";
>> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>> max-link-speed = <3>;
>> - num-lanes = <4>;
>> + num-lanes = <2>;
>> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 240 6>;
>> clock-names = "fck";
>> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
>> interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>> ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>> max-link-speed = <3>;
>> - num-lanes = <4>;
>> + num-lanes = <2>;
>> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> clocks = <&k3_clks 240 6>;
>> clock-names = "fck";
>> --
>> 2.25.1
>>
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2023-05-16 6:22 [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe Achal Verma
2023-05-16 6:33 ` Siddharth Vadapalli
2023-05-16 9:01 ` Verma, Achal
2023-05-16 13:13 ` Nishanth Menon
2023-05-16 16:24 ` Verma, Achal
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