* [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT
@ 2023-05-15 15:19 Rafał Miłecki
2023-05-15 15:19 ` [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts " Rafał Miłecki
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Rafał Miłecki @ 2023-05-15 15:19 UTC (permalink / raw)
To: Florian Fainelli
Cc: Hauke Mehrtens, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel, devicetree, bcm-kernel-feedback-list,
Rafał Miłecki
From: Rafał Miłecki <rafal@milecki.pl>
Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing.
That syncs more Northstar code to be based on the same licensing schema.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/arm/boot/dts/bcm-ns.dtsi | 90 +++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm5301x.dtsi | 85 -------------------------------
2 files changed, 90 insertions(+), 85 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi
index cc977bbc142b..58c30e3a142f 100644
--- a/arch/arm/boot/dts/bcm-ns.dtsi
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
@@ -1,4 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
+ */
#include <dt-bindings/clock/bcm-nsp.h>
#include <dt-bindings/gpio/gpio.h>
@@ -7,6 +10,81 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chipcommon-a-bus@18000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x18000000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@300 {
+ compatible = "ns16550";
+ reg = <0x0300 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&iprocslow>;
+ status = "disabled";
+ };
+
+ uart1: serial@400 {
+ compatible = "ns16550";
+ reg = <0x0400 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&iprocslow>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_uart1>;
+ status = "disabled";
+ };
+ };
+
+ mpcore-bus@19000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x19000000 0x00023000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scu@20000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x20000 0x100>;
+ };
+
+ timer@20200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&periph_clk>;
+ };
+
+ timer@20600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x20600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
+ gic: interrupt-controller@21000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
+ };
+
+ L2: cache-controller@22000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ arm,shared-override;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ cache-level = <2>;
+ };
+ };
+
axi@18000000 {
compatible = "brcm,bus-axi";
reg = <0x18000000 0x1000>;
@@ -216,6 +294,18 @@ thermal: thermal@2c0 {
};
};
+ nand_controller: nand-controller@18028000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
+ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcm,nand-has-wp;
+ };
+
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index bc36edc24510..d6c31ead0398 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -11,41 +11,7 @@
#include "bcm-ns.dtsi"
/ {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
-
- chipcommon-a-bus@18000000 {
- compatible = "simple-bus";
- ranges = <0x00000000 0x18000000 0x00001000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- uart0: serial@300 {
- compatible = "ns16550";
- reg = <0x0300 0x100>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&iprocslow>;
- status = "disabled";
- };
-
- uart1: serial@400 {
- compatible = "ns16550";
- reg = <0x0400 0x100>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&iprocslow>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_uart1>;
- status = "disabled";
- };
- };
-
mpcore-bus@19000000 {
- compatible = "simple-bus";
- ranges = <0x00000000 0x19000000 0x00023000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
a9pll: arm_clk@0 {
#clock-cells = <0>;
compatible = "brcm,nsp-armpll";
@@ -53,26 +19,6 @@ a9pll: arm_clk@0 {
reg = <0x00000 0x1000>;
};
- scu@20000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0x20000 0x100>;
- };
-
- timer@20200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x20200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
- clocks = <&periph_clk>;
- };
-
- timer@20600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20600 0x20>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_EDGE_RISING)>;
- clocks = <&periph_clk>;
- };
-
watchdog@20620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x20620 0x20>;
@@ -80,25 +26,6 @@ watchdog@20620 {
IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};
-
- gic: interrupt-controller@21000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x21000 0x1000>,
- <0x20100 0x100>;
- };
-
- L2: cache-controller@22000 {
- compatible = "arm,pl310-cache";
- reg = <0x22000 0x1000>;
- cache-unified;
- arm,shared-override;
- prefetch-data = <1>;
- prefetch-instr = <1>;
- cache-level = <2>;
- };
};
pmu {
@@ -301,18 +228,6 @@ genpll: clock-controller@140 {
};
};
- nand_controller: nand-controller@18028000 {
- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
- reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
- reg-names = "nand", "iproc-idm", "iproc-ext";
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- brcm,nand-has-wp;
- };
-
spi@18029200 {
compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x18029200 0x184>,
--
2.35.3
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL 2.0+ / MIT 2023-05-15 15:19 [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT Rafał Miłecki @ 2023-05-15 15:19 ` Rafał Miłecki 2023-05-18 22:59 ` Florian Fainelli 2023-05-20 9:09 ` Hauke Mehrtens 2023-05-18 23:00 ` [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's " Florian Fainelli 2023-05-20 9:09 ` Hauke Mehrtens 2 siblings, 2 replies; 8+ messages in thread From: Rafał Miłecki @ 2023-05-15 15:19 UTC (permalink / raw) To: Florian Fainelli Cc: Hauke Mehrtens, Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree, bcm-kernel-feedback-list, Rafał Miłecki From: Rafał Miłecki <rafal@milecki.pl> Those entries were added by: 1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ numbers for PCIe controller") 2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB interrupts") Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more Northstar code to be based on the same licensing schema. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Florian Fainelli <f.fainelli@gmail.com> --- arch/arm/boot/dts/bcm-ns.dtsi | 73 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 75 --------------------------------- 2 files changed, 73 insertions(+), 75 deletions(-) diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi index 58c30e3a142f..3f8220a7a54d 100644 --- a/arch/arm/boot/dts/bcm-ns.dtsi +++ b/arch/arm/boot/dts/bcm-ns.dtsi @@ -92,6 +92,79 @@ axi@18000000 { #address-cells = <1>; #size-cells = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + + /* Switch Register Access Block */ + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 1 */ + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 2 */ + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 3.0 Controller */ + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 2 */ + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 3 */ + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + + /* NAND Controller */ + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + chipcommon: chipcommon@0 { reg = <0x00000000 0x1000>; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index d6c31ead0398..0f40812eb5a4 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -3,8 +3,6 @@ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs * - * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> - * * Licensed under the GNU/GPL. See COPYING for details. */ @@ -72,79 +70,6 @@ periph_clk: periph_clk { }; axi@18000000 { - #interrupt-cells = <1>; - interrupt-map-mask = <0x000fffff 0xffff>; - interrupt-map = - /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - - /* Switch Register Access Block */ - <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 1 */ - <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - - /* PCIe Controller 2 */ - <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 2.0 Controller */ - <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, - - /* USB 3.0 Controller */ - <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 2 */ - <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - - /* Ethernet Controller 3 */ - <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - - /* NAND Controller */ - <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - pcie2: pcie@14000 { reg = <0x00014000 0x1000>; }; -- 2.35.3 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL 2.0+ / MIT 2023-05-15 15:19 ` [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts " Rafał Miłecki @ 2023-05-18 22:59 ` Florian Fainelli 2023-05-20 9:09 ` Hauke Mehrtens 1 sibling, 0 replies; 8+ messages in thread From: Florian Fainelli @ 2023-05-18 22:59 UTC (permalink / raw) To: bcm-kernel-feedback-list, Rafał Miłecki Cc: Florian Fainelli, Hauke Mehrtens, Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree, Rafał Miłecki [-- Attachment #1: Type: text/plain, Size: 846 bytes --] From: Florian Fainelli <f.fainelli@gmail.com> On Mon, 15 May 2023 17:19:21 +0200, Rafał Miłecki <zajec5@gmail.com> wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > Those entries were added by: > 1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's > bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ > numbers for PCIe controller") > 2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB > interrupts") > > Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more > Northstar code to be based on the same licensing schema. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > Cc: Hauke Mehrtens <hauke@hauke-m.de> > Cc: Florian Fainelli <f.fainelli@gmail.com> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian [-- Attachment #2: S/MIME Cryptographic Signature --] [-- Type: application/pkcs7-signature, Size: 4221 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL 2.0+ / MIT 2023-05-15 15:19 ` [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts " Rafał Miłecki 2023-05-18 22:59 ` Florian Fainelli @ 2023-05-20 9:09 ` Hauke Mehrtens 1 sibling, 0 replies; 8+ messages in thread From: Hauke Mehrtens @ 2023-05-20 9:09 UTC (permalink / raw) To: Rafał Miłecki, Florian Fainelli Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree, bcm-kernel-feedback-list, Rafał Miłecki On 5/15/23 17:19, Rafał Miłecki wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > Those entries were added by: > 1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's > bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ > numbers for PCIe controller") > 2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB > interrupts") > > Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more > Northstar code to be based on the same licensing schema. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > Cc: Hauke Mehrtens <hauke@hauke-m.de> > Cc: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> > --- > arch/arm/boot/dts/bcm-ns.dtsi | 73 ++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/bcm5301x.dtsi | 75 --------------------------------- > 2 files changed, 73 insertions(+), 75 deletions(-) > > diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi > index 58c30e3a142f..3f8220a7a54d 100644 > --- a/arch/arm/boot/dts/bcm-ns.dtsi > +++ b/arch/arm/boot/dts/bcm-ns.dtsi > @@ -92,6 +92,79 @@ axi@18000000 { > #address-cells = <1>; > #size-cells = <1>; > > + #interrupt-cells = <1>; > + interrupt-map-mask = <0x000fffff 0xffff>; > + interrupt-map = > + /* ChipCommon */ > + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > + > + /* Switch Register Access Block */ > + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > + > + /* PCIe Controller 0 */ > + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, > + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, > + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + > + /* PCIe Controller 1 */ > + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, > + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, > + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, > + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, > + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, > + > + /* PCIe Controller 2 */ > + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + > + /* USB 2.0 Controller */ > + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, > + > + /* USB 3.0 Controller */ > + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, > + > + /* Ethernet Controller 0 */ > + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + > + /* Ethernet Controller 1 */ > + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + > + /* Ethernet Controller 2 */ > + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + > + /* Ethernet Controller 3 */ > + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > + > + /* NAND Controller */ > + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, > + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, > + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, > + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, > + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, > + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + > chipcommon: chipcommon@0 { > reg = <0x00000000 0x1000>; > > diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi > index d6c31ead0398..0f40812eb5a4 100644 > --- a/arch/arm/boot/dts/bcm5301x.dtsi > +++ b/arch/arm/boot/dts/bcm5301x.dtsi > @@ -3,8 +3,6 @@ > * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, > * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs > * > - * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> > - * > * Licensed under the GNU/GPL. See COPYING for details. > */ > > @@ -72,79 +70,6 @@ periph_clk: periph_clk { > }; > > axi@18000000 { > - #interrupt-cells = <1>; > - interrupt-map-mask = <0x000fffff 0xffff>; > - interrupt-map = > - /* ChipCommon */ > - <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > - > - /* Switch Register Access Block */ > - <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > - <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > - > - /* PCIe Controller 0 */ > - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, > - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, > - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > - > - /* PCIe Controller 1 */ > - <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, > - <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, > - <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, > - <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > - <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, > - <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, > - > - /* PCIe Controller 2 */ > - <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > - <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > - <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > - <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > - <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > - <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > - > - /* USB 2.0 Controller */ > - <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, > - > - /* USB 3.0 Controller */ > - <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, > - > - /* Ethernet Controller 0 */ > - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > - > - /* Ethernet Controller 1 */ > - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > - > - /* Ethernet Controller 2 */ > - <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > - > - /* Ethernet Controller 3 */ > - <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > - > - /* NAND Controller */ > - <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, > - <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, > - <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, > - <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, > - <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > - <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, > - <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, > - <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > - > pcie2: pcie@14000 { > reg = <0x00014000 0x1000>; > }; ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT 2023-05-15 15:19 [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT Rafał Miłecki 2023-05-15 15:19 ` [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts " Rafał Miłecki @ 2023-05-18 23:00 ` Florian Fainelli 2023-05-19 5:18 ` Rafał Miłecki 2023-05-20 9:09 ` Hauke Mehrtens 2 siblings, 1 reply; 8+ messages in thread From: Florian Fainelli @ 2023-05-18 23:00 UTC (permalink / raw) To: Rafał Miłecki, Florian Fainelli Cc: Hauke Mehrtens, Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree, bcm-kernel-feedback-list, Rafał Miłecki [-- Attachment #1: Type: text/plain, Size: 432 bytes --] On 5/15/23 08:19, Rafał Miłecki wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing. > That syncs more Northstar code to be based on the same licensing schema. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > Cc: Hauke Mehrtens <hauke@hauke-m.de> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian [-- Attachment #2: S/MIME Cryptographic Signature --] [-- Type: application/pkcs7-signature, Size: 4221 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT 2023-05-18 23:00 ` [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's " Florian Fainelli @ 2023-05-19 5:18 ` Rafał Miłecki 2023-05-23 16:30 ` Florian Fainelli 0 siblings, 1 reply; 8+ messages in thread From: Rafał Miłecki @ 2023-05-19 5:18 UTC (permalink / raw) To: Florian Fainelli, Florian Fainelli, Hauke Mehrtens Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree, bcm-kernel-feedback-list, Rafał Miłecki On 19.05.2023 01:00, Florian Fainelli wrote: > On 5/15/23 08:19, Rafał Miłecki wrote: >> From: Rafał Miłecki <rafal@milecki.pl> >> >> Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing. >> That syncs more Northstar code to be based on the same licensing schema. >> >> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> >> Cc: Hauke Mehrtens <hauke@hauke-m.de> >> --- > > Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! Please don't / revert until we get Acked-by from Hauke. I'm sorry I didn't make that clear. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT 2023-05-19 5:18 ` Rafał Miłecki @ 2023-05-23 16:30 ` Florian Fainelli 0 siblings, 0 replies; 8+ messages in thread From: Florian Fainelli @ 2023-05-23 16:30 UTC (permalink / raw) To: Rafał Miłecki, Florian Fainelli, Hauke Mehrtens Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree, bcm-kernel-feedback-list, Rafał Miłecki [-- Attachment #1: Type: text/plain, Size: 736 bytes --] On 5/18/23 22:18, Rafał Miłecki wrote: > On 19.05.2023 01:00, Florian Fainelli wrote: >> On 5/15/23 08:19, Rafał Miłecki wrote: >>> From: Rafał Miłecki <rafal@milecki.pl> >>> >>> Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing. >>> That syncs more Northstar code to be based on the same licensing schema. >>> >>> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> >>> Cc: Hauke Mehrtens <hauke@hauke-m.de> >>> --- >> >> Applied to >> https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! > > Please don't / revert until we get Acked-by from Hauke. > > I'm sorry I didn't make that clear. This is fine, I amended the patches with Hauke's Acked-by tag and pushed them out now. -- Florian [-- Attachment #2: S/MIME Cryptographic Signature --] [-- Type: application/pkcs7-signature, Size: 4221 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT 2023-05-15 15:19 [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT Rafał Miłecki 2023-05-15 15:19 ` [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts " Rafał Miłecki 2023-05-18 23:00 ` [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's " Florian Fainelli @ 2023-05-20 9:09 ` Hauke Mehrtens 2 siblings, 0 replies; 8+ messages in thread From: Hauke Mehrtens @ 2023-05-20 9:09 UTC (permalink / raw) To: Rafał Miłecki, Florian Fainelli Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel, devicetree, bcm-kernel-feedback-list, Rafał Miłecki On 5/15/23 17:19, Rafał Miłecki wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing. > That syncs more Northstar code to be based on the same licensing schema. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > Cc: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> > --- > arch/arm/boot/dts/bcm-ns.dtsi | 90 +++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/bcm5301x.dtsi | 85 ------------------------------- > 2 files changed, 90 insertions(+), 85 deletions(-) > > diff --git a/arch/arm/boot/dts/bcm-ns.dtsi b/arch/arm/boot/dts/bcm-ns.dtsi > index cc977bbc142b..58c30e3a142f 100644 > --- a/arch/arm/boot/dts/bcm-ns.dtsi > +++ b/arch/arm/boot/dts/bcm-ns.dtsi > @@ -1,4 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0-or-later OR MIT > +/* > + * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> > + */ > > #include <dt-bindings/clock/bcm-nsp.h> > #include <dt-bindings/gpio/gpio.h> > @@ -7,6 +10,81 @@ > #include <dt-bindings/interrupt-controller/arm-gic.h> > > / { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + chipcommon-a-bus@18000000 { > + compatible = "simple-bus"; > + ranges = <0x00000000 0x18000000 0x00001000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@300 { > + compatible = "ns16550"; > + reg = <0x0300 0x100>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&iprocslow>; > + status = "disabled"; > + }; > + > + uart1: serial@400 { > + compatible = "ns16550"; > + reg = <0x0400 0x100>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&iprocslow>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinmux_uart1>; > + status = "disabled"; > + }; > + }; > + > + mpcore-bus@19000000 { > + compatible = "simple-bus"; > + ranges = <0x00000000 0x19000000 0x00023000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + scu@20000 { > + compatible = "arm,cortex-a9-scu"; > + reg = <0x20000 0x100>; > + }; > + > + timer@20200 { > + compatible = "arm,cortex-a9-global-timer"; > + reg = <0x20200 0x100>; > + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; > + clocks = <&periph_clk>; > + }; > + > + timer@20600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x20600 0x20>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_EDGE_RISING)>; > + clocks = <&periph_clk>; > + }; > + > + gic: interrupt-controller@21000 { > + compatible = "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x21000 0x1000>, > + <0x20100 0x100>; > + }; > + > + L2: cache-controller@22000 { > + compatible = "arm,pl310-cache"; > + reg = <0x22000 0x1000>; > + cache-unified; > + arm,shared-override; > + prefetch-data = <1>; > + prefetch-instr = <1>; > + cache-level = <2>; > + }; > + }; > + > axi@18000000 { > compatible = "brcm,bus-axi"; > reg = <0x18000000 0x1000>; > @@ -216,6 +294,18 @@ thermal: thermal@2c0 { > }; > }; > > + nand_controller: nand-controller@18028000 { > + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; > + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; > + reg-names = "nand", "iproc-idm", "iproc-ext"; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + brcm,nand-has-wp; > + }; > + > thermal-zones { > cpu_thermal: cpu-thermal { > polling-delay-passive = <0>; > diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi > index bc36edc24510..d6c31ead0398 100644 > --- a/arch/arm/boot/dts/bcm5301x.dtsi > +++ b/arch/arm/boot/dts/bcm5301x.dtsi > @@ -11,41 +11,7 @@ > #include "bcm-ns.dtsi" > > / { > - #address-cells = <1>; > - #size-cells = <1>; > - interrupt-parent = <&gic>; > - > - chipcommon-a-bus@18000000 { > - compatible = "simple-bus"; > - ranges = <0x00000000 0x18000000 0x00001000>; > - #address-cells = <1>; > - #size-cells = <1>; > - > - uart0: serial@300 { > - compatible = "ns16550"; > - reg = <0x0300 0x100>; > - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&iprocslow>; > - status = "disabled"; > - }; > - > - uart1: serial@400 { > - compatible = "ns16550"; > - reg = <0x0400 0x100>; > - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&iprocslow>; > - pinctrl-names = "default"; > - pinctrl-0 = <&pinmux_uart1>; > - status = "disabled"; > - }; > - }; > - > mpcore-bus@19000000 { > - compatible = "simple-bus"; > - ranges = <0x00000000 0x19000000 0x00023000>; > - #address-cells = <1>; > - #size-cells = <1>; > - > a9pll: arm_clk@0 { > #clock-cells = <0>; > compatible = "brcm,nsp-armpll"; > @@ -53,26 +19,6 @@ a9pll: arm_clk@0 { > reg = <0x00000 0x1000>; > }; > > - scu@20000 { > - compatible = "arm,cortex-a9-scu"; > - reg = <0x20000 0x100>; > - }; > - > - timer@20200 { > - compatible = "arm,cortex-a9-global-timer"; > - reg = <0x20200 0x100>; > - interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; > - clocks = <&periph_clk>; > - }; > - > - timer@20600 { > - compatible = "arm,cortex-a9-twd-timer"; > - reg = <0x20600 0x20>; > - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > - IRQ_TYPE_EDGE_RISING)>; > - clocks = <&periph_clk>; > - }; > - > watchdog@20620 { > compatible = "arm,cortex-a9-twd-wdt"; > reg = <0x20620 0x20>; > @@ -80,25 +26,6 @@ watchdog@20620 { > IRQ_TYPE_EDGE_RISING)>; > clocks = <&periph_clk>; > }; > - > - gic: interrupt-controller@21000 { > - compatible = "arm,cortex-a9-gic"; > - #interrupt-cells = <3>; > - #address-cells = <0>; > - interrupt-controller; > - reg = <0x21000 0x1000>, > - <0x20100 0x100>; > - }; > - > - L2: cache-controller@22000 { > - compatible = "arm,pl310-cache"; > - reg = <0x22000 0x1000>; > - cache-unified; > - arm,shared-override; > - prefetch-data = <1>; > - prefetch-instr = <1>; > - cache-level = <2>; > - }; > }; > > pmu { > @@ -301,18 +228,6 @@ genpll: clock-controller@140 { > }; > }; > > - nand_controller: nand-controller@18028000 { > - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; > - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; > - reg-names = "nand", "iproc-idm", "iproc-ext"; > - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; > - > - #address-cells = <1>; > - #size-cells = <0>; > - > - brcm,nand-has-wp; > - }; > - > spi@18029200 { > compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; > reg = <0x18029200 0x184>, ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-05-23 16:30 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-05-15 15:19 [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT Rafał Miłecki 2023-05-15 15:19 ` [PATCH 2/2] ARM: dts: BCM5301X: Relicense AXI interrupts " Rafał Miłecki 2023-05-18 22:59 ` Florian Fainelli 2023-05-20 9:09 ` Hauke Mehrtens 2023-05-18 23:00 ` [PATCH 1/2] ARM: dts: BCM5301X: Relicense Hauke's " Florian Fainelli 2023-05-19 5:18 ` Rafał Miłecki 2023-05-23 16:30 ` Florian Fainelli 2023-05-20 9:09 ` Hauke Mehrtens
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