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[217.164.166.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4851acf9c31sm13254295e9.12.2026.03.04.09.57.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 09:58:01 -0800 (PST) Date: Wed, 4 Mar 2026 21:57:56 +0400 From: "Anton D. Stavinskii" To: Inochi Amaoto Cc: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v4 6/6] riscv: dts: sophgo: dts nodes for i2s tdm modules Message-ID: Mail-Followup-To: Inochi Amaoto , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org References: <20260120-cv1800b-i2s-driver-v4-0-6ef787dc6426@gmail.com> <20260120-cv1800b-i2s-driver-v4-6-6ef787dc6426@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Feb 26, 2026 at 06:32:27AM +0400, Inochi Amaoto wrote: > > +#define DMA_CPU_A53 0 > > +#define DMA_CPU_C906_0 1 > > +#define DMA_CPU_C906_1 2 > > + > > +#endif // _SOPHGO_CV18XX_DMAMUX > > diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > > index 06b0ce5a2db7..ebe5e8113939 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi > > @@ -8,6 +8,7 @@ > > #include > > #include > > #include "cv18xx-reset.h" > > +#include "cv180x-dmamux.h" > > > > / { > > #address-cells = <1>; > > @@ -448,6 +449,60 @@ usb: usb@4340000 { > > status = "disabled"; > > }; > > > > + i2s0: i2s@4100000 { > > + compatible = "sophgo,cv1800b-i2s"; > > + reg = <0x04100000 0x1000>; > > + clocks = <&clk CLK_APB_I2S0>, <&clk CLK_SDMA_AUD0>; > > + clock-names = "i2s", "mclk"; > > + dmas = <&dmamux DMA_I2S0_RX 1>, <&dmamux DMA_I2S0_TX 1>; > > + dma-names = "rx", "tx"; > > + status = "disabled"; > > + }; > > This magic number 1 is bind to the RISC-V cores, I think we should add a > macro DMA_CPU_ID into CPU file to route the CPU id to real cores. > Or, just let the borad dts configure which dma is enabled. Hi, Inochi. Sorry for delay, I've missed the messages somehow. I'm not sure what is the best option TBH. If the problem is with the magic number, there are constants for this in your file: #define DMA_CPU_A53 0 #define DMA_CPU_C906_0 1 #define DMA_CPU_C906_1 2 So I could use them. If the problem with hardcoding the CPU - it is little bit more tricky. Ths commit is in the riscv branch so we could not use ID 0 at all. Unless you want it to be more generic. >From my understanding we could not boot from CPUID 2. (may be i'm wrong here) If it is correct, it means the whole setup will only work on CPU 1. In any case I will follow your suggestion. I agree, leaving this with the magic number is not good. Second question: Do you want me to resubmit this change as A separate patch as the rest of this patch was applied? > > Regards, > Inochi >