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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be1281ff70sm9670998eec.14.2026.03.05.00.34.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 00:34:20 -0800 (PST) Date: Thu, 5 Mar 2026 00:34:18 -0800 From: Qiang Yu To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support Message-ID: References: <20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com> <20260304-glymur_gen5x8_phy-v1-2-849e9a72e125@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-GUID: 1pfn0-3X4UfcJLEwkzRxaPHXAQpT4CvZ X-Authority-Analysis: v=2.4 cv=eqTSD4pX c=1 sm=1 tr=0 ts=69a9400d cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=-udo5FGDkBk8TPX1unEA:9 a=CjuIK1q_8ugA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: 1pfn0-3X4UfcJLEwkzRxaPHXAQpT4CvZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA2NyBTYWx0ZWRfX/3Z/gwNXzwyB 3/zCIADw4VVSz6lRIIy4rbn0o033/botRSzPsiAnL/71ZH7Tq4SdvLmq3w8/IXurR354yvNAwW6 d9AoUzJiS0UtgnIxueWdkp1QpAKJVuS+66HNWpLKMXvUlstVBg7qQWkIeybmq6HDDKhkSudAZlz bl7e0by6UhgOm7V2OvTvaCqRfME6cKqVwP4Yz3D+znzvq0wmYVMBNDhh2xZWUohuLOCOFz/0SaX dg5Gx6kwqzB+VdW41h4E1sHLJ2DhHm6BOaG5dQbysoR293ThL6/ygDdkdFqU9IyTTZ7VqIzsxs4 GCE5fvnf4YBbQ5taTuGM6iRAn245unxDsCIy+cXExrXJ40jaMhxOM6SymZMOkB1hYLcxN2qmL6k lFu03yhHsWtDt6ZrKUiDtEgDxnmH2AGa8D0Uspzm822OZ7vX8vDmBn1yGt7sczutw4xz0QqeZsg Z+ormuJc+uCyF3VT6OQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050067 On Thu, Mar 05, 2026 at 01:58:34AM +0200, Dmitry Baryshkov wrote: > On Wed, Mar 04, 2026 at 12:21:56AM -0800, Qiang Yu wrote: > > The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in > > a bifurcated configuration. Each PHY has its own power domain (phy_gdsc) > > that must be powered on before initialization per hardware requirements. > > > > Current PHY power management assumes a single power domain per PHY, > > preventing proper setup for this dual-PHY scenario. Add support for > > multiple power domains by using devm_pm_domain_attach_list() to attach > > power domains manually, while maintaining compatibility with single > > power domain PHYs. > > > > Enable runtime PM to allow power domain control when the PCIe driver > > calls phy_power_on/phy_power_off: > > > > - Single power domain: QMP PHY platform device directly attaches to > > power domain and controls it during runtime resume/suspend > > - Multiple power domains: devm_pm_domain_attach_list() creates virtual > > devices as power domain suppliers, linked to the QMP PHY platform > > device as consumer > > > > This ensures power domains are properly attached and turned on/off > > for both single and multiple power domain configurations. > > > > Signed-off-by: Qiang Yu > > --- > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > index fed2fc9bb31108d51f88d34f3379c7744681f485..7369c291be51aa1ad7a330459dcb857f5a1988f6 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > @@ -17,6 +17,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -3334,6 +3335,8 @@ struct qmp_pcie { > > > > struct clk_fixed_rate pipe_clk_fixed; > > struct clk_fixed_rate aux_clk_fixed; > > + > > + struct dev_pm_domain_list *pd_list; > > }; > > > > static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val) > > @@ -5348,6 +5351,16 @@ static int qmp_pcie_probe(struct platform_device *pdev) > > WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); > > WARN_ON_ONCE(!qmp->cfg->phy_status); > > > > + ret = devm_pm_domain_attach_list(dev, NULL, &qmp->pd_list); > > + if (ret < 0 && ret != -EEXIST) { > > + dev_err(dev, "Failed to attach power domain\n"); > > + return ret; > > + } > > + > > + ret = devm_pm_runtime_enable(dev); > > + if (ret) > > + return ret; > > These two should be separate commits. IIUC, dev_pm_domain_attach_list doesn't turn on power domian during attaching, which is different to dev_pm_domain_attach called in platform_probe for single power domain. - Qiang Yu > > > + > > ret = qmp_pcie_clk_init(qmp); > > if (ret) > > return ret; > > > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry