* [PATCH RFT] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names
@ 2022-07-11 8:26 Krzysztof Kozlowski
2022-07-11 14:57 ` Doug Anderson
0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-11 8:26 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Martin Botka, linux-arm-msm, devicetree,
linux-kernel
Cc: Douglas Anderson, Bhupesh Sharma, Krzysztof Kozlowski
SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
registers is cqhci, not core.
Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Not tested on hardware, but no practical impact is expected, because
supports-cqe is not defined.
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 77bff81af433..7664ef7e4da9 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 {
sdhc_1: mmc@4744000 {
compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
- reg-names = "hc", "core";
+ reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH RFT] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names
2022-07-11 8:26 [PATCH RFT] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names Krzysztof Kozlowski
@ 2022-07-11 14:57 ` Doug Anderson
2022-07-12 6:53 ` Krzysztof Kozlowski
0 siblings, 1 reply; 3+ messages in thread
From: Doug Anderson @ 2022-07-11 14:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Martin Botka, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
Bhupesh Sharma
Hi,
On Mon, Jul 11, 2022 at 1:26 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
> registers is cqhci, not core.
>
> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> Not tested on hardware, but no practical impact is expected, because
> supports-cqe is not defined.
Maybe the schema should enforce this? If "cqhci" is in reg-names then
you must have supports-cqe and vice versa?
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 77bff81af433..7664ef7e4da9 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 {
> sdhc_1: mmc@4744000 {
> compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
> reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
> - reg-names = "hc", "core";
> + reg-names = "hc", "cqhci";
Another possible fix would be to just delete the second register
range. Then it could be added back in once "supports-cqe" was added.
-Doug
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH RFT] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names
2022-07-11 14:57 ` Doug Anderson
@ 2022-07-12 6:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 3+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-12 6:53 UTC (permalink / raw)
To: Doug Anderson
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Martin Botka, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
Bhupesh Sharma
On 11/07/2022 16:57, Doug Anderson wrote:
> Hi,
>
> On Mon, Jul 11, 2022 at 1:26 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
>> registers is cqhci, not core.
>>
>> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> ---
>>
>> Not tested on hardware, but no practical impact is expected, because
>> supports-cqe is not defined.
>
> Maybe the schema should enforce this? If "cqhci" is in reg-names then
> you must have supports-cqe and vice versa?
I have mixed feelings about this. First, I don't know why support-cqe
was not enabled on all devices but only in some DTS (this does not look
like a property of a board but SoC). Second, cqhci address space might
be present in all devices, even if they do not use CQE.
>
>
>> ---
>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>> index 77bff81af433..7664ef7e4da9 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>> @@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 {
>> sdhc_1: mmc@4744000 {
>> compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
>> reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
>> - reg-names = "hc", "core";
>> + reg-names = "hc", "cqhci";
>
> Another possible fix would be to just delete the second register
> range. Then it could be added back in once "supports-cqe" was added.
True, but I assume that second address range is there for complete
hardware description.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-07-11 8:26 [PATCH RFT] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names Krzysztof Kozlowski
2022-07-11 14:57 ` Doug Anderson
2022-07-12 6:53 ` Krzysztof Kozlowski
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