* [PATCH 0/5] PCI: tegra: Add Tegra264 support
@ 2026-03-19 16:01 Thierry Reding
2026-03-19 16:01 ` [PATCH 1/5] soc/tegra: Update BPMP ABI header Thierry Reding
` (4 more replies)
0 siblings, 5 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-19 16:01 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Hi,
this series adds support for the PCIe controllers found on the Tegra264
SoC. There are six instances, one of which is for internal purposes only
and the other five are general purpose.
The first two patches in the series add the BPMP support needed to power
up/down the PCI link. Patch 3 contains the device tree bindings for the
PCIe controller and patch 4 adds the driver. Finally, patch 5 adds DT
nodes for the controllers found on the Tegra264 SoC.
Regarding merging these patches, I think ideally I'd want to pick up the
PCI driver patch into the Tegra tree because there is a build dependency
on patches 1 and 2. Furthermore, patch 1 depends on another patch that's
already in the Tegra tree, and there will be conflicts if it is merged
in another tree. Alternatively I can provide a stable branch with
patches 1 and 2 for the PCI maintainers to pull in.
Let me know how you'd like to handle this.
Thanks,
Thierry
Thierry Reding (5):
soc/tegra: Update BPMP ABI header
firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function
dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
PCI: tegra: Add Tegra264 support
arm64: tegra: Add PCI controllers on Tegra264
.../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 248 +-
drivers/firmware/tegra/bpmp.c | 34 +
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-tegra264.c | 506 ++
include/soc/tegra/bpmp-abi.h | 4565 +++++++++++++----
include/soc/tegra/bpmp.h | 1 +
8 files changed, 4534 insertions(+), 921 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
create mode 100644 drivers/pci/controller/pcie-tegra264.c
--
2.52.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 1/5] soc/tegra: Update BPMP ABI header
2026-03-19 16:01 [PATCH 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
@ 2026-03-19 16:01 ` Thierry Reding
2026-03-19 16:15 ` Krzysztof Kozlowski
2026-03-19 16:01 ` [PATCH 2/5] firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function Thierry Reding
` (3 subsequent siblings)
4 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2026-03-19 16:01 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
This update primarily adds various new commands and MRQs for Tegra264,
but also contains a few new annotations and fixes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
include/soc/tegra/bpmp-abi.h | 4565 +++++++++++++++++++++++++++-------
1 file changed, 3671 insertions(+), 894 deletions(-)
diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
index 39bb3f87e28d..6cf6442395f1 100644
--- a/include/soc/tegra/bpmp-abi.h
+++ b/include/soc/tegra/bpmp-abi.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
- * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2014-2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef ABI_BPMP_ABI_H
@@ -74,6 +74,7 @@
/**
* @ingroup MRQ_Format
+ *
* Request an answer from the peer.
* This should be set in mrq_request::flags for all requests targetted
* at BPMP. For requests originating in BPMP, this flag is optional except
@@ -85,6 +86,7 @@
/**
* @ingroup MRQ_Format
+ *
* Ring the sender's doorbell when responding. This should be set unless
* the sender wants to poll the underlying communications layer directly.
*
@@ -94,7 +96,9 @@
/**
* @ingroup MRQ_Format
- * CRC present
+ *
+ * This is set in mrq_request::flags for requests that have CRC present and
+ * correspondingly in mrq_response::flags for responses that have CRC present.
*/
#define BPMP_MAIL_CRC_PRESENT (1U << 2U)
@@ -127,91 +131,319 @@ struct mrq_request {
* crc16, xid and length fields are present when set.
* Some platform configurations, especially when targeted to applications requiring
* functional safety, mandate this option being set or otherwise will respond with
- * -BPMP_EBADMSG and ignore the request.
+ * -#BPMP_EBADMSG and ignore the request.
*
* **xid** is a transaction ID.
*
* Only used when #BPMP_MAIL_CRC_PRESENT is set.
*
* **payload_length** of the message expressed in bytes without the size of this header.
- * See table below for minimum accepted payload lengths for each MRQ.
- * Note: For DMCE communication, this field expresses the length as a multiple of 4 bytes
- * rather than bytes.
+ * See tables below for minimum accepted payload lengths for each MRQ.
*
* Only used when #BPMP_MAIL_CRC_PRESENT is set.
*
- * | MRQ | CMD | minimum payload length
- * | -------------------- | ------------------------------------ | ------------------------------------------ |
- * | MRQ_PING | | 4 |
- * | MRQ_THREADED_PING | | 4 |
- * | MRQ_RESET | any | 8 |
- * | MRQ_I2C | | 12 + cmd_i2c_xfer_request.data_size |
- * | MRQ_CLK | CMD_CLK_GET_RATE | 4 |
- * | MRQ_CLK | CMD_CLK_SET_RATE | 16 |
- * | MRQ_CLK | CMD_CLK_ROUND_RATE | 16 |
- * | MRQ_CLK | CMD_CLK_GET_PARENT | 4 |
- * | MRQ_CLK | CMD_CLK_SET_PARENT | 8 |
- * | MRQ_CLK | CMD_CLK_ENABLE | 4 |
- * | MRQ_CLK | CMD_CLK_DISABLE | 4 |
- * | MRQ_CLK | CMD_CLK_IS_ENABLED | 4 |
- * | MRQ_CLK | CMD_CLK_GET_ALL_INFO | 4 |
- * | MRQ_CLK | CMD_CLK_GET_MAX_CLK_ID | 4 |
- * | MRQ_CLK | CMD_CLK_GET_FMAX_AT_VMIN | 4 |
- * | MRQ_QUERY_ABI | | 4 |
- * | MRQ_PG | CMD_PG_QUERY_ABI | 12 |
- * | MRQ_PG | CMD_PG_SET_STATE | 12 |
- * | MRQ_PG | CMD_PG_GET_STATE | 8 |
- * | MRQ_PG | CMD_PG_GET_NAME | 8 |
- * | MRQ_PG | CMD_PG_GET_MAX_ID | 8 |
- * | MRQ_THERMAL | CMD_THERMAL_QUERY_ABI | 8 |
- * | MRQ_THERMAL | CMD_THERMAL_GET_TEMP | 8 |
- * | MRQ_THERMAL | CMD_THERMAL_SET_TRIP | 20 |
- * | MRQ_THERMAL | CMD_THERMAL_GET_NUM_ZONES | 4 |
- * | MRQ_THERMAL | CMD_THERMAL_GET_THERMTRIP | 8 |
- * | MRQ_CPU_VHINT | | 8 |
- * | MRQ_ABI_RATCHET | | 2 |
- * | MRQ_EMC_DVFS_LATENCY | | 8 |
- * | MRQ_EMC_DVFS_EMCHUB | | 8 |
- * | MRQ_EMC_DISP_RFL | | 4 |
- * | MRQ_BWMGR | CMD_BWMGR_QUERY_ABI | 8 |
- * | MRQ_BWMGR | CMD_BWMGR_CALC_RATE | 8 + 8 * bwmgr_rate_req.num_iso_clients |
- * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_QUERY_ABI | 8 |
- * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_CALCULATE_LA | 16 |
- * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_SET_LA | 16 |
- * | MRQ_ISO_CLIENT | CMD_ISO_CLIENT_GET_MAX_BW | 8 |
- * | MRQ_CPU_NDIV_LIMITS | | 4 |
- * | MRQ_CPU_AUTO_CC3 | | 4 |
- * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 |
- * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_READ | 5 |
- * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len |
- * | MRQ_RINGBUF_CONSOLE | CMD_RINGBUF_CONSOLE_GET_FIFO | 4 |
- * | MRQ_STRAP | STRAP_SET | 12 |
- * | MRQ_UPHY | CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 |
- * | MRQ_UPHY | CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 |
- * | MRQ_UPHY | CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 |
- * | MRQ_UPHY | CMD_UPHY_PCIE_CONTROLLER_STATE | 6 |
- * | MRQ_UPHY | CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 |
- * | MRQ_FMON | CMD_FMON_GEAR_CLAMP | 16 |
- * | MRQ_FMON | CMD_FMON_GEAR_FREE | 4 |
- * | MRQ_FMON | CMD_FMON_GEAR_GET | 4 |
- * | MRQ_FMON | CMD_FMON_FAULT_STS_GET | 8 |
- * | MRQ_EC | CMD_EC_STATUS_EX_GET | 12 |
- * | MRQ_QUERY_FW_TAG | | 0 |
- * | MRQ_DEBUG | CMD_DEBUG_OPEN_RO | 4 + length of cmd_debug_fopen_request.name |
- * | MRQ_DEBUG | CMD_DEBUG_OPEN_WO | 4 + length of cmd_debug_fopen_request.name |
- * | MRQ_DEBUG | CMD_DEBUG_READ | 8 |
- * | MRQ_DEBUG | CMD_DEBUG_WRITE | 12 + cmd_debug_fwrite_request.datalen |
- * | MRQ_DEBUG | CMD_DEBUG_CLOSE | 8 |
- * | MRQ_TELEMETRY | | 8 |
- * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_QUERY_ABI | 8 |
- * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_SET | 20 |
- * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_GET | 16 |
- * | MRQ_PWR_LIMIT | CMD_PWR_LIMIT_CURR_CAP | 8 |
- * | MRQ_GEARS | | 0 |
- * | MRQ_BWMGR_INT | CMD_BWMGR_INT_QUERY_ABI | 8 |
- * | MRQ_BWMGR_INT | CMD_BWMGR_INT_CALC_AND_SET | 16 |
- * | MRQ_BWMGR_INT | CMD_BWMGR_INT_CAP_SET | 8 |
- * | MRQ_OC_STATUS | | 0 |
+ * | MRQ | Sub-command | Minimum payload length
+ * | --------------------- | ------------------------------------ | ------------------------------------------------------- |
+ * | #MRQ_PING | - | 4 |
+ * | #MRQ_THREADED_PING | - | 4 |
+ * | #MRQ_RESET | any | 8 |
+ * | #MRQ_I2C | - | 12 + cmd_i2c_xfer_request.data_size |
+ * | #MRQ_CLK | #CMD_CLK_GET_RATE | 4 |
+ * | #MRQ_CLK | #CMD_CLK_SET_RATE | 16 |
+ * | #MRQ_CLK | #CMD_CLK_ROUND_RATE | 16 |
+ * | #MRQ_CLK | #CMD_CLK_GET_PARENT | 4 |
+ * | #MRQ_CLK | #CMD_CLK_SET_PARENT | 8 |
+ * | #MRQ_CLK | #CMD_CLK_ENABLE | 4 |
+ * | #MRQ_CLK | #CMD_CLK_DISABLE | 4 |
+ * | #MRQ_CLK | #CMD_CLK_IS_ENABLED | 4 |
+ * | #MRQ_CLK | #CMD_CLK_GET_ALL_INFO | 4 |
+ * | #MRQ_CLK | #CMD_CLK_GET_MAX_CLK_ID | 4 |
+ * | #MRQ_CLK | #CMD_CLK_GET_FMAX_AT_VMIN | 4 |
+ * | #MRQ_QUERY_ABI | - | 4 |
+ * | #MRQ_PG | #CMD_PG_QUERY_ABI | 12 |
+ * | #MRQ_PG | #CMD_PG_SET_STATE | 12 |
+ * | #MRQ_PG | #CMD_PG_GET_STATE | 8 |
+ * | #MRQ_PG | #CMD_PG_GET_NAME | 8 |
+ * | #MRQ_PG | #CMD_PG_GET_MAX_ID | 8 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_QUERY_ABI | 8 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_GET_TEMP | 8 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_GET_NUM_ZONES | 4 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_GET_THERMTRIP | 8 |
+ * | #MRQ_ABI_RATCHET | - | 2 |
+ * | #MRQ_EMC_DVFS_LATENCY | - | 8 |
+ * | #MRQ_QUERY_FW_TAG | - | 0 |
+ * | #MRQ_DEBUG | #CMD_DEBUG_OPEN_RO | 4 + length of cmd_debug_fopen_request.name |
+ * | #MRQ_DEBUG | #CMD_DEBUG_OPEN_WO | 4 + length of cmd_debug_fopen_request.name |
+ * | #MRQ_DEBUG | #CMD_DEBUG_READ | 8 |
+ * | #MRQ_DEBUG | #CMD_DEBUG_WRITE | 12 + cmd_debug_fwrite_request.datalen |
+ * | #MRQ_DEBUG | #CMD_DEBUG_CLOSE | 8 |
+ *
+ * @cond (bpmp_t186)
+ * The following additional MRQ is supported on T186 -platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | --------------------- | ------------------------------------- | ------------------------------------- |
+ * | #MRQ_CPU_VHINT | - | 8 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_SET_TRIP | 20 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_READ | 5 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_GET_FIFO | 4 |
+ * @endcond
+ *
+ * @cond (bpmp_t194)
+ * The following additional MRQs are supported on T194 -platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | --------------------- | ------------------------------------- | ------------------------------------- |
+ * | #MRQ_CPU_NDIV_LIMITS | - | 4 |
+ * | #MRQ_STRAP | #STRAP_SET | 12 |
+ * | #MRQ_CPU_AUTO_CC3 | - | 4 |
+ * | #MRQ_EC | #CMD_EC_STATUS_EX_GET | 12 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_CLAMP | 16 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_FREE | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_GET | 4 |
+ * | #MRQ_FMON | #CMD_FMON_FAULT_STS_GET | 8 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_SET_TRIP | 20 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_READ | 5 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_GET_FIFO | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_CONTROLLER_STATE | 6 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 |
+ * @endcond
+ *
+ * @cond (bpmp_safe && bpmp_t234)
+ * The following additional MRQ is supported on functional-safety
+ * builds for the T234 platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | --------------------- | ------------------------------------- | ------------------------------------- |
+ * | #MRQ_CPU_NDIV_LIMITS | - | 4 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_READ | 5 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_GET_FIFO | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_CONTROLLER_STATE | 6 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_CLAMP | 16 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_FREE | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_GET | 4 |
+ * | #MRQ_FMON | #CMD_FMON_FAULT_STS_GET | 8 |
+ * | #MRQ_EMC_DVFS_EMCHUB | - | 8 |
+ * | #MRQ_EMC_DISP_RFL | - | 4 |
+ *
+ * @endcond
+ *
+ * @cond (!bpmp_safe && bpmp_t234)
+ *
+ * The following additional MRQs are supported on non-functional-safety
+ * builds for the T234 and T238 -platforms:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | --------------------- | ------------------------------------- | --------------------------------------------------- |
+ * | #MRQ_CPU_NDIV_LIMITS | - | 4 |
+ * | #MRQ_STRAP | #STRAP_SET | 12 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_SET_TRIP | 20 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_READ | 5 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_GET_FIFO | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_CONTROLLER_STATE | 6 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_CLAMP | 16 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_FREE | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_GET | 4 |
+ * | #MRQ_FMON | #CMD_FMON_FAULT_STS_GET | 8 |
+ * | #MRQ_EMC_DVFS_EMCHUB | - | 8 |
+ * | #MRQ_EMC_DISP_RFL | - | 4 |
+ * | #MRQ_BWMGR | #CMD_BWMGR_QUERY_ABI | 8 |
+ * | #MRQ_BWMGR | #CMD_BWMGR_CALC_RATE | 8 + 8 * cmd_bwmgr_calc_rate_request.num_iso_clients |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_QUERY_ABI | 8 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_CALCULATE_LA | 16 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_SET_LA | 16 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_GET_MAX_BW | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_QUERY_ABI | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_CALC_AND_SET | 16 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_CAP_SET | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_GET_LAST_REQUEST | 9 |
+ * | #MRQ_OC_STATUS | - | 0 |
+ * @endcond
+ *
+ * @cond bpmp_t238
+ * The following additional MRQs are supported on T238 platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | --------------------- | ------------------------------------- | --------------------------------------------------- |
+ * | #MRQ_CPU_NDIV_LIMITS | - | 4 |
+ * | #MRQ_STRAP | #STRAP_SET | 12 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_SET_TRIP | 20 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_QUERY_ABI | 8 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_READ | 5 |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_WRITE | 5 + cmd_ringbuf_console_write_req.len |
+ * | #MRQ_RINGBUF_CONSOLE | #CMD_RINGBUF_CONSOLE_GET_FIFO | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_CONTROLLER_STATE | 6 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_CLAMP | 16 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_FREE | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_GET | 4 |
+ * | #MRQ_FMON | #CMD_FMON_FAULT_STS_GET | 8 |
+ * | #MRQ_EMC_DVFS_EMCHUB | - | 8 |
+ * | #MRQ_EMC_DISP_RFL | - | 4 |
+ * | #MRQ_BWMGR | #CMD_BWMGR_QUERY_ABI | 8 |
+ * | #MRQ_BWMGR | #CMD_BWMGR_CALC_RATE | 8 + 8 * cmd_bwmgr_calc_rate_request.num_iso_clients |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_QUERY_ABI | 8 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_CALCULATE_LA | 16 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_SET_LA | 16 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_GET_MAX_BW | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_QUERY_ABI | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_CALC_AND_SET | 16 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_CAP_SET | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_GET_LAST_REQUEST | 9 |
+ * | #MRQ_OC_STATUS | - | 0 |
+ * | #MRQ_THROTTLE | #CMD_THROTTLE_SET_OC_CONFIG | 5 |
+ * @endcond
+ *
+ * @cond (bpmp_th500)
+ * The following additional MRQs are supported on TH500 -platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | -------------------- | ------------------------------------- | ---------------------- |
+ * | #MRQ_CPU_NDIV_LIMITS | - | 4 |
+ * | #MRQ_THERMAL | #CMD_THERMAL_SET_TRIP | 20 |
+ * | #MRQ_STRAP | #STRAP_SET | 12 |
+ * | #MRQ_SHUTDOWN | - | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | 24 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_LANE_MARGIN_STATUS | 4 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT | 5 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_CONTROLLER_STATE | 6 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF | 5 |
+ * | #MRQ_UPHY | #CMD_UPHY_PCIE_CONFIG_VDM | 3 |
+ * | #MRQ_TELEMETRY | - | 8 |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_QUERY_ABI | 8 |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_SET | 20 |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_GET | 16 |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_CURR_CAP | 8 |
+ * | #MRQ_GEARS | - | 0 |
+ * | #MRQ_C2C | #CMD_C2C_QUERY_ABI | 8 |
+ * | #MRQ_C2C | #CMD_C2C_START_INITIALIZATION | 5 |
+ * | #MRQ_C2C | #CMD_C2C_GET_STATUS | 4 |
+ * | #MRQ_C2C | #CMD_C2C_HOTRESET_PREP | 5 |
+ * | #MRQ_C2C | #CMD_C2C_START_HOTRESET | 5 |
+ * | #MRQ_THROTTLE | #CMD_THROTTLE_QUERY_ABI | 4 |
+ * | #MRQ_THROTTLE | #CMD_THROTTLE_GET_CHIPTHROT_STATUS | 4 |
+ * | #MRQ_PWRMODEL | #CMD_PWRMODEL_QUERY_ABI | 8 |
+ * | #MRQ_PWRMODEL | #CMD_PWRMODEL_PWR_GET | 16 |
+ * | #MRQ_PWR_CNTRL | #CMD_PWR_CNTRL_QUERY_ABI | 8 |
+ * | #MRQ_PWR_CNTRL | #CMD_PWR_CNTRL_BYPASS_SET | 12 |
+ * | #MRQ_PWR_CNTRL | #CMD_PWR_CNTRL_BYPASS_GET | 8 |
+ * @endcond
+ *
+ * @cond (bpmp_tb500)
+ * The following additional MRQs are supported on TB500 -platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | -------------------- | ---------------------------------------- | ---------------------- |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_QUERY_ABI | 8 |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_SET | 20 |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_GET | 16 |
+ * | #MRQ_PWR_LIMIT | #CMD_PWR_LIMIT_CURR_CAP | 8 |
+ * | #MRQ_TELEMETRY_EX | #CMD_TELEMETRY_EX_QUERY_ABI | 8 |
+ * | #MRQ_TELEMETRY_EX | #CMD_TELEMETRY_EX_BASE_SZ_GET | 12 |
+ * | #MRQ_THROTTLE | #CMD_THROTTLE_GET_CHIPTHROT_STATUS | 4 |
+ * | #MRQ_C2C | #CMD_C2C_QUERY_ABI | 8 |
+ * | #MRQ_C2C | #CMD_C2C_START_INITIALIZATION | 5 |
+ * | #MRQ_C2C | #CMD_C2C_GET_STATUS | 4 |
+ * | #MRQ_C2C | #CMD_C2C_HOTRESET_PREP | 5 |
+ * | #MRQ_C2C | #CMD_C2C_START_HOTRESET | 5 |
+ * | MRQ_HWPM | CMD_HWPM_QUERY_ABI | 4 |
+ * | MRQ_HWPM | CMD_HWPM_IPMU_SET_TRIGGERS | 120 |
+ * | MRQ_HWPM | CMD_HWPM_IPMU_SET_PAYLOADS_SHIFTS | 120 |
+ * | MRQ_HWPM | CMD_HWPM_IPMU_GET_MAX_PAYLOADS | 0 |
+ * | MRQ_HWPM | CMD_HWPM_NVTHERM_SET_SAMPLE_RATE | 4 |
+ * | MRQ_HWPM | CMD_HWPM_NVTHERM_SET_BUBBLE_INTERVAL | 4 |
+ * | MRQ_HWPM | CMD_HWPM_NVTHERM_SET_FLEX_CHANNELS | 120 |
+ * | MRQ_HWPM | CMD_HWPM_ISENSE_GET_SENSOR_NAME | 4 |
+ * | MRQ_HWPM | CMD_HWPM_ISENSE_GET_SENSOR_CHANNEL | 4 |
+ * | MRQ_HWPM | CMD_HWPM_ISENSE_GET_SENSOR_SCALE_FACTOR | 4 |
+ * | MRQ_HWPM | CMD_HWPM_ISENSE_GET_SENSOR_OFFSET | 4 |
+ * | MRQ_HWPM | CMD_HWPM_ISENSE_GET_SUM_BLOCK_NAME | 4 |
+ * | MRQ_HWPM | CMD_HWPM_ISENSE_GET_SUM_BLOCK_INPUTS | 4 |
+ * | MRQ_DVFS | CMD_DVFS_QUERY_ABI | 4 |
+ * | MRQ_DVFS | CMD_DVFS_SET_CTRL_STATE | 8 |
+ * | MRQ_DVFS | CMD_DVFS_SET_MGR_STATE | 8 |
+ * | MRQ_PPP_PROFILE | CMD_PPP_PROFILE_QUERY_ABI | 8 |
+ * | MRQ_PPP_PROFILE | CMD_PPP_PROFILE_QUERY_MASKS | 8 |
+ * | MRQ_PPP_PROFILE | CMD_PPP_CORE_QUERY_CPU_MASK | 8 |
+ * | MRQ_PPP_PROFILE | CMD_PPP_AVAILABLE_QUERY | 4 |
+ * @endcond
+ *
+ * @cond (bpmp_safe && bpmp_t264)
+ * The following additional MRQ is supported on functional-safety
+ * builds for the T264 platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | -------------------- | --------------------------------- | ---------------------- |
+ * | #MRQ_CPU_NDIV_LIMITS | - | 4 |
+ * | #MRQ_STRAP | #STRAP_SET | 12 |
+ * | #MRQ_SHUTDOWN | - | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_CLAMP | 16 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_FREE | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_GET | 4 |
+ * | #MRQ_FMON | #CMD_FMON_FAULT_STS_GET | 8 |
+ * | #MRQ_PCIE | #CMD_PCIE_EP_CONTROLLER_INIT | 5 |
+ * | #MRQ_PCIE | #CMD_PCIE_EP_CONTROLLER_OFF | 5 |
+ * | #MRQ_CR7 | #CMD_CR7_ENTRY | 12 |
+ * | #MRQ_CR7 | #CMD_CR7_EXIT | 12 |
+ * | #MRQ_SLC | #CMD_SLC_QUERY_ABI | 8 |
+ * | #MRQ_SLC | #CMD_SLC_BYPASS_SET | 8 |
+ * | #MRQ_SLC | #CMD_SLC_BYPASS_GET | 4 |
+ * @endcond
+ *
+ * @cond (!bpmp_safe && bpmp_t264)
+ * The following additional MRQs are supported on non-functional-safety
+ * builds for the T264 -platform:
+ *
+ * | MRQ | Sub-command | Minimum payload length |
+ * | -------------------- | --------------------------------- | ---------------------- |
+ * | #MRQ_CPU_NDIV_LIMITS | - | 4 |
+ * | #MRQ_STRAP | #STRAP_SET | 12 |
+ * | #MRQ_SHUTDOWN | - | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_CLAMP | 16 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_FREE | 4 |
+ * | #MRQ_FMON | #CMD_FMON_GEAR_GET | 4 |
+ * | #MRQ_FMON | #CMD_FMON_FAULT_STS_GET | 8 |
+ * | #MRQ_OC_STATUS | - | 0 |
+ * | #MRQ_PCIE | #CMD_PCIE_EP_CONTROLLER_INIT | 5 |
+ * | #MRQ_PCIE | #CMD_PCIE_EP_CONTROLLER_OFF | 5 |
+ * | #MRQ_PCIE | #CMD_PCIE_RP_CONTROLLER_OFF | 5 |
+ * | #MRQ_CR7 | #CMD_CR7_ENTRY | 12 |
+ * | #MRQ_CR7 | #CMD_CR7_EXIT | 12 |
+ * | #MRQ_SLC | #CMD_SLC_QUERY_ABI | 8 |
+ * | #MRQ_SLC | #CMD_SLC_BYPASS_SET | 8 |
+ * | #MRQ_SLC | #CMD_SLC_BYPASS_GET | 4 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_QUERY_ABI | 8 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_CALCULATE_LA | 16 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_SET_LA | 16 |
+ * | #MRQ_ISO_CLIENT | #CMD_ISO_CLIENT_GET_MAX_BW | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_QUERY_ABI | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_CALC_AND_SET | 16 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_CAP_SET | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_CURR_AVAILABLE_BW | 8 |
+ * | #MRQ_BWMGR_INT | #CMD_BWMGR_INT_GET_LAST_REQUEST | 9 |
+ * @endcond
*
* **crc16**
*
@@ -220,7 +452,7 @@ struct mrq_request {
* including this header. However the crc16 field is considered to be set to 0 when
* calculating the CRC. Only used when #BPMP_MAIL_CRC_PRESENT is set. If
* #BPMP_MAIL_CRC_PRESENT is set and this field does not match the CRC as
- * calculated by BPMP, -BPMP_EBADMSG will be returned and the request will
+ * calculated by BPMP, -#BPMP_EBADMSG will be returned and the request will
* be ignored. See code snippet below on how to calculate the CRC.
*
* @code
@@ -322,6 +554,9 @@ struct mrq_response {
#define MRQ_CPU_VHINT 28U
#define MRQ_ABI_RATCHET 29U
#define MRQ_EMC_DVFS_LATENCY 31U
+//adoc: tag::bpmp_dmce_mrq_shutdown[]
+#define MRQ_SHUTDOWN 49U
+//adoc: end::bpmp_dmce_mrq_shutdown[]
#define MRQ_RINGBUF_CONSOLE 65U
#define MRQ_PG 66U
#define MRQ_CPU_NDIV_LIMITS 67U
@@ -341,48 +576,31 @@ struct mrq_response {
#define MRQ_GEARS 82U
#define MRQ_BWMGR_INT 83U
#define MRQ_OC_STATUS 84U
-
-/** @cond DEPRECATED */
-#define MRQ_RESERVED_2 2U
-#define MRQ_RESERVED_3 3U
-#define MRQ_RESERVED_4 4U
-#define MRQ_RESERVED_5 5U
-#define MRQ_RESERVED_6 6U
-#define MRQ_RESERVED_7 7U
-#define MRQ_RESERVED_8 8U
-#define MRQ_RESERVED_10 10U
-#define MRQ_RESERVED_11 11U
-#define MRQ_RESERVED_12 12U
-#define MRQ_RESERVED_13 13U
-#define MRQ_RESERVED_14 14U
-#define MRQ_RESERVED_15 15U
-#define MRQ_RESERVED_16 16U
-#define MRQ_RESERVED_17 17U
-#define MRQ_RESERVED_18 18U
-#define MRQ_RESERVED_24 24U
-#define MRQ_RESERVED_25 25U
-#define MRQ_RESERVED_26 26U
-#define MRQ_RESERVED_30 30U
-#define MRQ_RESERVED_64 64U
-#define MRQ_RESERVED_74 74U
-/** @endcond DEPRECATED */
-
-/** @} */
+#define MRQ_C2C 85U
+#define MRQ_THROTTLE 86U
+#define MRQ_PWRMODEL 87U
+#define MRQ_PCIE 88U
+#define MRQ_PWR_CNTRL 89U
+#define MRQ_CR7 90U
+#define MRQ_SLC 91U
+#define MRQ_TELEMETRY_EX 92U
+#define MRQ_HWPM 93U
+#define MRQ_DVFS 94U
+#define MRQ_PPP_PROFILE 95U
/**
- * @ingroup MRQ_Codes
* @brief Maximum MRQ code to be sent by CPU software to
* BPMP. Subject to change in future
*/
-#define MAX_CPU_MRQ_ID 84U
+#define MAX_CPU_MRQ_ID 95U
+
+/** @} */
/**
* @addtogroup MRQ_Payloads
* @{
* @defgroup Ping Ping
* @defgroup Query_Tag Query Tag
- * @defgroup Module Loadable Modules
- * @defgroup Trace Trace
* @defgroup Debugfs Debug File System
* @defgroup Reset Reset
* @defgroup I2C I2C
@@ -390,6 +608,7 @@ struct mrq_response {
* @defgroup ABI_info ABI Info
* @defgroup Powergating Power Gating
* @defgroup Thermal Thermal
+ * @defgroup Throttle Throttle
* @defgroup OC_status OC status
* @defgroup Vhint CPU Voltage hint
* @defgroup EMC EMC
@@ -405,7 +624,22 @@ struct mrq_response {
* @defgroup Telemetry Telemetry
* @defgroup Pwrlimit PWR_LIMIT
* @defgroup Gears Gears
+ * @defgroup Shutdown Shutdown
* @defgroup BWMGR_INT Bandwidth Manager Integrated
+ * @defgroup C2C C2C
+ * @defgroup Pwrmodel Power Model
+ * @defgroup Pwrcntrl Power Controllers
+ * @cond bpmp_t264
+ * * @defgroup PCIE PCIE
+ * * @defgroup CR7 CR7
+ * * @defgroup Slc Slc
+ * @endcond
+ * @cond bpmp_tb500
+ * * @defgroup Telemetry_ex Telemetry Expanded
+ * * @defgroup HWPM Hardware Performance Monitoring
+ * * @defgroup DVFS Dynamic Voltage and Frequency Scaling
+ * * @defgroup PPP power/performance profiles
+ * @endcond
* @} MRQ_Payloads
*/
@@ -414,7 +648,6 @@ struct mrq_response {
* @def MRQ_PING
* @brief A simple ping
*
- * * Platforms: All
* * Initiators: Any
* * Targets: Any
* * Request Payload: @ref mrq_ping_request
@@ -424,7 +657,6 @@ struct mrq_response {
* @def MRQ_THREADED_PING
* @brief A deeper ping
*
- * * Platforms: All
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_ping_request
@@ -441,8 +673,8 @@ struct mrq_response {
* @brief Request with #MRQ_PING
*
* Used by the sender of an #MRQ_PING message to request a pong from
- * recipient. The response from the recipient is computed based on
- * #challenge.
+ * recipient. The response from the recipient is computed based on the
+ * mrq_ping_request::challenge -value.
*/
struct mrq_ping_request {
/** @brief Arbitrarily chosen value */
@@ -470,7 +702,7 @@ struct mrq_ping_response {
*
* @deprecated Use #MRQ_QUERY_FW_TAG instead.
*
- * * Platforms: All
+ * @details
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_query_tag_request
@@ -483,7 +715,7 @@ struct mrq_ping_response {
* @brief Request with #MRQ_QUERY_TAG
*
* @deprecated This structure will be removed in future version.
- * Use MRQ_QUERY_FW_TAG instead.
+ * Use #MRQ_QUERY_FW_TAG instead.
*/
struct mrq_query_tag_request {
/** @brief Base address to store the firmware tag */
@@ -496,7 +728,6 @@ struct mrq_query_tag_request {
* @def MRQ_QUERY_FW_TAG
* @brief Query BPMP firmware's tag (i.e. unique identifier)
*
- * * Platforms: All
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: N/A
@@ -510,10 +741,9 @@ struct mrq_query_tag_request {
*
* Sent in response to #MRQ_QUERY_FW_TAG message. #tag contains the unique
* identifier for the version of firmware issuing the reply.
- *
*/
struct mrq_query_fw_tag_response {
- /** @brief Array to store tag information */
+ /** @brief Array to store tag information */
uint8_t tag[32];
} BPMP_ABI_PACKED;
@@ -532,9 +762,8 @@ struct mrq_threaded_ping_response {
* @def MRQ_DEBUGFS
* @brief Interact with BPMP's debugfs file nodes
*
- * @deprecated use MRQ_DEBUG instead.
+ * @deprecated Use #MRQ_DEBUG instead.
*
- * * Platforms: T186, T194
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_debugfs_request
@@ -626,9 +855,9 @@ struct cmd_debugfs_dumpdir_response {
/**
* @ingroup Debugfs
- * @brief Request with #MRQ_DEBUGFS.
+ * @brief Request with #MRQ_DEBUG.
*
- * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs
+ * The sender of an MRQ_DEBUG message uses #cmd to specify a debugfs
* command to execute. Legal commands are the values of @ref
* mrq_debugfs_commands. Each command requires a specific additional
* payload of data.
@@ -676,16 +905,15 @@ struct mrq_debugfs_response {
/**
* @ingroup MRQ_Codes
* @def MRQ_DEBUG
- * @brief Interact with BPMP's debugfs file nodes. Use message payload
+ * @brief Interact with BPMP-FW debugfs file nodes. Use message payload
* for exchanging data. This is functionally equivalent to
- * @ref MRQ_DEBUGFS. But the way in which data is exchanged is different.
- * When software running on CPU tries to read a debugfs file,
+ * the deprecated MRQ_DEBUGFS but the way in which data is exchanged is
+ * different. When software running on CPU tries to read a debugfs file,
* the file path and read data will be stored in message payload.
* Since the message payload size is limited, a debugfs file
* transaction might require multiple frames of data exchanged
* between BPMP and CPU until the transaction completes.
*
- * * Platforms: T194
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_debug_request
@@ -694,17 +922,34 @@ struct mrq_debugfs_response {
/** @ingroup Debugfs */
enum mrq_debug_commands {
- /** @brief Open required file for read operation */
+ /**
+ * @brief Open file represented by the path in
+ * cmd_debug_fopen_request::name for read operation
+ */
CMD_DEBUG_OPEN_RO = 0,
- /** @brief Open required file for write operation */
+ /**
+ * @brief Open file represented by the path in
+ * cmd_debug_fopen_request::name for write operation
+ */
CMD_DEBUG_OPEN_WO = 1,
- /** @brief Perform read */
+ /**
+ * @brief Perform read on a previously opened file handle represented
+ * by the cmd_debug_fread_request::fd -value.
+ */
CMD_DEBUG_READ = 2,
- /** @brief Perform write */
+ /**
+ * @brief Perform write on a previously opened file handle represented
+ * by the cmd_debug_fwrite_request::fd -value.
+ */
CMD_DEBUG_WRITE = 3,
- /** @brief Close file */
+ /**
+ * @brief Close previously opened file handle.
+ */
CMD_DEBUG_CLOSE = 4,
- /** @brief Not a command */
+ /**
+ * @brief Not a command, represents maximum number of supported
+ * sub-commands
+ */
CMD_DEBUG_MAX
};
@@ -727,35 +972,38 @@ enum mrq_debug_commands {
/**
* @ingroup Debugfs
- * @brief Parameters for CMD_DEBUG_OPEN command
+ * @brief Parameters for #CMD_DEBUG_OPEN_RO and #CMD_DEBUG_OPEN_WO -commands
*/
struct cmd_debug_fopen_request {
- /** @brief File name - Null-terminated string with maximum
- * length @ref DEBUG_FNAME_MAX_SZ
+ /**
+ * @brief File name - Null-terminated string with maximum
+ * length including the terminator defined by the
+ * #DEBUG_FNAME_MAX_SZ -preprocessor constant.
*/
char name[DEBUG_FNAME_MAX_SZ];
} BPMP_ABI_PACKED;
/**
* @ingroup Debugfs
- * @brief Response data for CMD_DEBUG_OPEN_RO/WO command
+ * @brief Response data for #CMD_DEBUG_OPEN_RO and #CMD_DEBUG_OPEN_WO commands
*/
struct cmd_debug_fopen_response {
/** @brief Identifier for file access */
uint32_t fd;
/** @brief Data length. File data size for READ command.
- * Maximum allowed length for WRITE command
+ * Maximum allowed length for WRITE command
*/
uint32_t datalen;
} BPMP_ABI_PACKED;
/**
* @ingroup Debugfs
- * @brief Parameters for CMD_DEBUG_READ command
+ * @brief Parameters for #CMD_DEBUG_READ command
*/
struct cmd_debug_fread_request {
- /** @brief File access identifier received in response
- * to CMD_DEBUG_OPEN_RO request
+ /**
+ * @brief File access identifier received in response
+ * to #CMD_DEBUG_OPEN_RO request
*/
uint32_t fd;
} BPMP_ABI_PACKED;
@@ -770,7 +1018,7 @@ struct cmd_debug_fread_request {
/**
* @ingroup Debugfs
- * @brief Response data for CMD_DEBUG_READ command
+ * @brief Response data for #CMD_DEBUG_READ command
*/
struct cmd_debug_fread_response {
/** @brief Size of data provided in this response in bytes */
@@ -789,11 +1037,11 @@ struct cmd_debug_fread_response {
/**
* @ingroup Debugfs
- * @brief Parameters for CMD_DEBUG_WRITE command
+ * @brief Parameters for #CMD_DEBUG_WRITE command
*/
struct cmd_debug_fwrite_request {
/** @brief File access identifier received in response
- * to CMD_DEBUG_OPEN_RO request
+ * to prior #CMD_DEBUG_OPEN_RO -request
*/
uint32_t fd;
/** @brief Size of write data in bytes */
@@ -804,11 +1052,12 @@ struct cmd_debug_fwrite_request {
/**
* @ingroup Debugfs
- * @brief Parameters for CMD_DEBUG_CLOSE command
+ * @brief Parameters for #CMD_DEBUG_CLOSE command
*/
struct cmd_debug_fclose_request {
- /** @brief File access identifier received in response
- * to CMD_DEBUG_OPEN_RO request
+ /**
+ * @brief File access identifier received in prior response
+ * to #CMD_DEBUG_OPEN_RO or #CMD_DEBUG_OPEN_WO -request.
*/
uint32_t fd;
} BPMP_ABI_PACKED;
@@ -817,30 +1066,34 @@ struct cmd_debug_fclose_request {
* @ingroup Debugfs
* @brief Request with #MRQ_DEBUG.
*
- * The sender of an MRQ_DEBUG message uses #cmd to specify a debugfs
- * command to execute. Legal commands are the values of @ref
- * mrq_debug_commands. Each command requires a specific additional
- * payload of data.
+ * The sender of an #MRQ_DEBUG message uses mrq_debug_request::cmd to specify
+ * which debugfs sub-command to execute. Legal sub-commands are the values
+ * specified in the @ref mrq_debug_commands -enumeration. Each sub-command
+ * requires a specific additional payload of data according to the following
+ * table:
*
- * |command |payload|
- * |-------------------|-------|
- * |CMD_DEBUG_OPEN_RO |fop |
- * |CMD_DEBUG_OPEN_WO |fop |
- * |CMD_DEBUG_READ |frd |
- * |CMD_DEBUG_WRITE |fwr |
- * |CMD_DEBUG_CLOSE |fcl |
+ * |Sub-command |Payload structure |
+ * |--------------------|---------------------------|
+ * |#CMD_DEBUG_OPEN_RO |cmd_debug_fopen_request |
+ * |#CMD_DEBUG_OPEN_WO |cmd_debug_fopen_request |
+ * |#CMD_DEBUG_READ |cmd_debug_fread_request |
+ * |#CMD_DEBUG_WRITE |cmd_debug_fwrite_request |
+ * |#CMD_DEBUG_CLOSE |cmd_debug_fclose_request |
*/
struct mrq_debug_request {
- /** @brief Sub-command (@ref mrq_debug_commands) */
+ /** @brief Sub-command identifier from @ref mrq_debug_commands */
uint32_t cmd;
union {
- /** @brief Request payload for CMD_DEBUG_OPEN_RO/WO command */
+ /**
+ * @brief Request payload for #CMD_DEBUG_OPEN_RO and
+ * #CMD_DEBUG_OPEN_WO sub-commands
+ */
struct cmd_debug_fopen_request fop;
- /** @brief Request payload for CMD_DEBUG_READ command */
+ /** @brief Request payload for #CMD_DEBUG_READ sub-command */
struct cmd_debug_fread_request frd;
- /** @brief Request payload for CMD_DEBUG_WRITE command */
+ /** @brief Request payload for #CMD_DEBUG_WRITE sub-command */
struct cmd_debug_fwrite_request fwr;
- /** @brief Request payload for CMD_DEBUG_CLOSE command */
+ /** @brief Request payload for #CMD_DEBUG_CLOSE sub-command */
struct cmd_debug_fclose_request fcl;
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
@@ -850,9 +1103,12 @@ struct mrq_debug_request {
*/
struct mrq_debug_response {
union {
- /** @brief Response data for CMD_DEBUG_OPEN_RO/WO command */
+ /**
+ * @brief Response data for the #CMD_DEBUG_OPEN_RO and
+ * #CMD_DEBUG_OPEN_WO sub-commands
+ */
struct cmd_debug_fopen_response fop;
- /** @brief Response data for CMD_DEBUG_READ command */
+ /** @brief Response data for the #CMD_DEBUG_READ sub-command */
struct cmd_debug_fread_response frd;
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
@@ -862,7 +1118,6 @@ struct mrq_debug_response {
* @def MRQ_RESET
* @brief Reset an IP block
*
- * * Platforms: T186, T194
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_reset_request
@@ -872,39 +1127,46 @@ struct mrq_debug_response {
* @{
*/
+/**
+ * @brief Sub-command identifiers for #MRQ_RESET
+ */
enum mrq_reset_commands {
/**
* @brief Assert module reset
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_EINVAL if mrq_reset_request::reset_id is invalid @n
- * -#BPMP_EACCES if mrq master is not an owner of target domain reset @n
- * -#BPMP_ENOTSUP if target domain h/w state does not allow reset
+ * mrq_response::err is
+ * * 0 if the operation was successful
+ * * -#BPMP_EINVAL if mrq_reset_request::reset_id is invalid
+ * * -#BPMP_EACCES if mrq master is not an owner of target domain reset
+ * * -#BPMP_ENOTSUP if target domain h/w state does not allow reset
*/
CMD_RESET_ASSERT = 1,
/**
* @brief Deassert module reset
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_EINVAL if mrq_reset_request::reset_id is invalid @n
- * -#BPMP_EACCES if mrq master is not an owner of target domain reset @n
- * -#BPMP_ENOTSUP if target domain h/w state does not allow reset
+ * mrq_response::err is
+ * * 0 if the operation was successful
+ * * -#BPMP_EINVAL if mrq_reset_request::reset_id is invalid
+ * * -#BPMP_EACCES if mrq master is not an owner of target domain reset
+ * * -#BPMP_ENOTSUP if target domain h/w state does not allow reset
*/
CMD_RESET_DEASSERT = 2,
/**
* @brief Assert and deassert the module reset
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_EINVAL if mrq_reset_request::reset_id is invalid @n
- * -#BPMP_EACCES if mrq master is not an owner of target domain reset @n
- * -#BPMP_ENOTSUP if target domain h/w state does not allow reset
+ * mrq_response::err is
+ * * 0 if the operation was successful
+ * * -#BPMP_EINVAL if mrq_reset_request::reset_id is invalid
+ * * -#BPMP_EACCES if mrq master is not an owner of target domain reset
+ * * -#BPMP_ENOTSUP if target domain h/w state does not allow reset
*/
CMD_RESET_MODULE = 3,
/**
* @brief Get the highest reset ID
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_ENODEV if no reset domains are supported (number of IDs is 0)
+ * mrq_response::err is
+ * * 0 if the operation was successful
+ * * -#BPMP_ENODEV if no reset domains are supported (number of IDs is 0)
*/
CMD_RESET_GET_MAX_ID = 4,
@@ -913,15 +1175,15 @@ enum mrq_reset_commands {
};
/**
- * @brief Request with MRQ_RESET
+ * @brief Request with #MRQ_RESET
*
* Used by the sender of an #MRQ_RESET message to request BPMP to
- * assert or or deassert a given reset line.
+ * assert or deassert a given reset line.
*/
struct mrq_reset_request {
- /** @brief Reset action to perform (@ref mrq_reset_commands) */
+ /** @brief Reset action to perform, from @ref mrq_reset_commands */
uint32_t cmd;
- /** @brief Id of the reset to affected */
+ /** @brief ID of the reset to affected, from @ref bpmp_reset_ids */
uint32_t reset_id;
} BPMP_ABI_PACKED;
@@ -940,7 +1202,7 @@ struct cmd_reset_get_max_id_response {
*
* Each sub-command supported by @ref mrq_reset_request may return
* sub-command-specific data. Some do and some do not as indicated
- * in the following table
+ * in the following table:
*
* | sub-command | payload |
* |----------------------|------------------|
@@ -962,7 +1224,6 @@ struct mrq_reset_response {
* @def MRQ_I2C
* @brief Issue an i2c transaction
*
- * * Platforms: T186, T194
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_i2c_request
@@ -971,19 +1232,60 @@ struct mrq_reset_response {
* @addtogroup I2C
* @{
*/
+
+/**
+ * @brief Size of the cmd_i2c_xfer_request::data_buf -member array in bytes.
+ */
#define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE (MSG_DATA_MIN_SZ - 12U)
+
+/**
+ * @brief Size of the cmd_i2c_xfer_response::data_buf -member array in bytes.
+ */
#define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE (MSG_DATA_MIN_SZ - 4U)
+/**
+ * @defgroup seriali2c_flags I2C flags
+ *
+ * @brief I2C transaction modifier flags for each transaction segment
+ * in #MRQ_I2C subcommand CMD_I2C_XFER
+ */
+
+/**
+ * @addtogroup seriali2c_flags
+ * @{
+ */
+
+/** @brief when set, use 10-bit I2C slave address */
#define SERIALI2C_TEN 0x0010U
+/** @brief when set, perform a Read transaction */
#define SERIALI2C_RD 0x0001U
-#define SERIALI2C_STOP 0x8000U
+/**
+ * @brief when set, no repeated START is issued between the segments
+ * of transaction. This flag is ignored for the first segment as any
+ * transaction always starts with a START condition
+ */
#define SERIALI2C_NOSTART 0x4000U
-#define SERIALI2C_REV_DIR_ADDR 0x2000U
+/**
+ * @brief when set, a no-ACK from slave device is ignored and treated
+ * always as success
+ */
#define SERIALI2C_IGNORE_NAK 0x1000U
+/** @} seriali2c_flags */
+
+/** brief Unused flag. Retained for backwards compatibility. */
+#define SERIALI2C_STOP 0x8000U
+/** brief Unused flag. Retained for backwards compatibility. */
+#define SERIALI2C_REV_DIR_ADDR 0x2000U
+/** brief Unused flag. Retained for backwards compatibility. */
#define SERIALI2C_NO_RD_ACK 0x0800U
+/** brief Unused flag. Retained for backwards compatibility. */
#define SERIALI2C_RECV_LEN 0x0400U
-enum {
+/**
+ * @brief Supported I2C sub-command identifiers
+ */
+enum mrq_i2c_commands {
+ /** @brief Perform an I2C transaction */
CMD_I2C_XFER = 1
};
@@ -1005,7 +1307,7 @@ enum {
struct serial_i2c_request {
/** @brief I2C slave address */
uint16_t addr;
- /** @brief Bitmask of SERIALI2C_ flags */
+ /** @brief Bitmask of @ref seriali2c_flags */
uint16_t flags;
/** @brief Length of I2C transaction in bytes */
uint16_t len;
@@ -1020,13 +1322,13 @@ struct cmd_i2c_xfer_request {
/**
* @brief Tegra PWR_I2C bus identifier
*
- * @cond (bpmp_t234 || bpmp_t238 || bpmp_t194)
+ * @cond (bpmp_t186 || bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_t264)
* Must be set to 5.
- * @endcond (bpmp_t234 || bpmp_t238 || bpmp_t194)
- * @cond bpmp_th500
- * Must be set to 1.
- * @endcond bpmp_th500
+ * @endcond
*
+ * @cond (bpmp_th500)
+ * Must be set to 1.
+ * @endcond
*/
uint32_t bus_id;
@@ -1047,7 +1349,7 @@ struct cmd_i2c_xfer_request {
struct cmd_i2c_xfer_response {
/** @brief Count of valid bytes in #data_buf*/
uint32_t data_size;
- /** @brief I2c read data */
+ /** @brief I2C read data */
uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE];
} BPMP_ABI_PACKED;
@@ -1064,16 +1366,19 @@ struct mrq_i2c_request {
/**
* @brief Response to #MRQ_I2C
*
- * mrq_response:err is
- * 0: Success
- * -#BPMP_EBADCMD: if mrq_i2c_request::cmd is other than 1
- * -#BPMP_EINVAL: if cmd_i2c_xfer_request does not contain correctly formatted request
- * -#BPMP_ENODEV: if cmd_i2c_xfer_request::bus_id is not supported by BPMP
- * -#BPMP_EACCES: if i2c transaction is not allowed due to firewall rules
- * -#BPMP_ETIMEDOUT: if i2c transaction times out
- * -#BPMP_ENXIO: if i2c slave device does not reply with ACK to the transaction
- * -#BPMP_EAGAIN: if ARB_LOST condition is detected by the i2c controller
- * -#BPMP_EIO: any other i2c controller error code than NO_ACK or ARB_LOST
+ * mrq_response::err value for this response is defined as:
+ *
+ * | Value | Description |
+ * |--------------------|---------------------------------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_EBADCMD | mrq_i2c_request::cmd is other than 1 |
+ * | -#BPMP_EINVAL | cmd_i2c_xfer_request does not contain correctly formatted request |
+ * | -#BPMP_ENODEV | cmd_i2c_xfer_request::bus_id is not supported by BPMP |
+ * | -#BPMP_EACCES | I2C transaction is not allowed due to firewall rules |
+ * | -#BPMP_ETIMEDOUT | I2C transaction times out |
+ * | -#BPMP_ENXIO | I2C slave device does not reply with ACK to the transaction |
+ * | -#BPMP_EAGAIN | ARB_LOST condition is detected by the I2C controller |
+ * | -#BPMP_EIO | Any other I2C controller error code than NO_ACK or ARB_LOST |
*/
struct mrq_i2c_response {
struct cmd_i2c_xfer_response xfer;
@@ -1086,7 +1391,6 @@ struct mrq_i2c_response {
* @def MRQ_CLK
* @brief Perform a clock operation
*
- * * Platforms: T186, T194
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_clk_request
@@ -1095,205 +1399,354 @@ struct mrq_i2c_response {
* @addtogroup Clocks
* @{
*/
-enum {
+
+/**
+ * @brief Sub-command identifiers for #MRQ_CLK
+ */
+enum mrq_clk_commands {
+ /** Get clock rate */
CMD_CLK_GET_RATE = 1,
+
+ /** Set clock rate */
CMD_CLK_SET_RATE = 2,
+
+ /** Get attainable clock rate closer to a given rate */
CMD_CLK_ROUND_RATE = 3,
+
+ /** Get parent clock identifier for a given clock */
CMD_CLK_GET_PARENT = 4,
+
+ /** Change clock parent */
CMD_CLK_SET_PARENT = 5,
+
+ /** Get clock enable status */
CMD_CLK_IS_ENABLED = 6,
+
+ /** Enable a clock */
CMD_CLK_ENABLE = 7,
+
+ /** Disable a clock */
CMD_CLK_DISABLE = 8,
-/** @cond DEPRECATED */
- CMD_CLK_PROPERTIES = 9,
- CMD_CLK_POSSIBLE_PARENTS = 10,
- CMD_CLK_NUM_POSSIBLE_PARENTS = 11,
- CMD_CLK_GET_POSSIBLE_PARENT = 12,
- CMD_CLK_RESET_REFCOUNTS = 13,
-/** @endcond DEPRECATED */
+
+ /** Get all information about a clock */
CMD_CLK_GET_ALL_INFO = 14,
+
+ /** Get largest supported clock identifier */
CMD_CLK_GET_MAX_CLK_ID = 15,
+
+ /** Get clock maximum rate at VMIN */
CMD_CLK_GET_FMAX_AT_VMIN = 16,
+
+ /** Largest supported #MRQ_CLK sub-command identifier + 1 */
CMD_CLK_MAX,
};
+/**
+ * Flag bit set in cmd_clk_get_all_info_response::flags -field when clock
+ * supports changing of the parent clock at runtime.
+ */
#define BPMP_CLK_HAS_MUX (1U << 0U)
+
+/**
+ * Flag bit set in cmd_clk_get_all_info_response::flags -field when clock
+ * supports changing the clock rate at runtime.
+ */
#define BPMP_CLK_HAS_SET_RATE (1U << 1U)
+
+/**
+ * Flag bit set in cmd_clk_get_all_info_response::flags -field when clock is a
+ * root clock without visible parents.
+ */
#define BPMP_CLK_IS_ROOT (1U << 2U)
+
#define BPMP_CLK_IS_VAR_ROOT (1U << 3U)
+
/**
* @brief Protection against rate and parent changes
*
- * #MRQ_CLK command #CMD_CLK_SET_RATE or #MRQ_CLK command #CMD_CLK_SET_PARENT will return
- * -#BPMP_EACCES.
+ * #MRQ_CLK command #CMD_CLK_SET_RATE or #MRQ_CLK command #CMD_CLK_SET_PARENT
+ * will return -#BPMP_EACCES.
*/
#define BPMP_CLK_RATE_PARENT_CHANGE_DENIED (1U << 30)
/**
* @brief Protection against state changes
*
- * #MRQ_CLK command #CMD_CLK_ENABLE or #MRQ_CLK command #CMD_CLK_DISABLE will return
- * -#BPMP_EACCES.
+ * #MRQ_CLK command #CMD_CLK_ENABLE or #MRQ_CLK command #CMD_CLK_DISABLE
+ * will return -#BPMP_EACCES.
*/
#define BPMP_CLK_STATE_CHANGE_DENIED (1U << 31)
+/**
+ * Size of the cmd_clk_get_all_info_response::name -array in number
+ * of elements.
+ */
#define MRQ_CLK_NAME_MAXLEN 40U
+
+/**
+ * @brief Maximum number of elements in parent_id arrays of clock info responses.
+ */
#define MRQ_CLK_MAX_PARENTS 16U
-/** @private */
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_GET_RATE
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_get_rate_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_GET_RATE
+ */
struct cmd_clk_get_rate_response {
+ /**
+ * Current rate of the given clock in Hz if mrq_response::err is 0 to
+ * indicate successful #CMD_CLK_GET_RATE -request.
+ */
int64_t rate;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_SET_RATE
+ */
struct cmd_clk_set_rate_request {
+ /** Unused / reserved field. */
int32_t unused;
+
+ /** Requested rate of the clock in Hz. */
int64_t rate;
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_SET_RATE
+ */
struct cmd_clk_set_rate_response {
+ /**
+ * If request was successful (mrq_response::err is 0), set to the new
+ * rate of the given clock in Hz.
+ */
int64_t rate;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_ROUND_RATE
+ */
struct cmd_clk_round_rate_request {
+ /** Unused / reserved field. */
int32_t unused;
+
+ /** Target rate for the clock */
int64_t rate;
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_ROUND_RATE
+ */
struct cmd_clk_round_rate_response {
+ /**
+ * The attainable rate if request was successful
+ * (mrq_response::err is 0).
+ */
int64_t rate;
} BPMP_ABI_PACKED;
-/** @private */
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_GET_PARENT
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_get_parent_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_GET_PARENT
+ */
struct cmd_clk_get_parent_response {
+ /**
+ * The clock identifier of the parent clock if request was successful
+ * (mrq_response::err is 0).
+ */
uint32_t parent_id;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_SET_PARENT
+ */
struct cmd_clk_set_parent_request {
+ /**
+ * The clock identifier of the new parent clock.
+ */
uint32_t parent_id;
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_SET_PARENT
+ */
struct cmd_clk_set_parent_response {
+ /**
+ * The clock identifier of the new parent clock if request was
+ * successful (mrq_response::err is 0).
+ */
uint32_t parent_id;
} BPMP_ABI_PACKED;
-/** @private */
+/**
+ * @brief Request payload for #CMD_CLK_IS_ENABLED -sub-command
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_is_enabled_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
/**
- * @brief Response data to #MRQ_CLK sub-command CMD_CLK_IS_ENABLED
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_IS_ENABLED
*/
struct cmd_clk_is_enabled_response {
/**
* @brief The state of the clock that has been successfully
- * requested with CMD_CLK_ENABLE or CMD_CLK_DISABLE by the
+ * requested with #CMD_CLK_ENABLE or #CMD_CLK_DISABLE by the
* master invoking the command earlier.
*
* The state may not reflect the physical state of the clock
* if there are some other masters requesting it to be
- * enabled.
+ * enabled. Valid values:
*
- * Value 0 is disabled, all other values indicate enabled.
+ * * Value 0: The clock is disabled,
+ * * Value 1: The clock is enabled.
*/
int32_t state;
} BPMP_ABI_PACKED;
-/** @private */
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_ENABLE
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_enable_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
-/** @private */
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_ENABLE
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_enable_response {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
-/** @private */
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_DISABLE
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_disable_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
-/** @private */
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_DISABLE
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_disable_response {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
-/** @cond DEPRECATED */
-/** @private */
-struct cmd_clk_properties_request {
- BPMP_ABI_EMPTY
-} BPMP_ABI_PACKED;
-
-/** @todo flags need to be spelled out here */
-struct cmd_clk_properties_response {
- uint32_t flags;
-} BPMP_ABI_PACKED;
-
-/** @private */
-struct cmd_clk_possible_parents_request {
- BPMP_ABI_EMPTY
-} BPMP_ABI_PACKED;
-
-struct cmd_clk_possible_parents_response {
- uint8_t num_parents;
- uint8_t reserved[3];
- uint32_t parent_id[MRQ_CLK_MAX_PARENTS];
-} BPMP_ABI_PACKED;
-
-/** @private */
-struct cmd_clk_num_possible_parents_request {
- BPMP_ABI_EMPTY
-} BPMP_ABI_PACKED;
-
-struct cmd_clk_num_possible_parents_response {
- uint8_t num_parents;
-} BPMP_ABI_PACKED;
-
-struct cmd_clk_get_possible_parent_request {
- uint8_t parent_idx;
-} BPMP_ABI_PACKED;
-
-struct cmd_clk_get_possible_parent_response {
- uint32_t parent_id;
-} BPMP_ABI_PACKED;
-/** @endcond DEPRECATED */
-
-/** @private */
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_GET_ALL_INFO
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_get_all_info_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_GET_ALL_INFO
+ *
+ * The values in the response are only set and valid if request status in
+ * mrq_response::err is 0.
+ */
struct cmd_clk_get_all_info_response {
+ /**
+ * State / informational flags for the clock:
+ *
+ * | Flag bit | Description |
+ * |------------------------|------------------------------------------|
+ * | #BPMP_CLK_IS_ROOT | Clock is a root clock. |
+ * | #BPMP_CLK_HAS_MUX | Clock supports changing of parent clock. |
+ * | #BPMP_CLK_HAS_SET_RATE | Clock supports changing clock rate. |
+ */
uint32_t flags;
+
+ /**
+ * Current parent clock identifier.
+ */
uint32_t parent;
+
+ /**
+ * Array of possible parent clock identifiers.
+ */
uint32_t parents[MRQ_CLK_MAX_PARENTS];
+
+ /**
+ * Number of identifiers in the #parents -array.
+ */
uint8_t num_parents;
+
+ /**
+ * Friendly name of the clock, truncated to fit the array
+ * and null-terminated.
+ */
uint8_t name[MRQ_CLK_NAME_MAXLEN];
} BPMP_ABI_PACKED;
-/** @private */
+
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_GET_MAX_CLK_ID
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_get_max_clk_id_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_GET_MAX_CLK_ID
+ */
struct cmd_clk_get_max_clk_id_response {
+ /** @brief Largest supported clock identifier. */
uint32_t max_id;
} BPMP_ABI_PACKED;
-/** @private */
+/**
+ * @brief Request payload for #MRQ_CLK sub-command #CMD_CLK_GET_FMAX_AT_VMIN
+ *
+ * This structure is an empty placeholder for future expansion of this
+ * sub-command.
+ */
struct cmd_clk_get_fmax_at_vmin_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_CLK sub-command #CMD_CLK_GET_FMAX_AT_VMIN
+ */
struct cmd_clk_get_fmax_at_vmin_response {
int64_t rate;
} BPMP_ABI_PACKED;
@@ -1308,38 +1761,26 @@ struct cmd_clk_get_fmax_at_vmin_response {
* require no additional data. Others have a sub-command specific
* payload
*
- * |sub-command |payload |
- * |----------------------------|-----------------------|
- * |CMD_CLK_GET_RATE |- |
- * |CMD_CLK_SET_RATE |clk_set_rate |
- * |CMD_CLK_ROUND_RATE |clk_round_rate |
- * |CMD_CLK_GET_PARENT |- |
- * |CMD_CLK_SET_PARENT |clk_set_parent |
- * |CMD_CLK_IS_ENABLED |- |
- * |CMD_CLK_ENABLE |- |
- * |CMD_CLK_DISABLE |- |
- * |CMD_CLK_GET_ALL_INFO |- |
- * |CMD_CLK_GET_MAX_CLK_ID |- |
- * |CMD_CLK_GET_FMAX_AT_VMIN |-
- * |
- *
+ * |Sub-command |Payload |
+ * |----------------------------|-----------------------------|
+ * |#CMD_CLK_GET_RATE |- |
+ * |#CMD_CLK_SET_RATE |#cmd_clk_set_rate_request |
+ * |#CMD_CLK_ROUND_RATE |#cmd_clk_round_rate_request |
+ * |#CMD_CLK_GET_PARENT |- |
+ * |#CMD_CLK_SET_PARENT |#cmd_clk_set_parent_request |
+ * |#CMD_CLK_IS_ENABLED |- |
+ * |#CMD_CLK_ENABLE |- |
+ * |#CMD_CLK_DISABLE |- |
+ * |#CMD_CLK_GET_ALL_INFO |- |
+ * |#CMD_CLK_GET_MAX_CLK_ID |- |
+ * |#CMD_CLK_GET_FMAX_AT_VMIN |- |
*/
-/** @cond DEPRECATED
- *
- * Older versions of firmware also supported following sub-commands:
- * |CMD_CLK_PROPERTIES |- |
- * |CMD_CLK_POSSIBLE_PARENTS |- |
- * |CMD_CLK_NUM_POSSIBLE_PARENTS|- |
- * |CMD_CLK_GET_POSSIBLE_PARENT |clk_get_possible_parent|
- * |CMD_CLK_RESET_REFCOUNTS |- |
- *
- * @endcond DEPRECATED */
-
struct mrq_clk_request {
/** @brief Sub-command and clock id concatenated to 32-bit word.
- * - bits[31..24] is the sub-cmd.
- * - bits[23..0] is the clock id
+ *
+ * - bits[31..24] is the sub-command ID from @ref mrq_clk_commands.
+ * - bits[23..0] is the clock identifier from @ref bpmp_clock_ids.
*/
uint32_t cmd_and_id;
@@ -1357,15 +1798,6 @@ struct mrq_clk_request {
struct cmd_clk_disable_request clk_disable;
/** @private */
struct cmd_clk_is_enabled_request clk_is_enabled;
- /** @cond DEPRECATED */
- /** @private */
- struct cmd_clk_properties_request clk_properties;
- /** @private */
- struct cmd_clk_possible_parents_request clk_possible_parents;
- /** @private */
- struct cmd_clk_num_possible_parents_request clk_num_possible_parents;
- struct cmd_clk_get_possible_parent_request clk_get_possible_parent;
- /** @endcond DEPRECATED */
/** @private */
struct cmd_clk_get_all_info_request clk_get_all_info;
/** @private */
@@ -1381,35 +1813,24 @@ struct mrq_clk_request {
*
* Each sub-command supported by @ref mrq_clk_request may return
* sub-command-specific data. Some do and some do not as indicated in
- * the following table
+ * the following table:
*
- * |sub-command |payload |
- * |----------------------------|------------------------|
- * |CMD_CLK_GET_RATE |clk_get_rate |
- * |CMD_CLK_SET_RATE |clk_set_rate |
- * |CMD_CLK_ROUND_RATE |clk_round_rate |
- * |CMD_CLK_GET_PARENT |clk_get_parent |
- * |CMD_CLK_SET_PARENT |clk_set_parent |
- * |CMD_CLK_IS_ENABLED |clk_is_enabled |
- * |CMD_CLK_ENABLE |- |
- * |CMD_CLK_DISABLE |- |
- * |CMD_CLK_GET_ALL_INFO |clk_get_all_info |
- * |CMD_CLK_GET_MAX_CLK_ID |clk_get_max_id |
- * |CMD_CLK_GET_FMAX_AT_VMIN |clk_get_fmax_at_vmin |
+ * |Sub-command |Payload |
+ * |----------------------------|-----------------------------------|
+ * |#CMD_CLK_GET_RATE |#cmd_clk_get_rate_response |
+ * |#CMD_CLK_SET_RATE |#cmd_clk_set_rate_response |
+ * |#CMD_CLK_ROUND_RATE |#cmd_clk_round_rate_response |
+ * |#CMD_CLK_GET_PARENT |#cmd_clk_get_parent_response |
+ * |#CMD_CLK_SET_PARENT |#cmd_clk_set_parent_response |
+ * |#CMD_CLK_IS_ENABLED |#cmd_clk_is_enabled_response |
+ * |#CMD_CLK_ENABLE |- |
+ * |#CMD_CLK_DISABLE |- |
+ * |#CMD_CLK_GET_ALL_INFO |#cmd_clk_get_all_info_response |
+ * |#CMD_CLK_GET_MAX_CLK_ID |#cmd_clk_get_max_clk_id_response |
+ * |#CMD_CLK_GET_FMAX_AT_VMIN |#cmd_clk_get_fmax_at_vmin_response |
*
*/
-/** @cond DEPRECATED
- *
- * Older versions of firmware also supported following sub-commands:
- * |CMD_CLK_PROPERTIES |clk_properties |
- * |CMD_CLK_POSSIBLE_PARENTS |clk_possible_parents |
- * |CMD_CLK_NUM_POSSIBLE_PARENTS|clk_num_possible_parents|
- * |CMD_CLK_GET_POSSIBLE_PARENT |clk_get_possible_parents|
- * |CMD_CLK_RESET_REFCOUNTS |- |
- *
- * @endcond DEPRECATED */
-
struct mrq_clk_response {
union {
struct cmd_clk_get_rate_response clk_get_rate;
@@ -1422,12 +1843,6 @@ struct mrq_clk_response {
/** @private */
struct cmd_clk_disable_response clk_disable;
struct cmd_clk_is_enabled_response clk_is_enabled;
- /** @cond DEPRECATED */
- struct cmd_clk_properties_response clk_properties;
- struct cmd_clk_possible_parents_response clk_possible_parents;
- struct cmd_clk_num_possible_parents_response clk_num_possible_parents;
- struct cmd_clk_get_possible_parent_response clk_get_possible_parent;
- /** @endcond DEPRECATED */
struct cmd_clk_get_all_info_response clk_get_all_info;
struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id;
struct cmd_clk_get_fmax_at_vmin_response clk_get_fmax_at_vmin;
@@ -1441,7 +1856,6 @@ struct mrq_clk_response {
* @def MRQ_QUERY_ABI
* @brief Check if an MRQ is implemented
*
- * * Platforms: All
* * Initiators: Any
* * Targets: Any except DMCE
* * Request Payload: @ref mrq_query_abi_request
@@ -1450,7 +1864,7 @@ struct mrq_clk_response {
/**
* @ingroup ABI_info
- * @brief Request with MRQ_QUERY_ABI
+ * @brief Request with #MRQ_QUERY_ABI
*
* Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported
* by the recipient.
@@ -1468,7 +1882,11 @@ struct mrq_query_abi_request {
* successful, not that the MRQ itself is supported!
*/
struct mrq_query_abi_response {
- /** @brief 0 if queried MRQ is supported. Else, -#BPMP_ENODEV */
+ /**
+ * This response field is set to:
+ * - 0 if queried MRQ is supported, or
+ * - -#BPMP_ENODEV if queried MRQ is not supported
+ */
int32_t status;
} BPMP_ABI_PACKED;
@@ -1476,9 +1894,7 @@ struct mrq_query_abi_response {
*
* @ingroup MRQ_Codes
* @def MRQ_PG
- * @brief Control power-gating state of a partition. In contrast to
- * MRQ_PG_UPDATE_STATE, operations that change the power partition
- * state are NOT reference counted
+ * @brief Control power-gating state of a partition.
*
* @cond (bpmp_t194 || bpmp_t186)
* @note On T194 and earlier BPMP-FW forcefully turns off some partitions as
@@ -1486,9 +1902,8 @@ struct mrq_query_abi_response {
* Therefore, it is recommended to power off all domains via MRQ_PG prior to SC7
* entry.
* See @ref bpmp_pdomain_ids for further detail.
- * @endcond (bpmp_t194 || bpmp_t186)
+ * @endcond
*
- * * Platforms: T186, T194
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_pg_request
@@ -1497,6 +1912,10 @@ struct mrq_query_abi_response {
* @addtogroup Powergating
* @{
*/
+
+/**
+ * @brief Sub-command identifiers for #MRQ_PG -command.
+ */
enum mrq_pg_cmd {
/**
* @brief Check whether the BPMP driver supports the specified
@@ -1512,9 +1931,14 @@ enum mrq_pg_cmd {
* possible values for power domains are defined in enum
* pg_states
*
- * mrq_response:err is
- * 0: Success
- * -#BPMP_EINVAL: Invalid request parameters
+ * mrq_response:err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------------------------------------ |
+ * | 0 | Request was successful. |
+ * | -#BPMP_EINVAL | Invalid request parameters were provided. |
+ * | -#BPMP_EACCES | Permission denied or always-off partition was attempted to be turned on. |
+ * | Any other <0 | Internal error while performing the operation. |
*/
CMD_PG_SET_STATE = 1,
@@ -1523,18 +1947,26 @@ enum mrq_pg_cmd {
* possible values for power domains are defined in enum
* pg_states
*
- * mrq_response:err is
- * 0: Success
- * -#BPMP_EINVAL: Invalid request parameters
+ * mrq_response:err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ---------------------------------------------- |
+ * | 0 | Request was successful. |
+ * | -#BPMP_EINVAL | Invalid request parameters were provided. |
+ * | Any other <0 | Internal error while performing the operation. |
*/
CMD_PG_GET_STATE = 2,
/**
* @brief Get the name string of specified power domain id.
*
- * mrq_response:err is
- * 0: Success
- * -#BPMP_EINVAL: Invalid request parameters
+ * mrq_response:err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ---------------------------------------------- |
+ * | 0 | Request was successful. |
+ * | -#BPMP_EINVAL | Invalid request parameters were provided. |
+ * | Any other <0 | Internal error while performing the operation. |
*/
CMD_PG_GET_NAME = 3,
@@ -1543,20 +1975,29 @@ enum mrq_pg_cmd {
* @brief Get the highest power domain id in the system. Not
* all IDs between 0 and max_id are valid IDs.
*
- * mrq_response:err is
- * 0: Success
- * -#BPMP_EINVAL: Invalid request parameters
+ * mrq_response:err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ---------------------------------------------- |
+ * | 0 | Request was successful. |
+ * | -#BPMP_EINVAL | Invalid request parameters were provided. |
+ * | Any other <0 | Internal error while performing the operation. |
*/
CMD_PG_GET_MAX_ID = 4,
};
#define MRQ_PG_NAME_MAXLEN 40
+/**
+ * @brief State value for the cmd_pg_set_state_request::state -field.
+ */
enum pg_states {
/** @brief Power domain is OFF */
PG_STATE_OFF = 0,
/** @brief Power domain is ON */
PG_STATE_ON = 1,
+
+ /** @cond bpmp_t186 */
/**
* @brief a legacy state where power domain and the clock
* associated to the domain are ON.
@@ -1564,40 +2005,51 @@ enum pg_states {
* deprecated.
*/
PG_STATE_RUNNING = 2,
+ /** @endcond */
};
struct cmd_pg_query_abi_request {
- /** @ref mrq_pg_cmd */
+ /** #MRQ_PG sub-command identifier from @ref mrq_pg_cmd */
uint32_t type;
} BPMP_ABI_PACKED;
struct cmd_pg_set_state_request {
- /** @ref pg_states */
+ /** One of the state values from @ref pg_states */
uint32_t state;
} BPMP_ABI_PACKED;
/**
- * @brief Response data to #MRQ_PG sub command #CMD_PG_GET_STATE
+ * @brief Response payload for the #MRQ_PG sub-command #CMD_PG_GET_STATE
*/
struct cmd_pg_get_state_response {
/**
* @brief The state of the power partition that has been
- * succesfuly requested by the master earlier using #MRQ_PG
+ * successfully requested by the master earlier using #MRQ_PG
* command #CMD_PG_SET_STATE.
*
* The state may not reflect the physical state of the power
* partition if there are some other masters requesting it to
* be enabled.
*
- * See @ref pg_states for possible values
+ * See @ref pg_states for possible values.
*/
uint32_t state;
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for the #MRQ_PG sub-command #CMD_PG_GET_NAME
+ */
struct cmd_pg_get_name_response {
+ /**
+ * @brief On successful response contains the null-terminated
+ * friendly name of the requested power-domain.
+ */
uint8_t name[MRQ_PG_NAME_MAXLEN];
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for the #MRQ_PG sub-command #CMD_PG_GET_MAX_ID
+ */
struct cmd_pg_get_max_id_response {
uint32_t max_id;
} BPMP_ABI_PACKED;
@@ -1606,22 +2058,28 @@ struct cmd_pg_get_max_id_response {
* @brief Request with #MRQ_PG
*
* Used by the sender of an #MRQ_PG message to control power
- * partitions. The pg_request is split into several sub-commands. Some
- * sub-commands require no additional data. Others have a sub-command
- * specific payload
+ * partitions. The expected payload depends on the sub-command identifier.
+ * Some sub-commands require no additional data while others have a sub-command
+ * specific payload:
*
- * |sub-command |payload |
- * |----------------------------|-----------------------|
- * |CMD_PG_QUERY_ABI | query_abi |
- * |CMD_PG_SET_STATE | set_state |
- * |CMD_PG_GET_STATE | - |
- * |CMD_PG_GET_NAME | - |
- * |CMD_PG_GET_MAX_ID | - |
+ * |Sub-command |Payload |
+ * |----------------------------|---------------------------|
+ * |#CMD_PG_QUERY_ABI | #cmd_pg_query_abi_request |
+ * |#CMD_PG_SET_STATE | #cmd_pg_set_state_request |
+ * |#CMD_PG_GET_STATE | - |
+ * |#CMD_PG_GET_NAME | - |
+ * |#CMD_PG_GET_MAX_ID | - |
*
*/
struct mrq_pg_request {
+ /** @brief Sub-command identifier from @ref mrq_pg_cmd. */
uint32_t cmd;
+
+ /**
+ * @brief Power-domain identifier
+ */
uint32_t id;
+
union {
struct cmd_pg_query_abi_request query_abi;
struct cmd_pg_set_state_request set_state;
@@ -1629,19 +2087,18 @@ struct mrq_pg_request {
} BPMP_ABI_PACKED;
/**
- * @brief Response to MRQ_PG
+ * @brief Response to #MRQ_PG
*
- * Each sub-command supported by @ref mrq_pg_request may return
- * sub-command-specific data. Some do and some do not as indicated in
- * the following table
+ * Some of the #MRQ_PG sub-commands return a sub-command -specific payload
+ * as specified in the following table:
*
- * |sub-command |payload |
- * |----------------------------|-----------------------|
- * |CMD_PG_QUERY_ABI | - |
- * |CMD_PG_SET_STATE | - |
- * |CMD_PG_GET_STATE | get_state |
- * |CMD_PG_GET_NAME | get_name |
- * |CMD_PG_GET_MAX_ID | get_max_id |
+ * |Sub-command |Payload |
+ * |--------------------|------------------------------|
+ * |#CMD_PG_QUERY_ABI | - |
+ * |#CMD_PG_SET_STATE | - |
+ * |#CMD_PG_GET_STATE | #cmd_pg_get_state_response |
+ * |#CMD_PG_GET_NAME | #cmd_pg_get_name_response |
+ * |#CMD_PG_GET_MAX_ID | #cmd_pg_get_max_id_response |
*/
struct mrq_pg_response {
union {
@@ -1658,11 +2115,10 @@ struct mrq_pg_response {
* @def MRQ_THERMAL
* @brief Interact with BPMP thermal framework
*
- * * Platforms: T186, T194
* * Initiators: Any
* * Targets: Any
- * * Request Payload: TODO
- * * Response Payload: TODO
+ * * Request Payload: #mrq_thermal_host_to_bpmp_request
+ * * Response Payload: #mrq_thermal_bpmp_to_host_response
*
* @addtogroup Thermal
*
@@ -1686,10 +2142,14 @@ struct mrq_pg_response {
* payload of @ref mrq_thermal_bpmp_to_host_request.
* @{
*/
+
+/**
+ * @brief Sub-command identifiers for Host->BPMP #MRQ_THERMAL -command.
+ */
enum mrq_thermal_host_to_bpmp_cmd {
/**
- * @brief Check whether the BPMP driver supports the specified
- * request type.
+ * @brief Check whether BPMP-FW supports the specified
+ * #MRQ_THERMAL sub-command.
*
* Host needs to supply request parameters.
*
@@ -1703,31 +2163,44 @@ enum mrq_thermal_host_to_bpmp_cmd {
*
* Host needs to supply request parameters.
*
- * mrq_response::err is
- * * 0: Temperature query succeeded.
- * * -#BPMP_EINVAL: Invalid request parameters.
- * * -#BPMP_ENOENT: No driver registered for thermal zone..
- * * -#BPMP_EFAULT: Problem reading temperature measurement.
+ * mrq_response::err value for this sub-command is:
+ *
+ * | Value | Description |
+ * | -------------- | ----------------------------------------- |
+ * | 0 | Temperature query succeeded. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_ENOENT | No driver registered for thermal zone. |
+ * | -#BPMP_EFAULT | Problem reading temperature measurement. |
*/
CMD_THERMAL_GET_TEMP = 1,
/**
+ * @cond (!bpmp_safe && !bpmp_t264)
* @brief Enable or disable and set the lower and upper
* thermal limits for a thermal trip point. Each zone has
* one trip point.
*
* Host needs to supply request parameters. Once the
* temperature hits a trip point, the BPMP will send a message
- * to the CPU having MRQ=MRQ_THERMAL and
- * type=CMD_THERMAL_HOST_TRIP_REACHED
+ * to the CPU having MRQ command identifier equal to #MRQ_THERMAL and
+ * sub-command identifier equal to #CMD_THERMAL_HOST_TRIP_REACHED.
*
- * mrq_response::err is
- * * 0: Trip successfully set.
- * * -#BPMP_EINVAL: Invalid request parameters.
- * * -#BPMP_ENOENT: No driver registered for thermal zone.
- * * -#BPMP_EFAULT: Problem setting trip point.
+ * If #CMD_THERMAL_SET_TRIP -sub-command is issued for a
+ * thermal zone that is currently power gated and unable to
+ * report temperature, a temperature of -256C is used as
+ * temperature for evaluation of the trip.
+ *
+ * mrq_response::err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * | --------------- | -------------------------------------- |
+ * | 0 | Trip successfully set. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_ENOENT | No driver registered for thermal zone. |
+ * | -#BPMP_EFAULT | Problem setting trip point. |
*/
CMD_THERMAL_SET_TRIP = 2,
+ /** @endcond */
/**
* @brief Get the number of supported thermal zones.
@@ -1739,135 +2212,153 @@ enum mrq_thermal_host_to_bpmp_cmd {
CMD_THERMAL_GET_NUM_ZONES = 3,
/**
- * @brief Get the thermtrip of the specified zone.
+ * @brief Get the thermal trip value of the specified zone.
*
* Host needs to supply request parameters.
*
- * mrq_response::err is
- * * 0: Valid zone information returned.
- * * -#BPMP_EINVAL: Invalid request parameters.
- * * -#BPMP_ENOENT: No driver registered for thermal zone.
- * * -#BPMP_ERANGE if thermtrip is invalid or disabled.
- * * -#BPMP_EFAULT: Problem reading zone information.
+ * mrq_response::err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * | --------------- | -------------------------------------- |
+ * | 0 | Valid zone information returned. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_ENOENT | No driver registered for thermal zone. |
+ * | -#BPMP_ERANGE | Thermal trip is invalid or disabled. |
+ * | -#BPMP_EFAULT | Problem reading zone information. |
*/
CMD_THERMAL_GET_THERMTRIP = 4,
- /** @brief: number of supported host-to-bpmp commands. May
- * increase in future
+ /**
+ * @brief Number of supported host-to-bpmp commands.
*/
CMD_THERMAL_HOST_TO_BPMP_NUM
};
+/**
+ * @brief Sub-command identifiers for BPMP->host #MRQ_THERMAL -command
+ */
enum mrq_thermal_bpmp_to_host_cmd {
/**
* @brief Indication that the temperature for a zone has
- * exceeded the range indicated in the thermal trip point
- * for the zone.
+ * exceeded the range indicated in the thermal trip point
+ * for the zone.
*
- * BPMP needs to supply request parameters. Host only needs to
+ * BPMP-FW needs to supply request parameters. Host only needs to
* acknowledge.
*/
CMD_THERMAL_HOST_TRIP_REACHED = 100,
- /** @brief: number of supported bpmp-to-host commands. May
- * increase in future
+ /**
+ * @brief: Number of supported bpmp-to-host commands. May
+ * increase in future.
*/
CMD_THERMAL_BPMP_TO_HOST_NUM
};
-/*
- * Host->BPMP request data for request type CMD_THERMAL_QUERY_ABI
- *
- * zone: Request type for which to check existence.
+/**
+ * Host->BPMP request payload for the #CMD_THERMAL_QUERY_ABI sub-command
*/
struct cmd_thermal_query_abi_request {
+ /**
+ * Request type for which to check whether supported by BPMP-FW.
+ *
+ * Valid identifiers are available at #mrq_thermal_host_to_bpmp_cmd
+ */
uint32_t type;
} BPMP_ABI_PACKED;
-/*
- * Host->BPMP request data for request type CMD_THERMAL_GET_TEMP
- *
- * zone: Number of thermal zone.
+/**
+ * Host->BPMP request payload for the #CMD_THERMAL_GET_TEMP sub-command
*/
struct cmd_thermal_get_temp_request {
+ /** Thermal zone identifier from @ref bpmp_thermal_ids. */
uint32_t zone;
} BPMP_ABI_PACKED;
-/*
- * BPMP->Host reply data for request CMD_THERMAL_GET_TEMP
+/**
+ * BPMP->Host response payload for the #CMD_THERMAL_GET_TEMP sub-command.
*
- * error: 0 if request succeeded.
- * -BPMP_EINVAL if request parameters were invalid.
- * -BPMP_ENOENT if no driver was registered for the specified thermal zone.
- * -BPMP_EFAULT for other thermal zone driver errors.
- * temp: Current temperature in millicelsius.
+ * mrq_response::err is defined as:
+ *
+ * | Value | Description |
+ * | ------------- | -------------------------------------------------------- |
+ * | 0 | Request succeeded. |
+ * | -#BPMP_EINVAL | Request parameters were invalid. |
+ * | -#BPMP_ENOENT | No driver was registered for the specified thermal zone. |
+ * | -#BPMP_EFAULT | For other BPMP-FW internal thermal zone driver errors. |
*/
struct cmd_thermal_get_temp_response {
+ /** @brief Current temperature in millicelsius. */
int32_t temp;
} BPMP_ABI_PACKED;
-/*
- * Host->BPMP request data for request type CMD_THERMAL_SET_TRIP
+/**
+ * @cond (!bpmp_safe && !bpmp_t264)
*
- * zone: Number of thermal zone.
- * low: Temperature of lower trip point in millicelsius
- * high: Temperature of upper trip point in millicelsius
- * enabled: 1 to enable trip point, 0 to disable trip point
+ * Host->BPMP request payload for the #CMD_THERMAL_SET_TRIP sub-command.
*/
struct cmd_thermal_set_trip_request {
+ /** @brief Thermal zone identifier from @ref bpmp_thermal_ids. */
uint32_t zone;
+ /** @brief Temperature of lower trip point in millicelsius */
int32_t low;
+ /** @brief Temperature of upper trip point in millicelsius */
int32_t high;
+ /** 1 to enable trip point, 0 to disable trip point */
uint32_t enabled;
} BPMP_ABI_PACKED;
-/*
- * BPMP->Host request data for request type CMD_THERMAL_HOST_TRIP_REACHED
- *
- * zone: Number of thermal zone where trip point was reached.
+/**
+ * BPMP->Host request payload for the #CMD_THERMAL_HOST_TRIP_REACHED sub-command.
*/
struct cmd_thermal_host_trip_reached_request {
+ /**
+ * @brief ID of the thermal zone where trip point was reached,
+ * from @ref bpmp_thermal_ids.
+ */
uint32_t zone;
} BPMP_ABI_PACKED;
+/** @endcond */
-/*
- * BPMP->Host reply data for request type CMD_THERMAL_GET_NUM_ZONES
- *
- * num: Number of supported thermal zones. The thermal zones are indexed
- * starting from zero.
+/**
+ * BPMP->Host response payload for the #CMD_THERMAL_GET_NUM_ZONES sub-command.
*/
struct cmd_thermal_get_num_zones_response {
+ /**
+ * @brief Number of supported thermal zones.
+ *
+ * The thermal zones are indexed starting from zero.
+ */
uint32_t num;
} BPMP_ABI_PACKED;
-/*
- * Host->BPMP request data for request type CMD_THERMAL_GET_THERMTRIP
- *
- * zone: Number of thermal zone.
+/**
+ * Host->BPMP request payload for the #CMD_THERMAL_GET_THERMTRIP sub-command.
*/
struct cmd_thermal_get_thermtrip_request {
+ /** @brief Thermal zone identifier from @ref bpmp_thermal_ids. */
uint32_t zone;
} BPMP_ABI_PACKED;
-/*
- * BPMP->Host reply data for request CMD_THERMAL_GET_THERMTRIP
- *
- * thermtrip: HW shutdown temperature in millicelsius.
+/**
+ * BPMP->Host response payload for the #CMD_THERMAL_GET_THERMTRIP sub-command.
*/
struct cmd_thermal_get_thermtrip_response {
+ /** @brief HW shutdown temperature in millicelsius. */
int32_t thermtrip;
} BPMP_ABI_PACKED;
-/*
- * Host->BPMP request data.
- *
- * Reply type is union mrq_thermal_bpmp_to_host_response.
+/**
+ * Host->BPMP #MRQ_THERMAL request payload.
*
- * type: Type of request. Values listed in enum mrq_thermal_type.
- * data: Request type specific parameters.
+ * Response payload type is #mrq_thermal_bpmp_to_host_response.
*/
struct mrq_thermal_host_to_bpmp_request {
+ /**
+ * Request sub-command identifier from @ref mrq_thermal_host_to_bpmp_cmd.
+ */
uint32_t type;
+
union {
struct cmd_thermal_query_abi_request query_abi;
struct cmd_thermal_get_temp_request get_temp;
@@ -1876,21 +2367,22 @@ struct mrq_thermal_host_to_bpmp_request {
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
-/*
- * BPMP->Host request data.
- *
- * type: Type of request. Values listed in enum mrq_thermal_type.
- * data: Request type specific parameters.
+/**
+ * @brief Request payload for the BPMP->Host #MRQ_THERMAL command.
*/
struct mrq_thermal_bpmp_to_host_request {
+ /**
+ * Request sub-command identifier from @ref mrq_thermal_bpmp_to_host_cmd.
+ */
uint32_t type;
+
union {
struct cmd_thermal_host_trip_reached_request host_trip_reached;
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
-/*
- * Data in reply to a Host->BPMP request.
+/**
+ * @brief Response payload for the Host->BPMP #MRQ_THERMAL command.
*/
union mrq_thermal_bpmp_to_host_response {
struct cmd_thermal_get_temp_response get_temp;
@@ -1900,13 +2392,11 @@ union mrq_thermal_bpmp_to_host_response {
/** @} Thermal */
-/**
+/** @cond (!bpmp_safe && (bpmp_t234 || bpmp_t238 || bpmp_t264))
* @ingroup MRQ_Codes
* @def MRQ_OC_STATUS
- * @brief Query over current status
+ * @brief Query overcurrent status
*
- * * Platforms: T234
- * @cond bpmp_t234
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: N/A
@@ -1916,33 +2406,224 @@ union mrq_thermal_bpmp_to_host_response {
* @{
*/
+/**
+ * @brief Size of the mrq_oc_status_response::throt_en and
+ * mrq_oc_status_response::event_cnt -arrays.
+ */
#define OC_STATUS_MAX_SIZE 24U
-/*
- * @brief Response to #MRQ_OC_STATUS
- *
- * throt_en: Value for each OC alarm where zero signifies throttle is
- * disabled, and non-zero throttle is enabled.
- * event_cnt: Total number of OC events for each OC alarm.
+/**
+ * @brief Response payload for the #MRQ_OC_STATUS -command.
*
* mrq_response::err is 0 if the operation was successful and
* -#BPMP_ENODEV otherwise.
*/
struct mrq_oc_status_response {
+ /**
+ * @brief Value for each overcurrent alarm where zero signifies
+ * throttle is disabled, and non-zero throttle is enabled.
+ */
uint8_t throt_en[OC_STATUS_MAX_SIZE];
+
+ /**
+ * @brief Total number of overcurrent events for each overcurrent alarm.
+ */
uint32_t event_cnt[OC_STATUS_MAX_SIZE];
} BPMP_ABI_PACKED;
/** @} OC_status */
-/** @endcond bpmp_t234 */
+/** @endcond */
+
+/** @cond (bpmp_th500 || bpmp_tb500 || bpmp_t238)
+ * @ingroup MRQ_Codes
+ * @def MRQ_THROTTLE
+ * @brief Overcurrent throttling
+ *
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_throttle_request
+ * * Response Payload: @ref mrq_throttle_response
+ * @addtogroup Throttle
+ * @{
+ */
+enum mrq_throttle_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_THROTTLE sub-command.
+ *
+ * mrq_response::err is 0 if the specified request is
+ * supported and -#BPMP_ENODEV otherwise.
+ */
+ CMD_THROTTLE_QUERY_ABI = 0,
+
+ /**
+ * @cond (bpmp_th500 || bpmp_tb500)
+ * @brief query chipthrot status
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|--------------------------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | CMD_THROTTLE_GET_CHIPTHROT_STATUS is not supported by BPMP-FW|
+ */
+ CMD_THROTTLE_GET_CHIPTHROT_STATUS = 1,
+ /** @endcond */
+
+ /**
+ * @cond bpmp_t238
+ * @brief program OC throttle configuration
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|--------------------------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_EINVAL | ID out of range or alarm for this ID not enabled at boot |
+ * | -#BPMP_ENODEV | CMD_THROTTLE_SET_OC_CONFIG is not supported by BPMP-FW |
+ */
+ CMD_THROTTLE_SET_OC_CONFIG = 2,
+ /** @endcond */
+};
/**
+ * @brief Request payload for #MRQ_THROTTLE sub-command #CMD_THROTTLE_QUERY_ABI
+ */
+struct cmd_throttle_query_abi_request {
+ uint32_t cmd; /**< @ref mrq_throttle_cmd */
+} BPMP_ABI_PACKED;
+
+/**
+ * @cond bpmp_th500
+ * @brief Response payload for #MRQ_THROTTLE sub-command
+ * #CMD_THROTTLE_GET_CHIPTHROT_STATUS
+ *
+ * Bit-mask of all h/w throttling actions that have been engaged since
+ * last invocation of this command
+ * Bit 0...11 : HW throttling status of the thermal zones.
+ * Bit 12...23 : Reserved for future thermal zone events.
+ * Bit 24...25 : HW throttling status of the Over current Alarms OC1 & OC2.
+ * Bit 26...31 : Reserved for future Over current alarm events.
+ * Bit 32...63 : Reserved for future use.
+ * @endcond
+ * @cond bpmp_tb500
+ * @brief Response payload for #MRQ_THROTTLE sub-command
+ * #CMD_THROTTLE_GET_CHIPTHROT_STATUS
+ *
+ * Bit-mask of all h/w throttling actions that have been engaged since
+ * last invocation of this command
+ * Bit 0 : HW throttling status of the TB500C_TJ_MAX thermal zone.
+ * Bit 1...63 : Reserved for future use.
+ * @endcond
+ * @cond (bpmp_th500 || bpmp_tb500)
+ */
+struct cmd_throttle_get_chipthrot_status_response {
+ uint64_t status;
+} BPMP_ABI_PACKED;
+/** @endcond */
+
+/**
+ * @cond bpmp_t238
+ * @brief Request payload for #MRQ_THROTTLE sub-command
+ * #CMD_THROTTLE_SET_OC_CONFIG
+ *
+ * Only alarms that have been configured as enabled in BPMP-DTB at boot can
+ * be reconfigured with this MRQ.
+ */
+struct cmd_throttle_set_oc_config_request {
+ /** @brief valid OC alarm ID from @ref bpmp_soctherm_edp_oc_ids */
+ uint32_t id;
+ /** @brief Throttling enable/disable
+ *
+ * Set to 1 to enable throttling, or 0 to disable. Other values are
+ * disallowed.
+ */
+ uint8_t en_throttle;
+} BPMP_ABI_PACKED;
+/** @endcond */
+
+/**
+ * @brief Request payload for the #MRQ_THROTTLE -command
+ *
+ * | Sub-command | Request payload |
+ * |------------------------------------|----------------------------------|
+ * | #CMD_THROTTLE_QUERY_ABI | #cmd_throttle_query_abi_request |
+ *
+ * @cond bpmp_th500
+ * The following additional sub-commands are supported on TH500 platforms:
+ * | Sub-command | Request payload |
+ * |------------------------------------|----------------------------------|
+ * | #CMD_THROTTLE_GET_CHIPTHROT_STATUS | - |
+ * @endcond
+ *
+ * @cond bpmp_tb500
+ * The following additional sub-commands are supported on TB500 platforms:
+ * | Sub-command | Request payload |
+ * |------------------------------------|----------------------------------|
+ * | #CMD_THROTTLE_GET_CHIPTHROT_STATUS | - |
+ * @endcond
+ *
+ * @cond bpmp_t238
+ * The following additional sub-commands are supported on T238 platforms:
+ * | Sub-command | Request payload |
+ * |------------------------------------|-------------------------------------|
+ * | #CMD_THROTTLE_SET_OC_CONFIG | #cmd_throttle_set_oc_config_request |
+ * @endcond
+ */
+struct mrq_throttle_request {
+ uint32_t cmd;
+ union {
+ struct cmd_throttle_query_abi_request throttle_query_abi_req;
+ /** @cond bpmp_t238 */
+ struct cmd_throttle_set_oc_config_request throttle_set_oc_config_req;
+ /** @endcond */
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for the #MRQ_THROTTLE -command.
+ *
+ * | Sub-command | Response payload |
+ * |------------------------------------|--------------------------------------------|
+ * | #CMD_THROTTLE_QUERY_ABI | - |
+ *
+ * @cond bpmp_th500
+ * The following additional sub-commands are supported on TH500 platforms:
+ * | Sub-command | Response payload |
+ * |------------------------------------|--------------------------------------------|
+ * | #CMD_THROTTLE_GET_CHIPTHROT_STATUS | #cmd_throttle_get_chipthrot_status_response|
+ * @endcond
+ *
+ * @cond bpmp_tb500
+ * The following additional sub-commands are supported on TB500 platforms:
+ * | Sub-command | Response payload |
+ * |------------------------------------|--------------------------------------------|
+ * | #CMD_THROTTLE_GET_CHIPTHROT_STATUS | #cmd_throttle_get_chipthrot_status_response|
+ * @endcond
+ *
+ * @cond bpmp_t238
+ * The following additional sub-commands are supported on T238 platforms:
+ * | Sub-command | Response payload |
+ * |------------------------------------|--------------------------------------------|
+ * | #CMD_THROTTLE_SET_OC_CONFIG | - |
+ * @endcond
+ */
+struct mrq_throttle_response {
+ union {
+ /** @cond (bpmp_th500 || bpmp_tb500) */
+ struct cmd_throttle_get_chipthrot_status_response throttle_get_chipthrot_status_resp;
+ /** @endcond */
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+/** @} Throttle */
+/** @endcond */
+
+
+/** @cond bpmp_t186
* @ingroup MRQ_Codes
* @def MRQ_CPU_VHINT
* @brief Query CPU voltage hint data
*
- * * Platforms: T186
- * @cond bpmp_t186
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_cpu_vhint_request
@@ -1995,14 +2676,13 @@ struct cpu_vhint_data {
} BPMP_ABI_PACKED;
/** @} Vhint */
-/** @endcond bpmp_t186 */
+/** @endcond */
/**
* @ingroup MRQ_Codes
* @def MRQ_ABI_RATCHET
* @brief ABI ratchet value query
*
- * * Platforms: T186, T194
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_abi_ratchet_request
@@ -2014,7 +2694,7 @@ struct cpu_vhint_data {
/**
* @brief An ABI compatibility mechanism
*
- * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future
+ * #BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future
* revision of this header file.
* 1. That future revision deprecates some MRQ
* 2. That future revision introduces a breaking change to an existing
@@ -2051,11 +2731,11 @@ struct mrq_abi_ratchet_request {
*
* If #ratchet is less than the requester's #BPMP_ABI_RATCHET_VALUE,
* the requster must either interoperate with BPMP according to an ABI
- * header version with BPMP_ABI_RATCHET_VALUE = ratchet or cease
+ * header version with #BPMP_ABI_RATCHET_VALUE = ratchet or cease
* communication with BPMP.
*
* If mrq_response::err is 0 and ratchet is greater than or equal to the
- * requester's BPMP_ABI_RATCHET_VALUE, the requester should continue
+ * requester's #BPMP_ABI_RATCHET_VALUE, the requester should continue
* normal operation.
*/
struct mrq_abi_ratchet_response {
@@ -2070,7 +2750,9 @@ struct mrq_abi_ratchet_response {
* @def MRQ_EMC_DVFS_LATENCY
* @brief Query frequency dependent EMC DVFS latency
*
- * * Platforms: T186, T194, T234
+ * On T264 and onwards, this MRQ service is available only when
+ * BPMP-FW has valid DRAM timing table passed by earlier boot stages.
+ *
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: N/A
@@ -2094,7 +2776,11 @@ struct emc_dvfs_latency {
* @brief Response to #MRQ_EMC_DVFS_LATENCY
*/
struct mrq_emc_dvfs_latency_response {
- /** @brief The number valid entries in #pairs */
+ /**
+ * @brief The number valid entries in #pairs
+ *
+ * Valid range is [0, #EMC_DVFS_LATENCY_MAX_SIZE]
+ */
uint32_t num_pairs;
/** @brief EMC DVFS node <frequency, latency> information */
struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE];
@@ -2102,13 +2788,11 @@ struct mrq_emc_dvfs_latency_response {
/** @} EMC */
-/**
+/** @cond (bpmp_t234)
* @ingroup MRQ_Codes
* @def MRQ_EMC_DVFS_EMCHUB
* @brief Query EMC HUB frequencies
*
- * * Platforms: T234 onwards
- * @cond (bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: N/A
@@ -2139,15 +2823,13 @@ struct mrq_emc_dvfs_emchub_response {
} BPMP_ABI_PACKED;
/** @} EMC */
-/** @endcond (bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+/** @cond (bpmp_t234)
* @ingroup MRQ_Codes
* @def MRQ_EMC_DISP_RFL
* @brief Set EMC display RFL handshake mode of operations
*
- * * Platforms: T234 onwards
- * @cond (bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_emc_disp_rfl_request
@@ -2157,6 +2839,9 @@ struct mrq_emc_dvfs_emchub_response {
* @{
*/
+/**
+ * @brief Allowed mode values for the mrq_emc_disp_rfl_request::mode -field.
+ */
enum mrq_emc_disp_rfl_mode {
/** @brief EMC display RFL handshake disabled */
EMC_DISP_RFL_MODE_DISABLED = 0,
@@ -2171,65 +2856,75 @@ enum mrq_emc_disp_rfl_mode {
* Used by the sender of an #MRQ_EMC_DISP_RFL message to
* request the mode of EMC display RFL handshake.
*
- * mrq_response::err is
- * * 0: RFL mode is set successfully
- * * -#BPMP_EINVAL: invalid mode requested
- * * -#BPMP_ENOSYS: RFL handshake is not supported
- * * -#BPMP_EACCES: Permission denied
- * * -#BPMP_ENODEV: if disp rfl mrq is not supported by BPMP-FW
+ * mrq_response::err for this request is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | --------------------------------------------- |
+ * | 0 | RFL mode is set successfully. |
+ * | -#BPMP_EINVAL | Invalid mode requested. |
+ * | -#BPMP_ENOSYS | RFL handshake is not supported. |
+ * | -#BPMP_EACCES | Permission denied. |
+ * | -#BPMP_ENODEV | if disp rfl mrq is not supported by BPMP-FW. |
*/
struct mrq_emc_disp_rfl_request {
- /** @brief EMC display RFL mode (@ref mrq_emc_disp_rfl_mode) */
+ /** @brief EMC display RFL mode from @ref mrq_emc_disp_rfl_mode */
uint32_t mode;
} BPMP_ABI_PACKED;
/** @} EMC */
-/** @endcond (bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+/** @cond (!bpmp_safe && (bpmp_t234 || bpmp_t238))
* @ingroup MRQ_Codes
* @def MRQ_BWMGR
- * @brief bwmgr requests
+ * @brief Bandwidth manager (BWMGR) commands
*
- * * Platforms: T234 onwards
- * @cond (bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_bwmgr_request
* * Response Payload: @ref mrq_bwmgr_response
*
* @addtogroup BWMGR
- *
* @{
*/
+/**
+ * @brief Sub-command identifiers for #MRQ_BWMGR
+ */
enum mrq_bwmgr_cmd {
/**
- * @brief Check whether the BPMP driver supports the specified
- * request type
+ * @brief Check whether BPMP-FW supports the specified
+ * #MRQ_BWMGR sub-command.
*
- * mrq_response::err is 0 if the specified request is
- * supported and -#BPMP_ENODEV otherwise.
+ * mrq_response::err is defined to be:
+ *
+ * | Value | Description
+ * |----------------|----------------------------
+ * | 0 | Specified sub-command is supported.
+ * | -#BPMP_ENODEV | Specified sub-command is not supported.
*/
CMD_BWMGR_QUERY_ABI = 0,
/**
- * @brief Determine dram rate to satisfy iso/niso bw requests
+ * @brief Determine DRAM rate to satisfy ISO/NISO bandwidth requests
*
- * mrq_response::err is
- * * 0: calc_rate succeeded.
- * * -#BPMP_EINVAL: Invalid request parameters.
- * * -#BPMP_ENOTSUP: Requested bw is not available.
+ * mrq_response::err is defined to be:
+ *
+ * | Value | Description
+ * |----------------|----------------------------
+ * | 0 | Rate calculation succeeded.
+ * | -#BPMP_EINVAL | Invalid request parameters.
+ * | -#BPMP_ENOTSUP | Requested bandwidth is not available.
+ * | <0 | Any other internal error.
*/
CMD_BWMGR_CALC_RATE = 1
};
-/*
- * request data for request type CMD_BWMGR_QUERY_ABI
- *
- * type: Request type for which to check existence.
+/**
+ * @brief Request payload for #MRQ_BWMGR sub-command #CMD_BWMGR_QUERY_ABI
*/
struct cmd_bwmgr_query_abi_request {
+ /** @brief Sub-command identifier from @ref mrq_bwmgr_cmd. */
uint32_t type;
} BPMP_ABI_PACKED;
@@ -2237,47 +2932,56 @@ struct cmd_bwmgr_query_abi_request {
* @brief Used by @ref cmd_bwmgr_calc_rate_request
*/
struct iso_req {
- /* @brief bwmgr client ID @ref bpmp_bwmgr_ids */
+ /** @brief BWMGR client ID from @ref bpmp_bwmgr_ids */
uint32_t id;
- /* @brief bw in kBps requested by client */
+ /** @brief Bandwidth in kBps requested by client */
uint32_t iso_bw;
} BPMP_ABI_PACKED;
+/**
+ * @brief Size of the cmd_bwmgr_calc_rate_request::isobw_reqs -array.
+ */
#define MAX_ISO_CLIENTS 13U
-/*
- * request data for request type CMD_BWMGR_CALC_RATE
+
+/**
+ * @brief Request payload for #MRQ_BWMGR sub-command #CMD_BWMGR_CALC_RATE
*/
struct cmd_bwmgr_calc_rate_request {
- /* @brief total bw in kBps requested by all niso clients */
+ /** @brief Total bandwidth in kBps requested by all NISO clients. */
uint32_t sum_niso_bw;
- /* @brief The number of iso clients */
+ /** @brief The number of ISO client requests in #isobw_reqs -array */
uint32_t num_iso_clients;
- /* @brief iso_req <id, iso_bw> information */
+ /** @brief iso_req <id, iso_bw> information */
struct iso_req isobw_reqs[MAX_ISO_CLIENTS];
} BPMP_ABI_PACKED;
-/*
- * response data for request type CMD_BWMGR_CALC_RATE
- *
- * iso_rate_min: min dram data clk rate in kHz to satisfy all iso bw reqs
- * total_rate_min: min dram data clk rate in kHz to satisfy all bw reqs
+/**
+ * @brief Response payload for #MRQ_BWMGR sub-command #CMD_BWMGR_CALC_RATE
*/
struct cmd_bwmgr_calc_rate_response {
+ /**
+ * @brief Minimum DRAM data clock rate in kHz to satisfy all ISO client
+ * bandwidth requests.
+ */
uint32_t iso_rate_min;
+
+ /**
+ * @brief Minimum DRAM data clock rate in kHz to satisfy all
+ * bandwidth requests.
+ */
uint32_t total_rate_min;
} BPMP_ABI_PACKED;
-/*
- * @brief Request with #MRQ_BWMGR
- *
- *
- * |sub-command |payload |
- * |----------------------------|------------------------------|
- * |CMD_BWMGR_QUERY_ABI | cmd_bwmgr_query_abi_request |
- * |CMD_BWMGR_CALC_RATE | cmd_bwmgr_calc_rate_request |
+/**
+ * @brief Request payload for the #MRQ_BWMGR -command.
*
+ * |Sub-command |Payload |
+ * |----------------------|-----------------------------|
+ * |#CMD_BWMGR_QUERY_ABI |#cmd_bwmgr_query_abi_request |
+ * |#CMD_BWMGR_CALC_RATE |#cmd_bwmgr_calc_rate_request |
*/
struct mrq_bwmgr_request {
+ /** @brief Sub-command identifier from @ref mrq_bwmgr_cmd. */
uint32_t cmd;
union {
struct cmd_bwmgr_query_abi_request query_abi;
@@ -2285,12 +2989,12 @@ struct mrq_bwmgr_request {
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
-/*
- * @brief Response to MRQ_BWMGR
+/**
+ * @brief Response payload for the #MRQ_BWMGR -command.
*
- * |sub-command |payload |
- * |----------------------------|------------------------------|
- * |CMD_BWMGR_CALC_RATE | cmd_bwmgr_calc_rate_response |
+ * |Sub-command |Payload |
+ * |----------------------|------------------------------|
+ * |#CMD_BWMGR_CALC_RATE |#cmd_bwmgr_calc_rate_response |
*/
struct mrq_bwmgr_response {
union {
@@ -2299,15 +3003,13 @@ struct mrq_bwmgr_response {
} BPMP_ABI_PACKED;
/** @} BWMGR */
-/** @endcond (bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+/** @cond (!bpmp_safe && (bpmp_t234 || bpmp_t238 || bpmp_t264))
* @ingroup MRQ_Codes
* @def MRQ_BWMGR_INT
- * @brief bpmp-integrated bwmgr requests
+ * @brief BPMP-FW integrated BWMGR requests
*
- * * Platforms: T234 onwards
- * @cond (bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_bwmgr_int_request
@@ -2317,10 +3019,13 @@ struct mrq_bwmgr_response {
* @{
*/
+/**
+ * @brief Sub-command identifiers for #MRQ_BWMGR_INT
+ */
enum mrq_bwmgr_int_cmd {
/**
* @brief Check whether the BPMP-FW supports the specified
- * request type
+ * sub-command.
*
* mrq_response::err is 0 if the specified request is
* supported and -#BPMP_ENODEV otherwise.
@@ -2328,36 +3033,64 @@ enum mrq_bwmgr_int_cmd {
CMD_BWMGR_INT_QUERY_ABI = 1,
/**
- * @brief Determine and set dram rate to satisfy iso/niso bw request
+ * @brief Determine and set DRAM rate to satisfy ISO/NISO bandwidth requests.
*
- * mrq_response::err is
- * * 0: request succeeded.
- * * -#BPMP_EINVAL: Invalid request parameters.
- * set_frequency in @ref cmd_bwmgr_int_calc_and_set_response
- * will not be set.
- * * -#BPMP_ENOTSUP: Requested bw is not available.
- * set_frequency in @ref cmd_bwmgr_int_calc_and_set_response
- * will be current dram-clk rate.
+ * mrq_response::err is defined as:
+ *
+ * |Value |Description |
+ * |-----------------|----------------------------------------------------------------------------------------------------------------|
+ * |0 |Request succeeded. |
+ * |-#BPMP_EINVAL |Invalid request parameters, cmd_bwmgr_int_calc_and_set_response::rate is not set. |
+ * |-#BPMP_ENOTSUP |Requested bandwidth is not available, cmd_bwmgr_int_calc_and_set_response::rate is the current DRAM clock rate. |
+ * |<0 |Any other internal error. |
*/
CMD_BWMGR_INT_CALC_AND_SET = 2,
/**
- * @brief Set a max DRAM frequency for the bandwidth-manager
+ * @brief Set a max DRAM frequency for the bandwidth manager.
*
- * mrq_response::err is
- * * 0: request succeeded.
- * * -#BPMP_ENOTSUP: Requested cap frequency is not possible.
+ * mrq_response::err is defined as:
+ *
+ * |Value |Description |
+ * |-----------------|------------------------------------------|
+ * |0 |Request succeeded. |
+ * |-#BPMP_ENOTSUP |Requested cap frequency is not possible. |
+ * |<0 |Any other internal error. |
+ */
+ CMD_BWMGR_INT_CAP_SET = 3,
+
+ /**
+ * @brief Obtain the maximum amount of bandwidth currently allocatable
+ * to the requesting client.
+ *
+ * mrq_response::err is defined as:
+ *
+ * |Value |Description |
+ * |-----------------|------------------------------------------|
+ * |0 |Request succeeded. |
+ * |-#BPMP_EINVAL |Invalid request parameters. |
+ * |<0 |Any other internal error. |
+ */
+ CMD_BWMGR_INT_CURR_AVAILABLE_BW = 4,
+ /**
+ * @brief Get the last request made by the client.
+ *
+ * mrq_response::err is defined as:
+ *
+ * |Value |Description |
+ * |-----------------|------------------------------------------|
+ * |0 |Request succeeded. |
+ * |-#BPMP_EINVAL |Invalid request parameters. |
+ * |<0 |Any other internal error. |
*/
- CMD_BWMGR_INT_CAP_SET = 3
+ CMD_BWMGR_INT_GET_LAST_REQUEST = 5,
};
-/*
- * request structure for request type CMD_BWMGR_QUERY_ABI
- *
- * type: Request type for which to check existence.
+/**
+ * @brief Request payload for #MRQ_BWMGR_INT sub-command #CMD_BWMGR_INT_QUERY_ABI
*/
struct cmd_bwmgr_int_query_abi_request {
- /* @brief request type determined by @ref mrq_bwmgr_int_cmd */
+ /** @brief Sub-command identifier from @ref mrq_bwmgr_int_cmd. */
uint32_t type;
} BPMP_ABI_PACKED;
@@ -2373,87 +3106,168 @@ struct cmd_bwmgr_int_query_abi_request {
/** @} bwmgr_int_unit_type */
-/*
- * request data for request type CMD_BWMGR_INT_CALC_AND_SET
+/**
+ * @brief Request payload for #MRQ_BWMGR_INT sub-command #CMD_BWMGR_INT_CALC_AND_SET
*/
struct cmd_bwmgr_int_calc_and_set_request {
- /* @brief bwmgr client ID @ref bpmp_bwmgr_ids */
+ /** @brief BWGMR client ID from @ref bpmp_bwmgr_ids */
uint32_t client_id;
- /* @brief average niso bw usage in kBps requested by client. */
+ /** @brief Average NISO bandwidth usage in kBps requested by client. */
uint32_t niso_bw;
- /*
- * @brief average iso bw usage in kBps requested by client.
- * Value is ignored if client is niso. Determined by client_id.
+ /**
+ * @brief Average ISO bandwidth usage in kBps requested by client.
+ *
+ * Value is ignored if client is NISO as determined by #client_id.
*/
uint32_t iso_bw;
- /*
- * @brief memory clock floor requested by client.
- * Unit determined by floor_unit.
+ /**
+ * @brief Memory clock floor requested by client, unit of the value
+ * is determined by #floor_unit -field.
*/
uint32_t mc_floor;
- /*
- * @brief toggle to determine the unit-type of floor value.
- * See @ref bwmgr_int_unit_type definitions for unit-type mappings.
+ /**
+ * @brief Value set to determine the unit of the #mc_floor value:
+ *
+ * | Value | Unit |
+ * |-----------------------|----------------------|
+ * | #BWMGR_INT_UNIT_KBPS | Kilobytes per second |
+ * | #BWMGR_INT_UNIT_KHZ | Kilohertz |
*/
uint8_t floor_unit;
} BPMP_ABI_PACKED;
-struct cmd_bwmgr_int_cap_set_request {
- /* @brief requested cap frequency in Hz. */
+/**
+ * @brief Response payload for #MRQ_BWMGR_INT sub-command #CMD_BWMGR_INT_CALC_AND_SET
+ */
+struct cmd_bwmgr_int_calc_and_set_response {
+ /** @brief Currently set memory clock frequency in Hz */
uint64_t rate;
} BPMP_ABI_PACKED;
-/*
- * response data for request type CMD_BWMGR_CALC_AND_SET
+/**
+ * @brief Request payload for #MRQ_BWMGR_INT sub-command #CMD_BWMGR_INT_CAP_SET
*/
-struct cmd_bwmgr_int_calc_and_set_response {
- /* @brief current set memory clock frequency in Hz */
+struct cmd_bwmgr_int_cap_set_request {
+ /** @brief Requested cap frequency in Hz. */
uint64_t rate;
} BPMP_ABI_PACKED;
-/*
- * @brief Request with #MRQ_BWMGR_INT
+/**
+ * @brief Request payload for #MRQ_BWMGR_INT sub-command #CMD_BWMGR_INT_CURR_AVAILABLE_BW
+ */
+struct cmd_bwmgr_int_curr_available_bw_request {
+ /** @brief BWMGR client ID from @ref bpmp_bwmgr_ids */
+ uint32_t id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for #MRQ_BWMGR_INT sub-command #CMD_BWMGR_INT_CURR_AVAILABLE_BW
+ */
+struct cmd_bwmgr_int_curr_available_bw_response {
+ /** @brief Current cap frequency in KHz. */
+ uint64_t cap_rate;
+ /** @brief Currently available bandwidth for the requesting client
+ * to allocate in KBps.
+ */
+ uint64_t available_bw;
+} BPMP_ABI_PACKED;
+
+struct cmd_bwmgr_int_get_last_request_request {
+ /** @brief BWMGR client ID from @ref bpmp_bwmgr_ids */
+ uint32_t id;
+ /**
+ * @brief Value set to determine the unit of the returned mc_floor value:
+ *
+ * | Value | Unit |
+ * |-----------------------|----------------------|
+ * | #BWMGR_INT_UNIT_KBPS | Kilobytes per second |
+ * | #BWMGR_INT_UNIT_KHZ | Kilohertz |
+ */
+ uint8_t floor_unit;
+} BPMP_ABI_PACKED;
+
+struct cmd_bwmgr_int_get_last_request_response {
+ /** @brief BWGMR client ID from @ref bpmp_bwmgr_ids */
+ uint32_t client_id;
+ /** @brief Average NISO bandwidth usage in kBps requested by client. */
+ uint32_t niso_bw;
+ /**
+ * @brief Average ISO bandwidth usage in kBps requested by client.
+ */
+ uint32_t iso_bw;
+ /**
+ * @brief Memory clock floor requested by client, unit of the value
+ * is determined by #floor_unit -field.
+ */
+ uint32_t mc_floor;
+ /**
+ * @brief Value set to determine the unit of the #mc_floor value:
+ *
+ * | Value | Unit |
+ * |-----------------------|----------------------|
+ * | #BWMGR_INT_UNIT_KBPS | Kilobytes per second |
+ * | #BWMGR_INT_UNIT_KHZ | Kilohertz |
+ */
+ uint8_t floor_unit;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_BWMGR_INT -command.
*
+ * |Sub-command |Payload |
+ * |---------------------------------|-----------------------------------------|
+ * |#CMD_BWMGR_INT_QUERY_ABI |#cmd_bwmgr_int_query_abi_request |
+ * |#CMD_BWMGR_INT_CALC_AND_SET |#cmd_bwmgr_int_calc_and_set_request |
+ * |#CMD_BWMGR_INT_CAP_SET |#cmd_bwmgr_int_cap_set_request |
+ * |#CMD_BWMGR_INT_GET_LAST_REQUEST |#cmd_bwmgr_int_get_last_request_request |
*
- * |sub-command |payload |
- * |----------------------------|-----------------------------------|
- * |CMD_BWMGR_INT_QUERY_ABI | cmd_bwmgr_int_query_abi_request |
- * |CMD_BWMGR_INT_CALC_AND_SET | cmd_bwmgr_int_calc_and_set_request|
- * |CMD_BWMGR_INT_CAP_SET | cmd_bwmgr_int_cap_set_request |
+ * The following additional sub-commands are supported on T264 platforms:
*
+ * |Sub-command |Payload |
+ * |---------------------------------|-----------------------------------------|
+ * |#CMD_BWMGR_INT_CURR_AVAILABLE_BW |#cmd_bwmgr_int_curr_available_bw_request |
*/
struct mrq_bwmgr_int_request {
+ /** @brief Sub-command identifier from @ref mrq_bwmgr_int_cmd. */
uint32_t cmd;
union {
struct cmd_bwmgr_int_query_abi_request query_abi;
struct cmd_bwmgr_int_calc_and_set_request bwmgr_calc_set_req;
struct cmd_bwmgr_int_cap_set_request bwmgr_cap_set_req;
+ struct cmd_bwmgr_int_curr_available_bw_request bwmgr_curr_available_bw_req;
+ struct cmd_bwmgr_int_get_last_request_request bwmgr_get_last_request_req;
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
-/*
- * @brief Response to MRQ_BWMGR_INT
+/**
+ * @brief Response payload for the #MRQ_BWMGR_INT -command.
*
- * |sub-command |payload |
- * |----------------------------|---------------------------------------|
- * |CMD_BWMGR_INT_CALC_AND_SET | cmd_bwmgr_int_calc_and_set_response |
+ * |Sub-command |Payload |
+ * |---------------------------------|------------------------------------------|
+ * |#CMD_BWMGR_INT_CALC_AND_SET |#cmd_bwmgr_int_calc_and_set_response |
+ * |#CMD_BWMGR_INT_GET_LAST_REQUEST |#cmd_bwmgr_int_get_last_request_response |
+ *
+ * The following additional sub-commands are supported on T264 platforms:
+ * |Sub-command |Payload |
+ * |---------------------------------|------------------------------------------|
+ * |#CMD_BWMGR_INT_CURR_AVAILABLE_BW |#cmd_bwmgr_int_curr_available_bw_response |
*/
struct mrq_bwmgr_int_response {
union {
struct cmd_bwmgr_int_calc_and_set_response bwmgr_calc_set_resp;
+ struct cmd_bwmgr_int_curr_available_bw_response bwmgr_curr_available_bw_resp;
+ struct cmd_bwmgr_int_get_last_request_response bwmgr_get_last_request_resp;
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
/** @} BWMGR_INT */
-/** @endcond (bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+/** @cond (!bpmp_safe && (bpmp_t234 || bpmp_t238 || bpmp_t264))
* @ingroup MRQ_Codes
* @def MRQ_ISO_CLIENT
* @brief ISO client requests
*
- * * Platforms: T234 onwards
- * @cond (bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_iso_client_request
@@ -2463,148 +3277,178 @@ struct mrq_bwmgr_int_response {
* @{
*/
+/**
+ * @brief Sub-command identifiers for #MRQ_ISO_CLIENT.
+ */
enum mrq_iso_client_cmd {
/**
- * @brief Check whether the BPMP driver supports the specified
- * request type
+ * @brief Check whether BPMP-FW supports a specified
+ * #MRQ_ISO_CLIENT sub-command.
*
* mrq_response::err is 0 if the specified request is
* supported and -#BPMP_ENODEV otherwise.
*/
CMD_ISO_CLIENT_QUERY_ABI = 0,
- /*
- * @brief check for legal LA for the iso client. Without programming
- * LA MC registers, calculate and ensure that legal LA is possible for
- * iso bw requested by the ISO client.
+ /**
+ * @brief Determine legal LA for ISO client.
*
- * mrq_response::err is
- * * 0: check la succeeded.
- * * -#BPMP_EINVAL: Invalid request parameters.
- * * -#BPMP_EFAULT: Legal LA is not possible for client requested iso_bw
+ * Without programming LA MC registers, calculate and ensure that
+ * a legal LA is possible for the ISO bandwidth requested by the
+ * ISO client.
+ *
+ * mrq_response::err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * |---------------|--------------------------------------------------------------|
+ * | 0 | Request successful and legal LA is possible. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_EFAULT | Legal LA is not possible for client requested ISO bandwidth. |
+ * | <0 | Any other internal error. |
*/
CMD_ISO_CLIENT_CALCULATE_LA = 1,
- /*
- * @brief set LA for the iso client. Calculate and program the LA/PTSA
- * MC registers corresponding to the client making bw request
+ /**
+ * @brief Set LA for ISO client.
*
- * mrq_response::err is
- * * 0: set la succeeded.
- * * -#BPMP_EINVAL: Invalid request parameters.
- * * -#BPMP_EFAULT: Failed to calculate or program MC registers.
+ * Calculate and program the LA/PTSA MC registers corresponding to the
+ * ISO client making the bandwidth request.
+ *
+ * mrq_response::err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * |---------------|----------------------------------------------|
+ * | 0 | Setting LA succeeded. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_EFAULT | Failed to calculate or program MC registers. |
+ * | <0 | Any other internal error. |
*/
CMD_ISO_CLIENT_SET_LA = 2,
- /*
- * @brief Get max possible bw for iso client
+ /**
+ * @brief Get maximum possible bandwidth for ISO client.
*
- * mrq_response::err is
- * * 0: get_max_bw succeeded.
- * * -#BPMP_EINVAL: Invalid request parameters.
+ * mrq_response::err for this sub-command is defined as:
+ *
+ * | Value | Description |
+ * |---------------|----------------------------------------------|
+ * | 0 | Operation successful. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | <0 | Any other internal error. |
*/
CMD_ISO_CLIENT_GET_MAX_BW = 3
};
-/*
- * request data for request type CMD_ISO_CLIENT_QUERY_ABI
- *
- * type: Request type for which to check existence.
+/**
+ * @brief Request payload for #MRQ_ISO_CLIENT sub-command #CMD_ISO_CLIENT_QUERY_ABI
*/
struct cmd_iso_client_query_abi_request {
+ /**
+ * @brief Sub-command identifier from @ref mrq_iso_client_cmd
+ * for which to check existence.
+ */
uint32_t type;
} BPMP_ABI_PACKED;
-/*
- * request data for request type CMD_ISO_CLIENT_CALCULATE_LA
- *
- * id: client ID in @ref bpmp_bwmgr_ids
- * bw: bw requested in kBps by client ID.
- * init_bw_floor: initial dram_bw_floor in kBps passed by client ID.
- * ISO client will perform mempool allocation and DVFS buffering based
- * on this dram_bw_floor.
+/**
+ * @brief Request payload #MRQ_ISO_CLIENT sub-command #CMD_ISO_CLIENT_CALCULATE_LA
*/
struct cmd_iso_client_calculate_la_request {
+ /** @brief BWMGR client ID from @ref bpmp_bwmgr_ids */
uint32_t id;
+ /** @brief Bandwidth requested in kBps for the client specified in #id. */
uint32_t bw;
+ /**
+ * @brief Initial DRAM bandwidth floor in kBps for the ISO client specified in #id.
+ *
+ * ISO client will perform mempool allocation and DVFS buffering based
+ * on this value.
+ */
uint32_t init_bw_floor;
} BPMP_ABI_PACKED;
-/*
- * request data for request type CMD_ISO_CLIENT_SET_LA
- *
- * id: client ID in @ref bpmp_bwmgr_ids
- * bw: bw requested in kBps by client ID.
- * final_bw_floor: final dram_bw_floor in kBps.
- * Sometimes the initial dram_bw_floor passed by ISO client may need to be
- * updated by considering higher dram freq's. This is the final dram_bw_floor
- * used to calculate and program MC registers.
+/**
+ * @brief Response payload for #MRQ_ISO_CLIENT sub-command #CMD_ISO_CLIENT_CALCULATE_LA
+ */
+struct cmd_iso_client_calculate_la_response {
+ /** @brief Minimum DRAM rate in kHz at which a legal LA is possible */
+ uint32_t la_rate_floor;
+ /**
+ * Minimum DRAM frequency in kHz required to satisfy this clients
+ * ISO bandwidth request, assuming all other ISO clients are inactive.
+ */
+ uint32_t iso_client_only_rate;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for #MRQ_ISO_CLIENT sub-command #CMD_ISO_CLIENT_SET_LA
*/
struct cmd_iso_client_set_la_request {
+ /** @brief BMWGR client ID from @ref bpmp_bwmgr_ids */
uint32_t id;
+ /** @brief Bandwidth requested in kBps for the client specified in #id. */
uint32_t bw;
+ /**
+ * @brief Final DRAM bandwidth floor in kBps.
+ *
+ * Sometimes the initial cmd_iso_client_calculate_la_request::dram_bw_floor
+ * passed by ISO client may need to be updated by considering higher
+ * DRAM frequencies. This is the final DRAM bandwidth floor value used
+ * to calculate and program MC registers.
+ */
uint32_t final_bw_floor;
} BPMP_ABI_PACKED;
-/*
- * request data for request type CMD_ISO_CLIENT_GET_MAX_BW
- *
- * id: client ID in @ref bpmp_bwmgr_ids
+/**
+ * @brief Request payload for #MRQ_ISO_CLIENT sub-command #CMD_ISO_CLIENT_GET_MAX_BW
*/
struct cmd_iso_client_get_max_bw_request {
+ /** @brief BWMGR client ID from @ref bpmp_bwmgr_ids */
uint32_t id;
} BPMP_ABI_PACKED;
-/*
- * response data for request type CMD_ISO_CLIENT_CALCULATE_LA
- *
- * la_rate_floor: minimum dram_rate_floor in kHz at which a legal la is possible
- * iso_client_only_rate: Minimum dram freq in kHz required to satisfy this clients
- * iso bw request, assuming all other iso clients are inactive
- */
-struct cmd_iso_client_calculate_la_response {
- uint32_t la_rate_floor;
- uint32_t iso_client_only_rate;
-} BPMP_ABI_PACKED;
-
/**
* @brief Used by @ref cmd_iso_client_get_max_bw_response
*/
struct iso_max_bw {
- /* @brief dram frequency in kHz */
+ /** @brief dram frequency in kHz */
uint32_t freq;
- /* @brief max possible iso-bw in kBps */
+ /** @brief max possible iso-bw in kBps */
uint32_t iso_bw;
} BPMP_ABI_PACKED;
+/**
+ * @brief Size of the cmd_iso_client_get_max_bw_response::pairs -array.
+ */
#define ISO_MAX_BW_MAX_SIZE 14U
-/*
- * response data for request type CMD_ISO_CLIENT_GET_MAX_BW
+
+/**
+ * @brief Response payload for #MRQ_ISO_CLIENT sub-command #CMD_ISO_CLIENT_GET_MAX_BW
*/
struct cmd_iso_client_get_max_bw_response {
- /* @brief The number valid entries in iso_max_bw pairs */
+ /** @brief The number valid entries in iso_max_bw pairs */
uint32_t num_pairs;
- /* @brief max ISOBW <dram freq, max bw> information */
+ /** @brief max ISOBW <dram freq, max bw> information */
struct iso_max_bw pairs[ISO_MAX_BW_MAX_SIZE];
} BPMP_ABI_PACKED;
/**
- * @brief Request with #MRQ_ISO_CLIENT
- *
- * Used by the sender of an #MRQ_ISO_CLIENT message.
+ * @brief Request payload for #MRQ_ISO_CLIENT command.
*
- * |sub-command |payload |
- * |------------------------------------ |----------------------------------------|
- * |CMD_ISO_CLIENT_QUERY_ABI |cmd_iso_client_query_abi_request |
- * |CMD_ISO_CLIENT_CALCULATE_LA |cmd_iso_client_calculate_la_request |
- * |CMD_ISO_CLIENT_SET_LA |cmd_iso_client_set_la_request |
- * |CMD_ISO_CLIENT_GET_MAX_BW |cmd_iso_client_get_max_bw_request |
+ * Each #MRQ_ISO_CLIENT -command is expected to include a sub-command specific
+ * payload as defined in table below:
*
+ * |Sub-command |Request payload |
+ * |-----------------------------|--------------------------------------|
+ * |#CMD_ISO_CLIENT_QUERY_ABI |#cmd_iso_client_query_abi_request |
+ * |#CMD_ISO_CLIENT_CALCULATE_LA |#cmd_iso_client_calculate_la_request |
+ * |#CMD_ISO_CLIENT_SET_LA |#cmd_iso_client_set_la_request |
+ * |#CMD_ISO_CLIENT_GET_MAX_BW |#cmd_iso_client_get_max_bw_request |
*/
-
struct mrq_iso_client_request {
- /* Type of request. Values listed in enum mrq_iso_client_cmd */
+ /** @brief Sub-command identifier from @ref mrq_iso_client_cmd. */
uint32_t cmd;
+
union {
struct cmd_iso_client_query_abi_request query_abi;
struct cmd_iso_client_calculate_la_request calculate_la_req;
@@ -2614,20 +3458,20 @@ struct mrq_iso_client_request {
} BPMP_ABI_PACKED;
/**
- * @brief Response to MRQ_ISO_CLIENT
+ * @brief Response payload for #MRQ_ISO_CLIENT command.
*
- * Each sub-command supported by @ref mrq_iso_client_request may return
- * sub-command-specific data. Some do and some do not as indicated in
- * the following table
+ * Some of the sub-commands supported by #MRQ_ISO_CLIENT may return
+ * a sub-command -specific payload in the MRQ response as defined in table
+ * below:
*
- * |sub-command |payload |
- * |---------------------------- |------------------------------------|
- * |CMD_ISO_CLIENT_CALCULATE_LA |cmd_iso_client_calculate_la_response|
- * |CMD_ISO_CLIENT_SET_LA |N/A |
- * |CMD_ISO_CLIENT_GET_MAX_BW |cmd_iso_client_get_max_bw_response |
+ * |Sub-command |Response payload |
+ * |---------------------------- |--------------------------------------|
+ * |#CMD_ISO_CLIENT_QUERY_ABI |- |
+ * |#CMD_ISO_CLIENT_CALCULATE_LA |#cmd_iso_client_calculate_la_response |
+ * |#CMD_ISO_CLIENT_SET_LA |- |
+ * |#CMD_ISO_CLIENT_GET_MAX_BW |#cmd_iso_client_get_max_bw_response |
*
*/
-
struct mrq_iso_client_response {
union {
struct cmd_iso_client_calculate_la_response calculate_la_resp;
@@ -2636,15 +3480,13 @@ struct mrq_iso_client_response {
} BPMP_ABI_PACKED;
/** @} ISO_CLIENT */
-/** @endcond (bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+/** @cond (!bpmp_t186)
* @ingroup MRQ_Codes
* @def MRQ_CPU_NDIV_LIMITS
- * @brief CPU freq. limits in ndiv
+ * @brief Return CPU cluster NDIV limits
*
- * * Platforms: T194 onwards
- * @cond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_cpu_ndiv_limits_request
@@ -2654,10 +3496,10 @@ struct mrq_iso_client_response {
*/
/**
- * @brief Request for ndiv limits of a cluster
+ * @brief Request payload for the #MRQ_CPU_NDIV_LIMITS -command
*/
struct mrq_cpu_ndiv_limits_request {
- /** @brief Enum cluster_id */
+ /** @brief Logical CPU cluster identifier */
uint32_t cluster_id;
} BPMP_ABI_PACKED;
@@ -2678,15 +3520,14 @@ struct mrq_cpu_ndiv_limits_response {
} BPMP_ABI_PACKED;
/** @} CPU */
-/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+
+/** @cond (bpmp_t194)
* @ingroup MRQ_Codes
* @def MRQ_CPU_AUTO_CC3
* @brief Query CPU cluster auto-CC3 configuration
*
- * * Platforms: T194
- * @cond bpmp_t194
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_cpu_auto_cc3_request
@@ -2702,15 +3543,15 @@ struct mrq_cpu_ndiv_limits_response {
*/
/**
- * @brief Request for auto-CC3 configuration of a cluster
+ * @brief Request payload for the #MRQ_CPU_AUTO_CC3 -command
*/
struct mrq_cpu_auto_cc3_request {
- /** @brief Enum cluster_id (logical cluster id, known to CCPLEX s/w) */
+ /** @brief Logical CPU cluster ID */
uint32_t cluster_id;
} BPMP_ABI_PACKED;
/**
- * @brief Response to #MRQ_CPU_AUTO_CC3
+ * @brief Response payload for the #MRQ_CPU_AUTO_CC3 -command
*/
struct mrq_cpu_auto_cc3_response {
/**
@@ -2724,9 +3565,9 @@ struct mrq_cpu_auto_cc3_response {
} BPMP_ABI_PACKED;
/** @} CC3 */
-/** @endcond bpmp_t194 */
+/** @endcond */
-/**
+/** @cond (bpmp_t186 || bpmp_t194 || bpmp_t234)
* @ingroup MRQ_Codes
* @def MRQ_RINGBUF_CONSOLE
* @brief A ring buffer debug console for BPMP
@@ -2811,7 +3652,9 @@ struct cmd_ringbuf_console_query_abi_resp {
*/
struct cmd_ringbuf_console_read_req {
/**
- * @brief Number of bytes requested to be read from the BPMP TX buffer
+ * @brief Number of bytes requested to be read from the BPMP TX buffer.
+ *
+ * Valid range is [0, #MRQ_RINGBUF_CONSOLE_MAX_READ_LEN]
*/
uint8_t len;
} BPMP_ABI_PACKED;
@@ -2823,7 +3666,11 @@ struct cmd_ringbuf_console_read_req {
struct cmd_ringbuf_console_read_resp {
/** @brief The actual data read from the BPMP TX buffer */
uint8_t data[MRQ_RINGBUF_CONSOLE_MAX_READ_LEN];
- /** @brief Number of bytes in cmd_ringbuf_console_read_resp::data */
+ /**
+ * @brief Number of bytes in cmd_ringbuf_console_read_resp::data
+ *
+ * Valid range is [0, #MRQ_RINGBUF_CONSOLE_MAX_WRITE_LEN]
+ */
uint8_t len;
} BPMP_ABI_PACKED;
@@ -2904,14 +3751,13 @@ union mrq_ringbuf_console_bpmp_to_host_response {
} BPMP_ABI_PACKED;
/** @} RingbufConsole */
+/** @endcond */
-/**
+/** @cond (!bpmp_t186 && !(bpmp_safe && bpmp_t234))
* @ingroup MRQ_Codes
* @def MRQ_STRAP
* @brief Set a strap value controlled by BPMP
*
- * * Platforms: T194 onwards
- * @cond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_strap_request
@@ -2925,10 +3771,14 @@ union mrq_ringbuf_console_bpmp_to_host_response {
* deasserted.
*
* BPMP owns registers which act as straps to various units. It
- * exposes limited control of those straps via #MRQ_STRAP.
+ * exposes limited control of those registers via #MRQ_STRAP.
*
* @{
*/
+
+/**
+ * @brief Sub-command identifiers for the #MRQ_STRAP -command.
+ */
enum mrq_strap_cmd {
/** @private */
STRAP_RESERVED = 0,
@@ -2937,27 +3787,31 @@ enum mrq_strap_cmd {
};
/**
- * @brief Request with #MRQ_STRAP
+ * @brief Request payload for the #MRQ_STRAP -command.
*/
struct mrq_strap_request {
- /** @brief @ref mrq_strap_cmd */
+ /** @brief Sub-command identifier from @ref mrq_strap_cmd */
uint32_t cmd;
- /** @brief Strap ID from @ref Strap_Identifiers */
+ /**
+ * @if (bpmp_t234 || bpmp_th500 || bpmp_t264)
+ * @brief Strap ID from @ref bpmp_strap_ids
+ * @else
+ * @brief Strap ID (undefined)
+ * @endif
+ */
uint32_t id;
- /** @brief Desired value for strap (if cmd is #STRAP_SET) */
+ /** @brief Desired value for strap (if #cmd is #STRAP_SET) */
uint32_t value;
} BPMP_ABI_PACKED;
/** @} Strap */
-/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+/** @cond (bpmp_t194 || bpmp_t234 || bpmp_th500)
* @ingroup MRQ_Codes
* @def MRQ_UPHY
* @brief Perform a UPHY operation
*
- * * Platforms: T194 onwards
- * @cond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_uphy_request
@@ -2966,52 +3820,124 @@ struct mrq_strap_request {
* @addtogroup UPHY
* @{
*/
-enum {
+
+/**
+ * @brief Sub-command identifiers for #MRQ_UPHY.
+ */
+enum mrq_uphy_cmd {
+ /** @brief Trigger PCIE lane margining procedure. */
CMD_UPHY_PCIE_LANE_MARGIN_CONTROL = 1,
+ /** @brief Return PCIE lane margining status. */
CMD_UPHY_PCIE_LANE_MARGIN_STATUS = 2,
+ /** @brief Initialize PCIE EP PLL controller. */
CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT = 3,
+ /** @brief Set state of the PCIE RP/EP controller. */
CMD_UPHY_PCIE_CONTROLLER_STATE = 4,
+ /** @brief Disable PCIE EP PLL controller. */
CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF = 5,
+
+ /**
+ * @cond bpmp_t238
+ * @brief Initialize and enable UPHY display port.
+ */
CMD_UPHY_DISPLAY_PORT_INIT = 6,
+ /** @brief Disable UPHY display port. */
CMD_UPHY_DISPLAY_PORT_OFF = 7,
+ /** @brief Trigger sequence to restore XUSB DYN lanes during SC7 exit. */
CMD_UPHY_XUSB_DYN_LANES_RESTORE = 8,
+ /** @endcond */
+
+ /**
+ * @cond bpmp_th500
+ * @brief Perform UPHY Lane EOM scan.
+ */
+ CMD_UPHY_LANE_EOM_SCAN = 9,
+ /** @brief Config PCIe VDM with a given BDF ID. */
+ CMD_UPHY_PCIE_CONFIG_VDM = 10,
+ /** @endcond */
+
CMD_UPHY_MAX,
};
+/**
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_PCIE_LANE_MARGIN_CONTROL.
+ */
struct cmd_uphy_margin_control_request {
- /** @brief Enable margin */
+ /**
+ * @brief Enable margin.
+ *
+ * Valid values:
+ * * Value 0 disables margin,
+ * * Value 1 enables margin.
+ */
int32_t en;
- /** @brief Clear the number of error and sections */
+ /**
+ * @brief Clear the number of error and sections.
+ *
+ * Valid values:
+ *
+ * * Value 0: Skip clear,
+ * * Value 1: Perform clear.
+ */
int32_t clr;
- /** @brief Set x offset (1's complement) for left/right margin type (y should be 0) */
+ /**
+ * @brief Set x offset (1's complement) for left/right margin type (y should be 0).
+ *
+ * Valid range is [0, 127]
+ */
uint32_t x;
- /** @brief Set y offset (1's complement) for left/right margin type (x should be 0) */
+ /**
+ * @brief Set y offset (1's complement) for left/right margin type (x should be 0)
+ *
+ * Valid range is [0, 63]
+ */
uint32_t y;
- /** @brief Set number of bit blocks for each margin section */
+ /**
+ * @brief Set number of bit blocks for each margin section.
+ *
+ * Valid range is [0, 15]
+ */
uint32_t nblks;
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_UPHY sub-command #CMD_UPHY_PCIE_LANE_MARGIN_STATUS.
+ */
struct cmd_uphy_margin_status_response {
/** @brief Number of errors observed */
uint32_t status;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT.
+ */
struct cmd_uphy_ep_controller_pll_init_request {
/** @brief EP controller number, T194 valid: 0, 4, 5; T234 valid: 5, 6, 7, 10; T238 valid: 0 */
uint8_t ep_controller;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_PCIE_CONTROLLER_STATE.
+ */
struct cmd_uphy_pcie_controller_state_request {
/** @brief PCIE controller number, T194 valid: 0-4; T234 valid: 0-10; T238 valid: 0-3 */
uint8_t pcie_controller;
+ /** @brief Nonzero value to enable controller, zero value to disable */
uint8_t enable;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF.
+ */
struct cmd_uphy_ep_controller_pll_off_request {
/** @brief EP controller number, T194 valid: 0, 4, 5; T234 valid: 5, 6, 7, 10; T238 valid: 0 */
uint8_t ep_controller;
} BPMP_ABI_PACKED;
+/**
+ * @cond bpmp_t238
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_DISPLAY_PORT_INIT.
+ */
struct cmd_uphy_display_port_init_request {
/** @brief DisplayPort link rate, T238 valid: 1620, 2700, 5400, 8100, 2160, 2430, 3240, 4320, 6750 */
uint16_t link_rate;
@@ -3019,37 +3945,90 @@ struct cmd_uphy_display_port_init_request {
uint16_t lanes_bitmap;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_XUSB_DYN_LANES_RESTORE.
+ */
struct cmd_uphy_xusb_dyn_lanes_restore_request {
/** @brief 1: lane 0; 2: lane 1; 3: lane 0 and 1 */
uint16_t lanes_bitmap;
} BPMP_ABI_PACKED;
+/** @endcond */
+
+/**
+ * @cond bpmp_th500
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_LANE_EOM_SCAN
+ */
+struct cmd_uphy_lane_eom_scan_request {
+ /** @brief UPHY brick number, valid: 0-5 */
+ uint32_t brick;
+ /** @brief UPHY lane number, valid: 0-15 for UPHY0-UPHY3, 0-1 for UPHY4-UPHY5 */
+ uint32_t lane;
+ /** @brief Perform EOM for PCIE GEN5 link: 1 for yes, 0 for no. */
+ uint32_t pcie_gen5;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for #MRQ_UPHY sub-command #CMD_UPHY_LANE_EOM_SCAN
+ */
+struct cmd_uphy_lane_eom_scan_response {
+ uint32_t data;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for #MRQ_UPHY sub-command #CMD_UPHY_PCIE_CONFIG_VDM
+ */
+struct cmd_uphy_pcie_config_vdm_request {
+ uint8_t pcie_controller;
+ /**
+ * @brief Bus/Dev/Func ID to be programmed for VDM.
+ *
+ * - bits[15..8] Bus
+ * - bits[7..3] Dev
+ * - bit [2..0] Func
+ */
+ uint16_t bdf;
+} BPMP_ABI_PACKED;
+/** @endcond */
/**
* @ingroup UPHY
- * @brief Request with #MRQ_UPHY
+ * @brief Request payload for the #MRQ_UPHY -command.
*
* Used by the sender of an #MRQ_UPHY message to control UPHY.
* The uphy_request is split into several sub-commands. CMD_UPHY_PCIE_LANE_MARGIN_STATUS
* requires no additional data. Others have a sub-command specific payload. Below table
* shows sub-commands with their corresponding payload data.
*
- * |sub-command |payload |
- * |------------------------------------ |----------------------------------------|
- * |CMD_UPHY_PCIE_LANE_MARGIN_CONTROL |uphy_set_margin_control |
- * |CMD_UPHY_PCIE_LANE_MARGIN_STATUS | |
- * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT |cmd_uphy_ep_controller_pll_init_request |
- * |CMD_UPHY_PCIE_CONTROLLER_STATE |cmd_uphy_pcie_controller_state_request |
- * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF |cmd_uphy_ep_controller_pll_off_request |
- * |CMD_UPHY_PCIE_DISPLAY_PORT_INIT |cmd_uphy_display_port_init_request |
- * |CMD_UPHY_PCIE_DISPLAY_PORT_OFF | |
- * |CMD_UPHY_XUSB_DYN_LANES_RESTORE |cmd_uphy_xusb_dyn_lanes_restore_request |
+ * |sub-command |payload |
+ * |--------------------------------------|-----------------------------------------|
+ * |#CMD_UPHY_PCIE_LANE_MARGIN_CONTROL |#cmd_uphy_margin_control_request |
+ * |#CMD_UPHY_PCIE_LANE_MARGIN_STATUS |- |
+ * |#CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT |#cmd_uphy_ep_controller_pll_init_request |
+ * |#CMD_UPHY_PCIE_CONTROLLER_STATE |#cmd_uphy_pcie_controller_state_request |
+ * |#CMD_UPHY_PCIE_EP_CONTROLLER_PLL_OFF |#cmd_uphy_ep_controller_pll_off_request |
+ *
+ * @cond bpmp_t238
+ * The following additional sub-commands are supported on T238 platforms:
+ *
+ * |sub-command |payload |
+ * |--------------------------------------|-----------------------------------------|
+ * |#CMD_UPHY_DISPLAY_PORT_INIT |#cmd_uphy_display_port_init_request |
+ * |#CMD_UPHY_DISPLAY_PORT_OFF |- |
+ * |#CMD_UPHY_XUSB_DYN_LANES_RESTORE |#cmd_uphy_xusb_dyn_lanes_restore_request |
+ * @endcond
*
+ * @cond bpmp_th500
+ * The following additional sub-commands are supported on TH500 platforms:
+ * |sub-command |payload |
+ * |--------------------------------------|-----------------------------------------|
+ * |#CMD_UPHY_LANE_EOM_SCAN |#cmd_uphy_lane_eom_scan_request |
+ * |#CMD_UPHY_PCIE_CONFIG_VDM |#cmd_uphy_pcie_config_vdm_request |
+ * @endcond
*/
-
struct mrq_uphy_request {
/** @brief Lane number. */
uint16_t lane;
- /** @brief Sub-command id. */
+ /** @brief Sub-command ID from @ref mrq_uphy_cmd. */
uint16_t cmd;
union {
@@ -3057,53 +4036,68 @@ struct mrq_uphy_request {
struct cmd_uphy_ep_controller_pll_init_request ep_ctrlr_pll_init;
struct cmd_uphy_pcie_controller_state_request controller_state;
struct cmd_uphy_ep_controller_pll_off_request ep_ctrlr_pll_off;
+ /** @cond bpmp_t238 */
struct cmd_uphy_display_port_init_request display_port_init;
struct cmd_uphy_xusb_dyn_lanes_restore_request xusb_dyn_lanes_restore;
+ /** @endcond */
+ /** @cond bpmp_th500 */
+ struct cmd_uphy_lane_eom_scan_request lane_eom_scan;
+ struct cmd_uphy_pcie_config_vdm_request pcie_vdm;
+ /** @endcond */
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
/**
* @ingroup UPHY
- * @brief Response to MRQ_UPHY
+ * @brief Response payload for the #MRQ_UPHY -command.
*
* Each sub-command supported by @ref mrq_uphy_request may return
* sub-command-specific data. Some do and some do not as indicated in
* the following table
*
- * |sub-command |payload |
- * |---------------------------- |------------------------|
- * |CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | |
- * |CMD_UPHY_PCIE_LANE_MARGIN_STATUS |uphy_get_margin_status |
+ * |sub-command |payload |
+ * |-----------------------------------|---------------------------------|
+ * |#CMD_UPHY_PCIE_LANE_MARGIN_CONTROL |- |
+ * |#CMD_UPHY_PCIE_LANE_MARGIN_STATUS |#cmd_uphy_margin_status_response |
*
+ * @cond bpmp_th500
+ * The following additional sub-commands are supported on TH500 platforms:
+ * |sub-command |payload |
+ * |-----------------------------------|---------------------------------|
+ * |#CMD_UPHY_LANE_EOM_SCAN |#cmd_uphy_lane_eom_scan_response |
+ * |#CMD_UPHY_PCIE_CONFIG_VDM |- |
+ * @endcond
*/
-
struct mrq_uphy_response {
union {
struct cmd_uphy_margin_status_response uphy_get_margin_status;
+ /** @cond bpmp_th500 */
+ struct cmd_uphy_lane_eom_scan_response eom_status;
+ /** @endcond */
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
/** @} UPHY */
-/** @endcond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500) */
+/** @endcond */
-/**
+/** @cond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_t264)
* @ingroup MRQ_Codes
* @def MRQ_FMON
- * @brief Perform a frequency monitor configuration operations
+ * @brief Perform a frequency monitor configuration operation
*
- * * Platforms: T194 onwards
- * @cond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500)
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_fmon_request
* * Response Payload: @ref mrq_fmon_response
- * @endcond (bpmp_t194 || bpmp_t234 || bpmp_t238 || bpmp_th500)
*
* @addtogroup FMON
* @{
- * @cond (bpmp_t194 || bpmp_t234)
*/
-enum {
+
+/**
+ * @brief Sub-command identifiers for #MRQ_FMON
+ */
+enum mrq_fmon_cmd {
/**
* @brief Clamp FMON configuration to specified rate.
*
@@ -3111,62 +4105,80 @@ enum {
* clamped, FMON configuration is preserved when clock rate
* and/or state is changed.
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_EACCES: FMON access error @n
- * -#BPMP_EBADCMD if subcommand is not supported @n
- * -#BPMP_EBADSLT: clamp FMON on cluster with auto-CC3 enabled @n
- * -#BPMP_EBUSY: fmon is already clamped at different rate @n
- * -#BPMP_EFAULT: self-diagnostic error @n
- * -#BPMP_EINVAL: invalid FMON configuration @n
- * -#BPMP_EOPNOTSUPP: not in production mode @n
- * -#BPMP_ENODEV: invalid clk_id @n
- * -#BPMP_ENOENT: no calibration data, uninitialized @n
- * -#BPMP_ENOTSUP: avfs config not set @n
- * -#BPMP_ENOSYS: clamp FMON on cluster clock w/ no NAFLL @n
- * -#BPMP_ETIMEDOUT: operation timed out @n
+ * mrq_response::err for this sub-command is defined to be:
+ *
+ * | Value | Description |
+ * |-------------------|---------------------------------------------------|
+ * | 0 | Operation was successful. |
+ * | -#BPMP_EBADCMD | Subcommand is not supported. |
+ * | -#BPMP_EACCES | FMON access error. |
+ * | -#BPMP_EBADSLT | Clamp FMON on cluster with auto-CC3 enabled. |
+ * | -#BPMP_EBUSY | FMON is already clamped at different rate. |
+ * | -#BPMP_EFAULT | Self-diagnostic error detected. |
+ * | -#BPMP_EINVAL | Invalid FMON configuration. |
+ * | -#BPMP_EOPNOTSUPP | Not in production mode. |
+ * | -#BPMP_ENODEV | Invalid clock ID in mrq_fmon_request::cmd_and_id. |
+ * | -#BPMP_ENOENT | No calibration data, uninitialized. |
+ * | -#BPMP_ENOTSUP | AVFS config not set. |
+ * | -#BPMP_ENOSYS | Clamp FMON on cluster clock w/ no NAFLL. |
+ * | -#BPMP_ETIMEDOUT | Operation timed out. |
*/
CMD_FMON_GEAR_CLAMP = 1,
+
/**
* @brief Release clamped FMON configuration.
*
* Allow FMON configuration to follow monitored clock rate
* and/or state changes.
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_EBADCMD if subcommand is not supported @n
- * -#BPMP_ENODEV: invalid clk_id @n
- * -#BPMP_ENOENT: no calibration data, uninitialized @n
- * -#BPMP_ENOTSUP: avfs config not set @n
- * -#BPMP_EOPNOTSUPP: not in production mode @n
+ * mrq_response::err for this sub-command is defined to be:
+ *
+ * | Value | Description |
+ * |-------------------|---------------------------------------------------|
+ * | 0 | Operation was successful. |
+ * | -#BPMP_EBADCMD | Subcommand is not supported. |
+ * | -#BPMP_ENODEV | Invalid clock ID in mrq_fmon_request::cmd_and_id. |
+ * | -#BPMP_ENOENT | No calibration data, uninitialized. |
+ * | -#BPMP_ENOTSUP | AVFS config not set. |
+ * | -#BPMP_EOPNOTSUPP | Not in production mode. |
*/
CMD_FMON_GEAR_FREE = 2,
+
/**
- * @brief Return rate FMON is clamped at, or 0 if FMON is not
- * clamped.
+ * @brief Return rate FMON is clamped at, or 0 if FMON is not clamped.
*
- * Inherently racy, since clamp state can be changed
- * concurrently. Useful for testing.
+ * Inherently racy, since clamp state can be changed concurrently,
+ * only provided and useful for testing purposes.
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_EBADCMD if subcommand is not supported @n
- * -#BPMP_ENODEV: invalid clk_id @n
- * -#BPMP_ENOENT: no calibration data, uninitialized @n
- * -#BPMP_ENOTSUP: avfs config not set @n
- * -#BPMP_EOPNOTSUPP: not in production mode @n
+ * mrq_response::err for this sub-command is defined to be:
+ *
+ * | Value | Description |
+ * |-------------------|---------------------------------------------------|
+ * | 0 | Operation was successful. |
+ * | -#BPMP_EBADCMD | Subcommand is not supported. |
+ * | -#BPMP_ENODEV | Invalid clock ID in mrq_fmon_request::cmd_and_id. |
+ * | -#BPMP_ENOENT | No calibration data, uninitialized. |
+ * | -#BPMP_ENOTSUP | AVFS config not set. |
+ * | -#BPMP_EOPNOTSUPP | Not in production mode. |
*/
CMD_FMON_GEAR_GET = 3,
+
/**
* @brief Return current status of FMON faults detected by FMON
- * h/w or s/w since last invocation of this command.
- * Clears fault status.
+ * HW or SW since last invocation of this sub-command.
+ * Clears fault status.
*
- * mrq_response::err is 0 if the operation was successful, or @n
- * -#BPMP_EBADCMD if subcommand is not supported @n
- * -#BPMP_EINVAL: invalid fault type @n
- * -#BPMP_ENODEV: invalid clk_id @n
- * -#BPMP_ENOENT: no calibration data, uninitialized @n
- * -#BPMP_ENOTSUP: avfs config not set @n
- * -#BPMP_EOPNOTSUPP: not in production mode @n
+ * mrq_response::err for this sub-command is defined to be:
+ *
+ * | Value | Description |
+ * |-------------------|---------------------------------------------------|
+ * | 0 | Operation was successful. |
+ * | -#BPMP_EBADCMD | Subcommand is not supported. |
+ * | -#BPMP_ENODEV | Invalid clock ID in mrq_fmon_request::cmd_and_id. |
+ * | -#BPMP_ENOENT | No calibration data, uninitialized. |
+ * | -#BPMP_ENOTSUP | AVFS config not set. |
+ * | -#BPMP_EOPNOTSUPP | Not in production mode. |
+ * | -#BPMP_EINVAL | Invalid fault type. |
*/
CMD_FMON_FAULT_STS_GET = 4,
};
@@ -3177,25 +4189,30 @@ enum {
*/
#define CMD_FMON_NUM 4
-/** @endcond DEPRECATED */
+/** @endcond */
/**
- * @defgroup fmon_fault_type FMON fault type
+ * @defgroup fmon_fault_type FMON fault types
* @addtogroup fmon_fault_type
* @{
*/
-/** @brief All detected FMON faults (h/w or s/w) */
+/** @brief All detected FMON faults (HW or SW) */
#define FMON_FAULT_TYPE_ALL 0U
-/** @brief FMON faults detected by h/w */
+/** @brief FMON faults detected by HW */
#define FMON_FAULT_TYPE_HW 1U
-/** @brief FMON faults detected by s/w */
+/** @brief FMON faults detected by SW */
#define FMON_FAULT_TYPE_SW 2U
/** @} fmon_fault_type */
-
+/**
+ * @brief Request payload for #MRQ_FMON sub-command #CMD_FMON_GEAR_CLAMP.
+ */
struct cmd_fmon_gear_clamp_request {
+ /** @brief Unused / reserved */
int32_t unused;
+
+ /** @brief Target rate in Hz. Valid range for the rate is [1, INT64_MAX] */
int64_t rate;
} BPMP_ABI_PACKED;
@@ -3219,40 +4236,63 @@ struct cmd_fmon_gear_get_request {
BPMP_ABI_EMPTY
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_FMON sub-command #CMD_FMON_GEAR_GET.
+ */
struct cmd_fmon_gear_get_response {
int64_t rate;
} BPMP_ABI_PACKED;
+/**
+ * @brief Request payload for #MRQ_FMON sub-command #CMD_FMON_FAULT_STS_GET
+ */
struct cmd_fmon_fault_sts_get_request {
- uint32_t fault_type; /**< @ref fmon_fault_type */
+ /**
+ * @brief Which fault types to return in response:
+ *
+ * | Value | Description |
+ * |----------------------|-----------------------------------------|
+ * | #FMON_FAULT_TYPE_ALL | Return all detected faults (HW and SW). |
+ * | #FMON_FAULT_TYPE_HW | Return only HW detected faults. |
+ * | #FMON_FAULT_TYPE_SW | Return only SW detected faults. |
+ */
+ uint32_t fault_type;
} BPMP_ABI_PACKED;
+/**
+ * @brief Response payload for #MRQ_FMON sub-command #CMD_FMON_FAULT_STS_GET
+ */
struct cmd_fmon_fault_sts_get_response {
+ /**
+ * Bitmask of detected HW / SW specific faults, or 0 if no faults have
+ * been detected since last invocation of #CMD_FMON_FAULT_STS_GET.
+ */
uint32_t fault_sts;
} BPMP_ABI_PACKED;
/**
* @ingroup FMON
- * @brief Request with #MRQ_FMON
+ * @brief Request payload for the #MRQ_FMON -command.
*
* Used by the sender of an #MRQ_FMON message to configure clock
* frequency monitors. The FMON request is split into several
- * sub-commands. Some sub-commands require no additional data.
- * Others have a sub-command specific payload
+ * sub-commands. Sub-command specific payloads are defined in
+ * the following table:
*
- * |sub-command |payload |
- * |----------------------------|-----------------------|
- * |CMD_FMON_GEAR_CLAMP |fmon_gear_clamp |
- * |CMD_FMON_GEAR_FREE |- |
- * |CMD_FMON_GEAR_GET |- |
- * |CMD_FMON_FAULT_STS_GET |fmon_fault_sts_get |
+ * |Sub-command |Payload |
+ * |------------------------|--------------------------------|
+ * |#CMD_FMON_GEAR_CLAMP |#cmd_fmon_gear_clamp_request |
+ * |#CMD_FMON_GEAR_FREE |- |
+ * |#CMD_FMON_GEAR_GET |- |
+ * |#CMD_FMON_FAULT_STS_GET |#cmd_fmon_fault_sts_get_request |
*
*/
struct mrq_fmon_request {
- /** @brief Sub-command and clock id concatenated to 32-bit word.
- * - bits[31..24] is the sub-cmd.
- * - bits[23..0] is monitored clock id used to select target
- * FMON
+ /**
+ * @brief Sub-command and clock id concatenated to 32-bit word.
+ *
+ * - bits[31..24] -> Sub-command identifier from @ref mrq_fmon_cmd.
+ * - bits[23..0] -> Monitored clock identifier used to select target FMON.
*/
uint32_t cmd_and_id;
@@ -3268,20 +4308,19 @@ struct mrq_fmon_request {
/**
* @ingroup FMON
- * @brief Response to MRQ_FMON
+ * @brief Response payload for the #MRQ_FMON -command.
*
* Each sub-command supported by @ref mrq_fmon_request may
* return sub-command-specific data as indicated below.
*
- * |sub-command |payload |
- * |----------------------------|------------------------|
- * |CMD_FMON_GEAR_CLAMP |- |
- * |CMD_FMON_GEAR_FREE |- |
- * |CMD_FMON_GEAR_GET |fmon_gear_get |
- * |CMD_FMON_FAULT_STS_GET |fmon_fault_sts_get |
+ * |Sub-command |Payload |
+ * |------------------------|---------------------------------|
+ * |#CMD_FMON_GEAR_CLAMP |- |
+ * |#CMD_FMON_GEAR_FREE |- |
+ * |#CMD_FMON_GEAR_GET |#cmd_fmon_gear_get_response |
+ * |#CMD_FMON_FAULT_STS_GET |#cmd_fmon_fault_sts_get_response |
*
*/
-
struct mrq_fmon_response {
union {
/** @private */
@@ -3293,17 +4332,15 @@ struct mrq_fmon_response {
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
-/** @endcond (bpmp_t194 || bpmp_t234) */
/** @} FMON */
+/** @endcond */
-/**
+/** @cond (bpmp_t194)
* @ingroup MRQ_Codes
* @def MRQ_EC
* @brief Provide status information on faults reported by Error
* Collator (EC) to HSM.
*
- * * Platforms: T194
- * @cond bpmp_t194
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: @ref mrq_ec_request
@@ -3311,10 +4348,8 @@ struct mrq_fmon_response {
*
* @note This MRQ ABI is under construction, and subject to change
*
- * @endcond bpmp_t194
* @addtogroup EC
* @{
- * @cond bpmp_t194
*/
enum {
/**
@@ -3325,7 +4360,7 @@ enum {
* -#BPMP_ENODEV if target EC is not owned by BPMP @n
* -#BPMP_EACCES if target EC power domain is turned off @n
* -#BPMP_EBADCMD if subcommand is not supported
- * @endcond DEPRECATED
+ * @endcond
*/
CMD_EC_STATUS_GET = 1, /* deprecated */
@@ -3572,7 +4607,7 @@ struct cmd_ec_status_get_response {
/** @brief EC error descriptors */
union ec_err_desc error_descs[EC_ERR_STATUS_DESC_MAX_NUM];
} BPMP_ABI_PACKED;
-/** @endcond DEPRECATED */
+/** @endcond */
struct cmd_ec_status_ex_get_response {
/** @brief Target EC id (the same id received with request). */
@@ -3610,7 +4645,7 @@ struct cmd_ec_status_ex_get_response {
* |sub-command |payload |
* |----------------------------|-----------------------|
* |@ref CMD_EC_STATUS_GET |ec_status_get |
- * @endcond DEPRECATED
+ * @endcond
*
* |sub-command |payload |
* |----------------------------|-----------------------|
@@ -3638,7 +4673,7 @@ struct mrq_ec_request {
* |sub-command |payload |
* |----------------------------|------------------------|
* |@ref CMD_EC_STATUS_GET |ec_status_get |
- * @endcond DEPRECATED
+ * @endcond
*
* |sub-command |payload |
* |----------------------------|------------------------|
@@ -3652,22 +4687,20 @@ struct mrq_ec_response {
* @cond DEPRECATED
*/
struct cmd_ec_status_get_response ec_status_get;
- /** @endcond DEPRECATED */
+ /** @endcond */
struct cmd_ec_status_ex_get_response ec_status_ex_get;
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
-/** @endcond bpmp_t194 */
/** @} EC */
+/** @endcond */
-/**
+/** @cond (bpmp_th500)
* @ingroup MRQ_Codes
* @def MRQ_TELEMETRY
* @brief Get address of memory buffer refreshed with recently sampled
* telemetry data
*
- * * Platforms: TH500 onwards
- * @cond bpmp_th500
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: N/A
@@ -3677,14 +4710,17 @@ struct mrq_ec_response {
*/
/**
- * @brief Response to #MRQ_TELEMETRY
+ * @brief Response payload for the #MRQ_TELEMETRY -command
*
- * mrq_response::err is
- * * 0: Telemetry data is available at returned address
- * * -#BPMP_EACCES: MRQ master is not allowed to request buffer refresh
- * * -#BPMP_ENAVAIL: Telemetry buffer cannot be refreshed via this MRQ channel
- * * -#BPMP_ENOTSUP: Telemetry buffer is not supported by BPMP-FW
- * * -#BPMP_ENODEV: Telemetry mrq is not supported by BPMP-FW
+ * mrq_response::err is defined as:
+ *
+ * | Value | Description |
+ * |-----------------|------------------------------------------------------------|
+ * | 0 | Telemetry data is available at returned address. |
+ * | -#BPMP_EACCES | MRQ master is not allowed to request buffer refresh. |
+ * | -#BPMP_ENAVAIL | Telemetry buffer cannot be refreshed via this MRQ channel. |
+ * | -#BPMP_ENOTSUP | Telemetry buffer is not supported by BPMP-FW. |
+ * | -#BPMP_ENODEV | Telemetry MRQ is not supported by BPMP-FW. |
*/
struct mrq_telemetry_response {
/** @brief Physical address of telemetry data buffer */
@@ -3692,15 +4728,112 @@ struct mrq_telemetry_response {
} BPMP_ABI_PACKED;
/** @} Telemetry */
-/** @endcond bpmp_th500 */
+/** @endcond */
+
+/** @cond (bpmp_tb500)
+ * @ingroup MRQ_Codes
+ * @def MRQ_TELEMETRY_EX
+ * @brief Get telemetry configuration settings.
+ *
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_telemetry_ex_request
+ * * Response Payload: @ref mrq_telemetry_ex_response
+ *
+ * @addtogroup Telemetry_ex
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_TELEMETRY_EX.
+ */
+enum mrq_telemetry_ex_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_TELEMETRY_EX sub-command.
+ *
+ * mrq_response::err is 0 if the specified request is
+ * supported and -#BPMP_ENODEV otherwise.
+ */
+ CMD_TELEMETRY_EX_QUERY_ABI = 0,
+
+ /**
+ * @brief Get telemetry buffer base address and data size
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|------------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_TELEMETRY_EX is not supported by BPMP-FW. |
+ */
+ CMD_TELEMETRY_EX_BASE_SZ_GET = 1,
+};
/**
+ * @brief Request data for #MRQ_TELEMETRY_EX sub-command
+ * #CMD_TELEMETRY_EX_QUERY_ABI
+ */
+struct cmd_telemetry_ex_query_abi_request {
+ /** @brief Sub-command identifier from @ref mrq_telemetry_ex_cmd */
+ uint32_t cmd_code;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for #MRQ_TELEMETRY_EX sub-command
+ * #CMD_TELEMETRY_EX_BASE_SZ_GET
+ */
+struct cmd_telemetry_ex_base_sz_get_response {
+ /**
+ * @brief Physical address of telemetry data buffer
+ *
+ * 0 if no buffer is allocated for the initiator sending MRQ.
+ */
+ uint64_t buf_base_addr;
+ /** @brief Telemetry data size in bytes */
+ uint32_t buf_size;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_TELEMETRY_EX -command
+ *
+ * | Sub-command | Request payload |
+ * |-------------------------------|----------------------------------------|
+ * | #CMD_TELEMETRY_EX_QUERY_ABI | #cmd_telemetry_ex_query_abi_request |
+ * | #CMD_TELEMETRY_EX_BASE_SZ_GET | - |
+ */
+struct mrq_telemetry_ex_request {
+ /** @brief Sub-command ID from @ref mrq_telemetry_ex_cmd. */
+ uint32_t cmd;
+ union {
+ struct cmd_telemetry_ex_query_abi_request
+ telemetry_ex_query_abi_req;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for the #MRQ_TELEMETRY_EX -command.
+ *
+ * | Sub-command | Response payload |
+ * |-------------------------------|----------------------------------------|
+ * | #CMD_TELEMETRY_EX_QUERY_ABI | - |
+ * | #CMD_TELEMETRY_EX_BASE_SZ_GET | #cmd_telemetry_ex_base_sz_get_response |
+ */
+struct mrq_telemetry_ex_response {
+ union {
+ struct cmd_telemetry_ex_base_sz_get_response
+ telemetry_ex_base_sz_get_rsp;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} Telemetry_ex */
+/** @endcond */
+
+/** @cond (bpmp_th500 || bpmp_tb500)
* @ingroup MRQ_Codes
* @def MRQ_PWR_LIMIT
* @brief Control power limits.
*
- * * Platforms: TH500 onwards
- * @cond bpmp_th500
* * Initiators: Any
* * Targets: BPMP
* * Request Payload: @ref mrq_pwr_limit_request
@@ -3709,10 +4842,14 @@ struct mrq_telemetry_response {
* @addtogroup Pwrlimit
* @{
*/
+
+/**
+ * @brief Sub-command identifiers for #MRQ_PWR_LIMIT.
+ */
enum mrq_pwr_limit_cmd {
/**
* @brief Check whether the BPMP-FW supports the specified
- * command
+ * #MRQ_PWR_LIMIT sub-command.
*
* mrq_response::err is 0 if the specified request is
* supported and -#BPMP_ENODEV otherwise.
@@ -3722,31 +4859,43 @@ enum mrq_pwr_limit_cmd {
/**
* @brief Set power limit
*
- * mrq_response:err is
- * * 0: Success
- * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW
- * * -#BPMP_ENAVAIL: Invalid request parameters
- * * -#BPMP_EACCES: Request is not accepted
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_PWR_LIMIT is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_EACCES | Request is not accepted. |
*/
CMD_PWR_LIMIT_SET = 1,
/**
* @brief Get power limit setting
*
- * mrq_response:err is
- * * 0: Success
- * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW
- * * -#BPMP_ENAVAIL: Invalid request parameters
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_PWR_LIMIT is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
*/
CMD_PWR_LIMIT_GET = 2,
/**
- * @brief Get current power cap
+ * @brief Get current aggregated power cap
*
- * mrq_response:err is
- * * 0: Success
- * * -#BPMP_ENODEV: Pwr limit mrq is not supported by BPMP-FW
- * * -#BPMP_ENAVAIL: Invalid request parameters
+ * Get currently applied power cap for the specified limit id
+ * aggregated across all limit sources and types.
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_PWR_LIMIT is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
*/
CMD_PWR_LIMIT_CURR_CAP = 3,
};
@@ -3761,7 +4910,7 @@ enum mrq_pwr_limit_cmd {
#define PWR_LIMIT_TYPE_BOUND_MAX 1U
/** @brief Limit value specifies minimum possible target cap */
#define PWR_LIMIT_TYPE_BOUND_MIN 2U
-/** @brief Number of limit types supported by mrq interface */
+/** @brief Number of limit types supported by #MRQ_PWR_LIMIT command */
#define PWR_LIMIT_TYPE_NUM 3U
/** @} bpmp_pwr_limit_type */
@@ -3770,7 +4919,8 @@ enum mrq_pwr_limit_cmd {
* @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_QUERY_ABI
*/
struct cmd_pwr_limit_query_abi_request {
- uint32_t cmd_code; /**< @ref mrq_pwr_limit_cmd */
+ /** @brief Sub-command identifier from @ref mrq_pwr_limit_cmd */
+ uint32_t cmd_code;
} BPMP_ABI_PACKED;
/**
@@ -3782,56 +4932,66 @@ struct cmd_pwr_limit_query_abi_request {
* is ignored by the arbitration (i.e., indicates "no limit set").
*/
struct cmd_pwr_limit_set_request {
- uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */
+ /** @brief Power limit identifier from @ref bpmp_pwr_limit_id */
+ uint32_t limit_id;
+ /** @brief Power limit source identifier from @ref bpmp_pwr_limit_src */
uint32_t limit_src; /**< @ref bpmp_pwr_limit_src */
- uint32_t limit_type; /**< @ref bpmp_pwr_limit_type */
+ /** @brief Power limit type from @ref bpmp_pwr_limit_type */
+ uint32_t limit_type;
+ /** @brief New power limit value */
uint32_t limit_setting;
} BPMP_ABI_PACKED;
/**
- * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_GET
+ * @brief Request payload for #MRQ_PWR_LIMIT sub-command #CMD_PWR_LIMIT_GET
*
* Get previously set from specified source specified limit value of specified
* type.
*/
struct cmd_pwr_limit_get_request {
- uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */
+ /** @brief Power limit identifier from @ref bpmp_pwr_limit_id */
+ uint32_t limit_id;
+ /** @brief Power limit source identifier from @ref bpmp_pwr_limit_src */
uint32_t limit_src; /**< @ref bpmp_pwr_limit_src */
- uint32_t limit_type; /**< @ref bpmp_pwr_limit_type */
+ /** @brief Power limit type from @ref bpmp_pwr_limit_type */
+ uint32_t limit_type;
} BPMP_ABI_PACKED;
/**
- * @brief Response data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_GET
+ * @brief Response payload for #MRQ_PWR_LIMIT sub-command #CMD_PWR_LIMIT_GET
*/
struct cmd_pwr_limit_get_response {
+ /** @brief Power limit value */
uint32_t limit_setting;
} BPMP_ABI_PACKED;
/**
- * @brief Request data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_CURR_CAP
+ * @brief Request payload for #MRQ_PWR_LIMIT sub-command #CMD_PWR_LIMIT_CURR_CAP
*
* For specified limit get current power cap aggregated from all sources.
*/
struct cmd_pwr_limit_curr_cap_request {
- uint32_t limit_id; /**< @ref bpmp_pwr_limit_id */
+ /** @brief Power limit identifier from @ref bpmp_pwr_limit_id */
+ uint32_t limit_id;
} BPMP_ABI_PACKED;
/**
- * @brief Response data for #MRQ_PWR_LIMIT command CMD_PWR_LIMIT_CURR_CAP
+ * @brief Response payload for #MRQ_PWR_LIMIT sub-command #CMD_PWR_LIMIT_CURR_CAP
*/
struct cmd_pwr_limit_curr_cap_response {
+ /** @brief Current power cap value */
uint32_t curr_cap;
} BPMP_ABI_PACKED;
/**
- * @brief Request with #MRQ_PWR_LIMIT
+ * @brief Request payload for the #MRQ_PWR_LIMIT -command
*
- * |sub-command |payload |
- * |----------------------------|---------------------------------|
- * |CMD_PWR_LIMIT_QUERY_ABI | cmd_pwr_limit_query_abi_request |
- * |CMD_PWR_LIMIT_SET | cmd_pwr_limit_set_request |
- * |CMD_PWR_LIMIT_GET | cmd_pwr_limit_get_request |
- * |CMD_PWR_LIMIT_CURR_CAP | cmd_pwr_limit_curr_cap_request |
+ * | Sub-command | Request payload |
+ * |--------------------------|----------------------------------|
+ * | #CMD_PWR_LIMIT_QUERY_ABI | #cmd_pwr_limit_query_abi_request |
+ * | #CMD_PWR_LIMIT_SET | #cmd_pwr_limit_set_request |
+ * | #CMD_PWR_LIMIT_GET | #cmd_pwr_limit_get_request |
+ * | #CMD_PWR_LIMIT_CURR_CAP | #cmd_pwr_limit_curr_cap_request |
*/
struct mrq_pwr_limit_request {
uint32_t cmd;
@@ -3844,14 +5004,14 @@ struct mrq_pwr_limit_request {
} BPMP_ABI_PACKED;
/**
- * @brief Response to MRQ_PWR_LIMIT
+ * @brief Response payload for the #MRQ_PWR_LIMIT -command.
*
- * |sub-command |payload |
- * |----------------------------|---------------------------------|
- * |CMD_PWR_LIMIT_QUERY_ABI | - |
- * |CMD_PWR_LIMIT_SET | - |
- * |CMD_PWR_LIMIT_GET | cmd_pwr_limit_get_response |
- * |CMD_PWR_LIMIT_CURR_CAP | cmd_pwr_limit_curr_cap_response |
+ * | Sub-command | Response payload |
+ * |--------------------------|----------------------------------|
+ * | #CMD_PWR_LIMIT_QUERY_ABI | - |
+ * | #CMD_PWR_LIMIT_SET | - |
+ * | #CMD_PWR_LIMIT_GET | #cmd_pwr_limit_get_response |
+ * | #CMD_PWR_LIMIT_CURR_CAP | #cmd_pwr_limit_curr_cap_response |
*/
struct mrq_pwr_limit_response {
union {
@@ -3860,17 +5020,395 @@ struct mrq_pwr_limit_response {
} BPMP_UNION_ANON;
} BPMP_ABI_PACKED;
-/** @} PwrLimit */
-/** @endcond bpmp_th500 */
+/** @} Pwrlimit */
+/** @endcond */
+
+/** @cond (bpmp_th500)
+ * @ingroup MRQ_Codes
+ * @def MRQ_PWRMODEL
+ * @brief Retrieve power evaluted by SoC power model.
+ *
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_pwrmodel_request
+ * * Response Payload: @ref mrq_pwrmodel_response
+ *
+ * @addtogroup Pwrmodel
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_PWRMODEL.
+ */
+enum mrq_pwrmodel_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_PWRMODEL sub-command.
+ *
+ * mrq_response::err is 0 if the specified request is
+ * supported and -#BPMP_ENODEV otherwise.
+ */
+ CMD_PWRMODEL_QUERY_ABI = 0,
+
+ /**
+ * @brief Get power model output power
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_PWRMODEL is not supported by BPMP-FW. |
+ * | -#BPMP_ERANGE | Power model calculation overflow. |
+ */
+ CMD_PWRMODEL_PWR_GET = 1,
+};
+
+/**
+ * @brief Request data for #MRQ_PWRMODEL sub-command #CMD_PWRMODEL_QUERY_ABI
+ */
+struct cmd_pwrmodel_query_abi_request {
+ /** @brief Sub-command identifier from @ref mrq_pwrmodel_cmd */
+ uint32_t cmd_code;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for #MRQ_PWRMODEL sub-command #CMD_PWRMODEL_PWR_GET
+ *
+ * Rerieve power evaluated by power model for specified work-load factor,
+ * temperature, and cpu iso frequency for all cores.
+ */
+struct cmd_pwrmodel_pwr_get_request {
+ /** @brief Unitless work load factor to evaluate power model at */
+ uint32_t work_load_factor;
+ /** @brief CPU frequency in kHz to evaluate power model at */
+ uint32_t cpu_frequency;
+ /** @brief Temperature in mC to evaluate power model at */
+ int32_t temperature;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for #MRQ_PWRMODEL sub-command #CMD_PWRMODEL_PWR_GET
+ */
+struct cmd_pwrmodel_pwr_get_response {
+ /** @brief Power model output in mW */
+ uint32_t power;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_PWRMODEL -command
+ *
+ * | Sub-command | Request payload |
+ * |--------------------------|----------------------------------|
+ * | #CMD_PWRMODEL_QUERY_ABI | #cmd_pwrmodel_query_abi_request |
+ * | #CMD_PWRMODEL_PWR_GET | #cmd_pwrmodel_pwr_get_request |
+ */
+struct mrq_pwrmodel_request {
+ uint32_t cmd;
+ union {
+ struct cmd_pwrmodel_query_abi_request pwrmodel_query_abi_req;
+ struct cmd_pwrmodel_pwr_get_request pwrmodel_pwr_get_req;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
/**
+ * @brief Response payload for the #MRQ_PWRMODEL -command.
+ *
+ * | Sub-command | Response payload |
+ * |--------------------------|----------------------------------|
+ * | #CMD_PWRMODEL_QUERY_ABI | - |
+ * | #CMD_PWRMODEL_PWR_GET | #cmd_pwrmodel_pwr_get_response |
+ */
+struct mrq_pwrmodel_response {
+ union {
+ struct cmd_pwrmodel_pwr_get_response pwrmodel_pwr_get_rsp;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} Pwrmodel */
+/** @endcond */
+
+
+/** @cond (bpmp_th500)
+ * @ingroup MRQ_Codes
+ * @def MRQ_PWR_CNTRL
+ * @brief Configure power controllers.
+ *
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_pwr_cntrl_request
+ * * Response Payload: @ref mrq_pwr_cntrl_response
+ *
+ * @addtogroup Pwrcntrl
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_PWR_CNTRL.
+ */
+enum mrq_pwr_cntrl_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_PWR_CNTRL sub-command.
+ *
+ * mrq_response::err is 0 if the specified request is
+ * supported and -#BPMP_ENODEV otherwise.
+ */
+ CMD_PWR_CNTRL_QUERY_ABI = 0,
+
+ /**
+ * @brief Switch power controller to/out of bypass mode
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_PWR_CNTRL is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_ENOTSUP | Bypass mode is not supported. |
+ */
+ CMD_PWR_CNTRL_BYPASS_SET = 1,
+
+ /**
+ * @brief Get power controller bypass mode status
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_PWR_CNTRL is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_PWR_CNTRL_BYPASS_GET = 2,
+};
+
+/**
+ * @brief Request data for #MRQ_PWR_CNTRL sub-command #CMD_PWR_CNTRL_QUERY_ABI
+ */
+struct cmd_pwr_cntrl_query_abi_request {
+ /** @brief Sub-command identifier from @ref mrq_pwr_cntrl_cmd */
+ uint32_t cmd_code;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_PWR_CNTRL sub-command #CMD_PWR_CNTRL_BYPASS_SET
+ *
+ * Switch specified power controller to / out of bypass mode provided such
+ * mode is supported by the controller.
+ */
+struct cmd_pwr_cntrl_bypass_set_request {
+ /** @brief Power controller identifier from @ref bpmp_pwr_cntrl_id */
+ uint32_t cntrl_id;
+ /**
+ * @brief Bypass setting.
+ *
+ * Valid values:
+ *
+ * * 1 to enter bypass mode,
+ * * 0 to exit bypass mode.
+ */
+ uint32_t bypass_setting;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_PWR_CNTRL sub-command #CMD_PWR_CNTRL_BYPASS_GET
+ *
+ * Get bypass mode status of the specified power controller.
+ */
+struct cmd_pwr_cntrl_bypass_get_request {
+ /** @brief Power controller identifier from @ref bpmp_pwr_cntrl_id */
+ uint32_t cntrl_id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_PWR_CNTRL sub-command #CMD_PWR_CNTRL_BYPASS_GET
+ *
+ * Get current bypass mode status if such mode is supported by the controller.
+ * Otherwise, return "out of bypass" .
+ */
+struct cmd_pwr_cntrl_bypass_get_response {
+ /**
+ * @brief Bypass mode status: 1 controller is in bypass,
+ * 0 controller is out of bypass.
+ */
+ uint32_t bypass_status;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_PWR_CNTRL -command
+ *
+ * | Sub-command | Request payload |
+ * |---------------------------|-----------------------------------|
+ * | #CMD_PWR_CNTRL_QUERY_ABI | #cmd_pwr_cntrl_query_abi_request |
+ * | #CMD_PWR_CNTRL_BYPASS_SET | #cmd_pwr_cntrl_bypass_set_request |
+ * | #CMD_PWR_CNTRL_BYPASS_GET | #cmd_pwr_cntrl_bypass_get_request |
+ */
+struct mrq_pwr_cntrl_request {
+ uint32_t cmd;
+ union {
+ struct cmd_pwr_cntrl_query_abi_request pwr_cntrl_query_abi_req;
+ struct cmd_pwr_cntrl_bypass_set_request pwr_cntrl_bypass_set_req;
+ struct cmd_pwr_cntrl_bypass_get_request pwr_cntrl_bypass_get_req;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for the #MRQ_PWR_CNTRL -command.
+ *
+ * | Sub-command | Response payload |
+ * |---------------------------|-----------------------------------|
+ * | #CMD_PWR_CNTRL_QUERY_ABI | - |
+ * | #CMD_PWR_CNTRL_BYPASS_SET | - |
+ * | #CMD_PWR_CNTRL_BYPASS_GET | #cmd_pwr_cntrl_bypass_get_response|
+ */
+struct mrq_pwr_cntrl_response {
+ union {
+ struct cmd_pwr_cntrl_bypass_get_response pwr_cntrl_bypass_get_rsp;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} Pwrcntrl */
+/** @endcond */
+
+
+/** @cond (bpmp_t264)
+ * @ingroup MRQ_Codes
+ * @def MRQ_SLC
+ * @brief Configure SLC state.
+ *
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_slc_request
+ * * Response Payload: @ref mrq_slc_response
+ *
+ * @addtogroup Slc
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_SLC.
+ */
+enum mrq_slc_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_SLC sub-command.
+ *
+ * mrq_response::err is 0 if the specified request is
+ * supported and -#BPMP_ENODEV otherwise.
+ */
+ CMD_SLC_QUERY_ABI = 0,
+
+ /**
+ * @brief Switch SLC to/out of bypass mode
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_SLC is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_ENOTSUP | Bypass mode is not supported. |
+ */
+ CMD_SLC_BYPASS_SET = 1,
+
+ /**
+ * @brief Get SLC bypass mode status
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|---------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_SLC is not supported by BPMP-FW. |
+ */
+ CMD_SLC_BYPASS_GET = 2,
+};
+
+/**
+ * @brief Request data for #MRQ_SLC sub-command #CMD_SLC_QUERY_ABI
+ */
+struct cmd_slc_query_abi_request {
+ /** @brief Sub-command identifier from @ref mrq_slc_cmd */
+ uint32_t cmd_code;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_SLC sub-command #CMD_SLC_BYPASS_SET
+ *
+ * Switch SLC to / out of bypass mode provided such
+ * mode is supported by the SLC.
+ */
+struct cmd_slc_bypass_set_request {
+ /**
+ * @brief Bypass setting.
+ *
+ * Valid values:
+ *
+ * * 1 to enter bypass mode,
+ * * 0 to exit bypass mode.
+ */
+ uint32_t bypass_setting;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_SLC sub-command #CMD_SLC_BYPASS_GET
+ *
+ * Get current bypass mode status if such mode is supported by the SLC.
+ * Otherwise, return "out of bypass" .
+ */
+struct cmd_slc_bypass_get_response {
+ /**
+ * @brief Bypass mode status: 1 SLC is in bypass,
+ * 0 SLC is out of bypass.
+ */
+ uint32_t bypass_status;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_SLC -command
+ *
+ * | Sub-command | Request payload |
+ * |---------------------------|-----------------------------------|
+ * | #CMD_SLC_QUERY_ABI | #cmd_slc_query_abi_request |
+ * | #CMD_SLC_BYPASS_SET | #cmd_slc_bypass_set_request |
+ * | #CMD_SLC_BYPASS_GET | - |
+ */
+struct mrq_slc_request {
+ uint32_t cmd;
+ union {
+ struct cmd_slc_query_abi_request slc_query_abi_req;
+ struct cmd_slc_bypass_set_request slc_bypass_set_req;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for the #MRQ_SLC -command.
+ *
+ * | Sub-command | Response payload |
+ * |---------------------------|-----------------------------------|
+ * | #CMD_SLC_QUERY_ABI | - |
+ * | #CMD_SLC_BYPASS_SET | - |
+ * | #CMD_SLC_BYPASS_GET | #cmd_slc_bypass_get_response |
+ */
+struct mrq_slc_response {
+ union {
+ struct cmd_slc_bypass_get_response slc_bypass_get_rsp;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} Slc */
+/** @endcond */
+
+/** @cond (bpmp_th500)
* @ingroup MRQ_Codes
* @def MRQ_GEARS
* @brief Get thresholds for NDIV offset switching
*
- * * Platforms: TH500 onwards
- * @cond bpmp_th500
* * Initiators: CCPLEX
* * Targets: BPMP
* * Request Payload: N/A
@@ -3905,11 +5443,1248 @@ struct mrq_pwr_limit_response {
*/
struct mrq_gears_response {
/** @brief number of online CPUs for each gear */
- uint32_t ncpu[16];
+ uint32_t ncpu[8];
+ /** @brief ndiv offset for each gear */
+ uint32_t ndiv_offset[8];
+ /** @brief voltage below which gears are disabled */
+ uint32_t uv_threshold;
} BPMP_ABI_PACKED;
/** @} Gears */
-/** @endcond bpmp_th500 */
+/** @endcond */
+
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_SHUTDOWN
+ * @brief System shutdown
+ *
+ * This message indicates system shutdown or reboot request. BPMP will
+ * initiate system shutdown/reboot after receiving this message, it
+ * may include turning off some rails in sequence and programming
+ * PMIC.
+ *
+ * * Initiators: CPU_S, MCE
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_shutdown_request
+ * * Response Payload: N/A
+ * @addtogroup Shutdown
+ * @{
+ */
+
+/**
+ * @brief Request with #MRQ_SHUTDOWN
+ */
+struct mrq_shutdown_request {
+ /**
+ * @brief Shutdown state ID
+ *
+ * Legal values:
+ * * 0 - Power off
+ * * 1 - Reboot
+ * @cond bpmp_t264
+ * * 2 - Suspend
+ * @endcond
+ */
+ uint32_t state;
+} BPMP_ABI_PACKED;
+
+/** @} Shutdown */
+
+/** @cond (bpmp_th500 || bpmp_tb500)
+ * @defgroup bpmp_c2c_status C2C link status
+ * @addtogroup bpmp_c2c_status
+ * @{
+ */
+/** @brief initial status code */
+#define BPMP_C2C_STATUS_INIT_NOT_STARTED 0
+/** @brief Invalid speedo code */
+#define BPMP_C2C_STATUS_C2C_INVALID_SPEEDO_CODE 7
+/** @brief Invalid frequency */
+#define BPMP_C2C_STATUS_C2C_INVALID_FREQ 8
+/** @brief Invalid link */
+#define BPMP_C2C_STATUS_C2C_INVALID_LINK 9
+/** @brief refpll lock polling times out - partition 0 */
+#define BPMP_C2C_STATUS_C2C0_REFPLL_FAIL 10
+/** @brief refpll lock polling times out - partition 1 */
+#define BPMP_C2C_STATUS_C2C1_REFPLL_FAIL 11
+/** @brief PLL cal times out - partition 0 */
+#define BPMP_C2C_STATUS_C2C0_PLLCAL_FAIL 12
+/** @brief PLL cal times out - partition 1 */
+#define BPMP_C2C_STATUS_C2C1_PLLCAL_FAIL 13
+/** @brief clock detection times out - partition 0 */
+#define BPMP_C2C_STATUS_C2C0_CLKDET_FAIL 14
+/** @brief clock detection times out - partition 1 */
+#define BPMP_C2C_STATUS_C2C1_CLKDET_FAIL 15
+/** @brief Final trainings fail partition 0 */
+#define BPMP_C2C_STATUS_C2C0_TR_FAIL 16
+/** @brief Final trainings fail partition 1 */
+#define BPMP_C2C_STATUS_C2C1_TR_FAIL 17
+/** @brief C2C FW init done */
+#define NV_GFW_GLOBAL_DEVINIT_C2C_STATUS_C2C_FW_INIT_DONE 20
+/** @brief C2C FW init failed partition 0 */
+#define NV_GFW_GLOBAL_DEVINIT_C2C_STATUS_C2C0_FW_INIT_FAIL 21
+/** @brief C2C FW init failed partition 1 */
+#define NV_GFW_GLOBAL_DEVINIT_C2C_STATUS_C2C1_FW_INIT_FAIL 22
+/** @brief no failure seen, c2c init was successful */
+#define BPMP_C2C_STATUS_C2C_LINK_TRAIN_PASS 255
+/** @} bpmp_c2c_status */
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_C2C
+ * @brief Control C2C partitions initialization.
+ *
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_c2c_request
+ * * Response Payload: @ref mrq_c2c_response
+ *
+ * @addtogroup C2C
+ * @{
+ */
+enum mrq_c2c_cmd {
+ /**
+ * @brief Check whether the BPMP driver supports the specified request
+ * type
+ *
+ * mrq_response:: err is 0 if the specified request is supported and
+ * -#BPMP_ENODEV otherwise
+ */
+ CMD_C2C_QUERY_ABI = 0,
+
+ /**
+ * @brief Start C2C initialization
+ *
+ * mrq_response:err is
+ * * 0: Success
+ * * -#BPMP_ENODEV: MRQ_C2C is not supported by BPMP-FW
+ * * -#BPMP_ENAVAIL: Invalid request parameters
+ * * -#BPMP_EACCES: Request is not accepted
+ */
+ CMD_C2C_START_INITIALIZATION = 1,
+
+ /**
+ * @brief Command to query current C2C training status
+ *
+ * This command will return the result of the latest C2C re-training that is initiated with
+ * MRQ_C2C.CMD_C2C_START_INITIALIZATION or MRQ_C2C.CMD_C2C_START_HOTRESET calls.
+ * If no training has been initiated yet, the command will return code BPMP_C2C_STATUS_INIT_NOT_STARTED.
+ *
+ * mrq_response:err is
+ * * 0: Success
+ * * -#BPMP_ENODEV: MRQ_C2C is not supported by BPMP-FW
+ * * -#BPMP_EACCES: Request is not accepted
+ */
+ CMD_C2C_GET_STATUS = 2,
+ /**
+ * @brief C2C hot-reset precondition
+ *
+ * mrq_response:err is
+ * * 0: Success
+ * * -#BPMP_ENODEV: MRQ_C2C is not supported by BPMP-FW
+ * * -#BPMP_ENAVAIL: Invalid request parameters
+ * * -#BPMP_EACCES: Request is not accepted
+ */
+ CMD_C2C_HOTRESET_PREP = 3,
+ /**
+ * @brief Start C2C hot-reset
+ *
+ * mrq_response:err is
+ * * 0: Success
+ * * -#BPMP_ENODEV: MRQ_C2C is not supported by BPMP-FW
+ * * -#BPMP_ENAVAIL: Invalid request parameters
+ * * -#BPMP_EACCES: Request is not accepted
+ */
+ CMD_C2C_START_HOTRESET = 4,
+
+ CMD_C2C_MAX
+};
+
+/**
+ * @brief Request data for #MRQ_C2C command CMD_C2C_QUERY_ABI
+ */
+struct cmd_c2c_query_abi_request {
+ /** @brief Command identifier to be queried */
+ uint32_t cmd;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_C2C command CMD_C2C_START_INITIALIZATION
+ */
+struct cmd_c2c_start_init_request {
+ /** @brief 1: partition 0; 2: partition 1; 3: partition 0 and 1; */
+ uint8_t partitions;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_C2C command CMD_C2C_START_INITIALIZATION
+ */
+struct cmd_c2c_start_init_response {
+ /** @brief Refer to @ref bpmp_c2c_status */
+ uint8_t status;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_C2C command CMD_C2C_GET_STATUS
+ */
+struct cmd_c2c_get_status_response {
+ /** @brief Refer to @ref bpmp_c2c_status */
+ uint8_t status;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_C2C command CMD_C2C_HOTRESET_PREP
+ */
+struct cmd_c2c_hotreset_prep_request {
+ /** @brief 1: partition 0; 2: partition 1; 3: partition 0 and 1; */
+ uint8_t partitions;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_C2C command CMD_C2C_START_HOTRESET
+ */
+struct cmd_c2c_start_hotreset_request {
+ /** @brief 1: partition 0; 2: partition 1; 3: partition 0 and 1; */
+ uint8_t partitions;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_C2C command CMD_C2C_START_HOTRESET
+ */
+struct cmd_c2c_start_hotreset_response {
+ /** @brief Refer to @ref bpmp_c2c_status */
+ uint8_t status;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request with #MRQ_C2C
+ *
+ * |sub-command |payload |
+ * |-----------------------------|-------------------------------|
+ * |CMD_C2C_QUERY_ABI |cmd_c2c_query_abi_request |
+ * |CMD_C2C_START_INITIALIZATION |cmd_c2c_start_init_request |
+ * |CMD_C2C_GET_STATUS | |
+ * |CMD_C2C_HOTRESET_PREP |cmd_c2c_hotreset_prep_request |
+ * |CMD_C2C_START_HOTRESET |cmd_c2c_start_hotreset_request |
+
+ */
+struct mrq_c2c_request {
+ uint32_t cmd;
+ union {
+ struct cmd_c2c_query_abi_request c2c_query_abi_req;
+ struct cmd_c2c_start_init_request c2c_start_init_req;
+ struct cmd_c2c_hotreset_prep_request c2c_hotreset_prep_req;
+ struct cmd_c2c_start_hotreset_request c2c_start_hotreset_req;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response to MRQ_C2C
+ *
+ * |sub-command |payload |
+ * |-----------------------------|--------------------------------|
+ * |CMD_C2C_QUERY_ABI | |
+ * |CMD_C2C_START_INITIALIZATION |cmd_c2c_start_init_response |
+ * |CMD_C2C_GET_STATUS |cmd_c2c_get_status_response |
+ * |CMD_C2C_HOTRESET_PREP | |
+ * |CMD_C2C_START_HOTRESET |cmd_c2c_start_hotreset_response |
+ */
+struct mrq_c2c_response {
+ union {
+ struct cmd_c2c_start_init_response c2c_start_init_resp;
+ struct cmd_c2c_get_status_response c2c_get_status_resp;
+ struct cmd_c2c_start_hotreset_response c2c_start_hotreset_resp;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+/** @} */
+/** @endcond */
+
+
+/** @cond (bpmp_t264)
+ * @ingroup MRQ_Codes
+ * @def MRQ_PCIE
+ * @brief Perform a PCIE operation
+ *
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_pcie_request
+ *
+ * @addtogroup PCIE
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_PCIE.
+ */
+enum mrq_pcie_cmd {
+ /** @brief Initialize PCIE EP controller. */
+ CMD_PCIE_EP_CONTROLLER_INIT = 0,
+ /** @brief Disable PCIE EP controller. */
+ CMD_PCIE_EP_CONTROLLER_OFF = 1,
+
+ /** @brief Disable PCIE RP controller. */
+ CMD_PCIE_RP_CONTROLLER_OFF = 100,
+
+ CMD_PCIE_MAX,
+};
+
+/**
+ * @brief Request payload for #MRQ_PCIE sub-command #CMD_PCIE_EP_CONTROLLER_INIT.
+ */
+struct cmd_pcie_ep_controller_init_request {
+ /**
+ * @brief PCIe EP controller number.
+ * Valid entries for T264 are 2, 4 and 5.
+ */
+ uint8_t ep_controller;
+ /**
+ * @brief PCIe EP function programming interface code.
+ * Valid range in HW is [0, 0xFFU], BPMP-FW programs the input value without any check.
+ * It is up to the requester to send valid input as documented in "PCI CODE AND ID
+ * ASSIGNMENT SPECIFICATION".
+ */
+ uint8_t progif_code;
+ /**
+ * @brief PCIe EP function sub-class code.
+ * Valid range in HW is [0, 0xFFU], BPMP-FW programs the input value without any check.
+ * It is up to the requester to send valid input as documented in "PCI CODE AND ID
+ * ASSIGNMENT SPECIFICATION".
+ */
+ uint8_t subclass_code;
+ /**
+ * @brief PCIe EP function base class code.
+ * Valid range in HW is [0, 0xFFU], BPMP-FW programs the input value without any check.
+ * It is up to the requester to send valid input as documented in "PCI CODE AND ID
+ * ASSIGNMENT SPECIFICATION".
+ */
+ uint8_t baseclass_code;
+ /**
+ * @brief PCIe EP function device id.
+ * Valid range is [0, 0x7FU], only LSB 7 bits are writable in 16-bit PCI device id.
+ * Valid range check is done on input value and returns -BPMP_EINVAL on failure.
+ */
+ uint8_t deviceid;
+ /**
+ * @brief PCIe EP EP BAR1 size.
+ * Valid range is [6U, 16U], which translate to [64MB, 64GB] size.
+ * Valid range check is done on input value and returns -BPMP_EINVAL on failure.
+ */
+ uint8_t bar1_size;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for #MRQ_PCIE sub-command #CMD_PCIE_EP_CONTROLLER_OFF.
+ */
+struct cmd_pcie_ep_controller_off_request {
+ /** @brief EP controller number, T264 valid: 2, 4, 5. */
+ uint8_t ep_controller;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for #MRQ_PCIE sub-command #CMD_PCIE_RP_CONTROLLER_OFF.
+ */
+struct cmd_pcie_rp_controller_off_request {
+ /** @brief RP controller number, T264 valid: 1-5 */
+ uint8_t rp_controller;
+} BPMP_ABI_PACKED;
+
+/**
+ * @ingroup PCIE
+ * @brief Request payload for the #MRQ_PCIE command.
+ *
+ * Used by the sender of an #MRQ_PCIE message to control PCIE.
+ * Below table shows sub-commands with their corresponding payload data.
+ *
+ * |sub-command |payload |
+ * |--------------------------------------|-----------------------------------------|
+ * |#CMD_PCIE_EP_CONTROLLER_INIT |#cmd_pcie_ep_controller_init_request |
+ * |#CMD_PCIE_EP_CONTROLLER_OFF |#cmd_pcie_ep_controller_off_request |
+ *
+ * @cond (!bpmp_safe)
+ *
+ * The following additional MRQs are supported on non-functional-safety
+ * builds:
+ * |sub-command |payload |
+ * |--------------------------------------|-----------------------------------------|
+ * |#CMD_PCIE_RP_CONTROLLER_OFF |#cmd_pcie_rp_controller_off_request |
+ *
+ * @endcond
+ *
+ */
+struct mrq_pcie_request {
+ /** @brief Sub-command ID from @ref mrq_pcie_cmd. */
+ uint32_t cmd;
+
+ union {
+ struct cmd_pcie_ep_controller_init_request ep_ctrlr_init;
+ struct cmd_pcie_ep_controller_off_request ep_ctrlr_off;
+ /** @cond (!bpmp_safe) */
+ struct cmd_pcie_rp_controller_off_request rp_ctrlr_off;
+ /** @endcond */
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} PCIE */
+/** @endcond */
+
+/** @cond (bpmp_t264)
+ * @ingroup MRQ_Codes
+ * @def MRQ_CR7
+ * @brief Perform a CR7 operation
+ *
+ * * Initiators: CPU_S
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_cr7_request
+ *
+ * @addtogroup CR7
+ * @{
+ */
+
+/**
+ * @brief Payload for #MRQ_CR7
+ * 2 fields for future parameters are provided. These must be 0 currently.
+ */
+struct cmd_cr7_request {
+ uint32_t fld0;
+ uint32_t fld1;
+} BPMP_ABI_PACKED;
+
+struct cmd_cr7_query_abi_request {
+ /** #MRQ_CR7 sub-command identifier from @ref mrq_cr7_cmd */
+ uint32_t type;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Sub-command identifiers for #MRQ_CR7.
+ */
+enum mrq_cr7_cmd {
+ /**
+ * @brief Check whether the BPMP driver supports the specified request
+ * type
+ *
+ * mrq_response:: err is 0 if the specified request is supported and
+ * -#BPMP_ENODEV otherwise
+ */
+ CMD_CR7_QUERY_ABI = 0,
+
+ /** @brief Enter CR7 state on the package BPMP-FW is running on. */
+ CMD_CR7_ENTRY = 1,
+ /** @brief Exit CR7 state on the package BPMP-FW is running on. */
+ CMD_CR7_EXIT = 2,
+
+ CMD_CR7_MAX,
+};
+
+/**
+ * @ingroup CR7
+ * @brief #MRQ_CR7 structure
+ *
+ * |Sub-command |Payload |
+ * |----------------------------|---------------------------|
+ * |#CMD_CR7_QUERY_ABI | #cmd_cr7_query_abi_request|
+ * |#CMD_CR7_ENTRY | #cmd_cr7_request |
+ * |#CMD_CR7_EXIT | #cmd_cr7_request |
+
+ */
+struct mrq_cr7_request {
+ /** @brief Sub-command ID from @ref mrq_cr7_cmd. */
+ uint32_t cmd;
+ union {
+ struct cmd_cr7_query_abi_request query_abi;
+ struct cmd_cr7_request cr7_request;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} CR7 */
+/** @endcond */
+
+/** @cond (bpmp_tb500)
+ * @ingroup MRQ_Codes
+ * @def MRQ_HWPM
+ * @brief Configure and query HWPM functionality
+ *
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_hwpm_request
+ * * Response Payload: @ref mrq_hwpm_response
+ *
+ * @addtogroup HWPM
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_HWPM.
+ */
+enum mrq_hwpm_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_HWPM sub-command.
+ *
+ * mrq_response:err is 0 if the specified request is
+ * supported and -#BPMP_ENODEV otherwise.
+ */
+ CMD_HWPM_QUERY_ABI = 1,
+
+ /**
+ * @brief Configure IPMU triggers
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_IPMU_SET_TRIGGERS = 2,
+
+ /**
+ * @brief Configure IPMU payloads and shifts
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_IPMU_SET_PAYLOADS_SHIFTS = 3,
+
+ /**
+ * @brief Get maximum number of payloads
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ */
+ CMD_HWPM_IPMU_GET_MAX_PAYLOADS = 4,
+
+ /**
+ * @brief Configure NVTHERM sample rate
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_NVTHERM_SET_SAMPLE_RATE = 5,
+
+ /**
+ * @brief Set NVTHERM bubble interval
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_NVTHERM_SET_BUBBLE_INTERVAL = 6,
+
+ /**
+ * @brief Configure NVTHERM DG flexible channels
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_NVTHERM_SET_FLEX_CHANNELS = 7,
+
+ /**
+ * @brief Get ISENSE sensor name
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_ISENSE_GET_SENSOR_NAME = 8,
+
+ /**
+ * @brief Get ISENSE sensor channel
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_ISENSE_GET_SENSOR_CHANNEL = 9,
+
+ /**
+ * @brief Get ISENSE sensor scale factor
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_ISENSE_GET_SENSOR_SCALE_FACTOR = 10,
+
+ /**
+ * @brief Get ISENSE sensor offset
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ * | -#BPMP_ENODATA | No sensor offset. |
+ */
+ CMD_HWPM_ISENSE_GET_SENSOR_OFFSET = 11,
+
+ /**
+ * @brief Get ISENSE sum block name
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_ISENSE_GET_SUM_BLOCK_NAME = 12,
+
+ /**
+ * @brief Get ISENSE sum input sensor IDs
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_HWPM is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_HWPM_ISENSE_GET_SUM_BLOCK_INPUTS = 13,
+
+ /**
+ * @brief Largest supported #MRQ_HWPM sub-command identifier + 1
+ */
+ CMD_HWPM_MAX,
+};
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_QUERY_ABI
+ */
+struct cmd_hwpm_query_abi_req {
+ /** @brief Sub-command identifier from @ref mrq_hwpm_cmd */
+ uint32_t cmd_code;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Maximum array length for IPMU trigger bitmask
+ */
+#define HWPM_IPMU_TRIGGER_ARR_LEN 28U
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_IPMU_SET_TRIGGERS
+ */
+struct cmd_hwpm_ipmu_set_triggers_req {
+ /** @brief IPMU physical ID
+ *
+ * @note Valid range from [0, MAX_CPU_CORES), see @ref bpmp_hwpm_core_config
+ */
+ uint32_t ipmu_phys_id;
+ /** @brief Trigger bitmask, see @ref bpmp_ipmu_trigger_ids
+ *
+ * @note Setting a trigger bit will cause the associated trigger to
+ * generate an output packet from IPMU to the HWPM perfmux.
+ * @note Up to a maximum possible 896 triggers
+ */
+ uint32_t triggers[HWPM_IPMU_TRIGGER_ARR_LEN];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Array length for IPMU payload bitmask
+ */
+#define HWPM_IPMU_PAYLOAD_ARR_LEN 26U
+
+/**
+ * @brief Array length for IPMU payload shift bitmask
+ */
+#define HWPM_IPMU_SHIFT_ARR_LEN 2U
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_IPMU_SET_PAYLOADS_SHIFTS
+ */
+struct cmd_hwpm_ipmu_set_payloads_shifts_req {
+ /** @brief IPMU physical ID
+ *
+ * @note Valid range from [0, MAX_CPU_CORES), see @ref bpmp_hwpm_core_config
+ */
+ uint32_t ipmu_phys_id;
+ /** @brief Payload bitmask, see @ref bpmp_ipmu_payload_ids
+ *
+ * @note Setting a payload bit will add the associated payload to the
+ * IPMU output packet.
+ * @note The maximum number of payloads is platform dependent,
+ * @see #CMD_HWPM_IPMU_GET_MAX_PAYLOADS
+ * @note To disable IPMU streaming on this instance, set all payload bits to 0.
+ * @note Up to a maximum of 832 available payloads
+ */
+ uint32_t payloads[HWPM_IPMU_PAYLOAD_ARR_LEN];
+ /**
+ * @brief Payload shift mask
+ *
+ * @note Setting the i-th shift bit will right-shift the
+ * i-th enabled payload by 1 bit.
+ * @note Up to a maximum of 64 simultaneous emitted payloads
+ */
+ uint32_t shifts[HWPM_IPMU_SHIFT_ARR_LEN];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_IPMU_GET_MAX_PAYLOADS
+ */
+struct cmd_hwpm_ipmu_get_max_payloads_req {
+ BPMP_ABI_EMPTY
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_NVTHERM_SET_SAMPLE_RATE
+ */
+struct cmd_hwpm_nvtherm_set_sample_rate_req {
+ /** @brief Sample rate in microseconds
+ *
+ * @note Requesting a sample rate of 0 will disable NVTHERM streaming.
+ */
+ uint32_t sample_rate;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_NVTHERM_SET_BUBBLE_INTERVAL
+ */
+struct cmd_hwpm_nvtherm_set_bubble_interval_req {
+ /** @brief Bubble interval in microseconds */
+ uint32_t bubble_interval;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Maximum array length for NVTHERM flexible channel bitmask
+ */
+#define HWPM_NVTHERM_FLEX_CHANNEL_ARR_LEN 29U
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_NVTHERM_SET_FLEX_CHANNELS
+ */
+struct cmd_hwpm_nvtherm_set_flex_channels_req {
+ /** @brief NVTHERM flexible channel bitmask
+ *
+ * @see #bpmp_nvtherm_flex_channel_ids
+ *
+ * @note Up to a maximum of 928 flexible channels
+ */
+ uint32_t channels[HWPM_NVTHERM_FLEX_CHANNEL_ARR_LEN];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_NAME
+ */
+struct cmd_hwpm_isense_get_sensor_name_req {
+ /** @brief Sensor ID from @ref bpmp_isense_sensor_ids */
+ uint32_t sensor_id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_CHANNEL
+ */
+struct cmd_hwpm_isense_get_sensor_channel_req {
+ /** @brief Sensor ID from @ref bpmp_isense_sensor_ids */
+ uint32_t sensor_id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_SCALE_FACTOR
+ */
+struct cmd_hwpm_isense_get_sensor_scale_factor_req {
+ /** @brief Sensor ID from @ref bpmp_isense_sensor_ids */
+ uint32_t sensor_id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_OFFSET
+ */
+struct cmd_hwpm_isense_get_sensor_offset_req {
+ /** @brief Sensor ID from @ref bpmp_isense_sensor_ids */
+ uint32_t sensor_id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SUM_BLOCK_NAME
+ */
+struct cmd_hwpm_isense_get_sum_block_name_req {
+ /** @brief Sum block index */
+ uint32_t sum_block_index;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SUM_BLOCK_INPUTS
+ */
+struct cmd_hwpm_isense_get_sum_block_inputs_req {
+ /** @brief Sum block index */
+ uint32_t sum_block_index;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_HWPM sub-command #CMD_HWPM_IPMU_GET_MAX_PAYLOADS
+ */
+struct cmd_hwpm_ipmu_get_max_payloads_resp {
+ /** @brief Maximum number of payloads */
+ uint32_t max_payloads;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Maximum array length for ISENSE sensor name
+ */
+#define HWPM_ISENSE_SENSOR_MAX_NAME_LEN 64U
+
+/**
+ * @brief Response data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_NAME
+ */
+struct cmd_hwpm_isense_get_sensor_name_resp {
+ /** @brief Sensor name */
+ char sensor_name[HWPM_ISENSE_SENSOR_MAX_NAME_LEN];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_CHANNEL
+ */
+struct cmd_hwpm_isense_get_sensor_channel_resp {
+ /** @brief Physical channel index */
+ uint32_t channel_index;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_SCALE_FACTOR
+ */
+struct cmd_hwpm_isense_get_sensor_scale_factor_resp {
+ /** @brief Scale factor */
+ float scale_factor;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SENSOR_OFFSET
+ */
+struct cmd_hwpm_isense_get_sensor_offset_resp {
+ /** @brief Offset sensor ID */
+ uint32_t offset_sensor_id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Maximum array length for ISENSE sum name
+ */
+#define HWPM_ISENSE_SUM_BLOCK_MAX_NAME_LEN 64U
+
+/**
+ * @brief Response data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SUM_BLOCK_NAME
+ */
+struct cmd_hwpm_isense_get_sum_block_name_resp {
+ /** @brief Sum block name */
+ char sum_block_name[HWPM_ISENSE_SUM_BLOCK_MAX_NAME_LEN];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Maximum array length for ISENSE sum block input sensor IDs
+ */
+#define HWPM_ISENSE_SUM_BLOCK_INPUTS_MAX 16U
+
+/**
+ * @brief Response data for #MRQ_HWPM sub-command #CMD_HWPM_ISENSE_GET_SUM_BLOCK_INPUTS
+ */
+struct cmd_hwpm_isense_get_sum_block_inputs_resp {
+ /** @brief Input channel indices; negative if no input is applied */
+ int32_t input_channel_idx[HWPM_ISENSE_SUM_BLOCK_INPUTS_MAX];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_HWPM -command
+ *
+ * | Sub-command | Request payload |
+ * | ---------------------------------------- | -------------------------------------------- |
+ * | #CMD_HWPM_QUERY_ABI | #cmd_hwpm_query_abi_req |
+ * | #CMD_HWPM_IPMU_SET_TRIGGERS | #cmd_hwpm_ipmu_set_triggers_req |
+ * | #CMD_HWPM_IPMU_SET_PAYLOADS_SHIFTS | #cmd_hwpm_ipmu_set_payloads_shifts_req |
+ * | #CMD_HWPM_IPMU_GET_MAX_PAYLOADS | #cmd_hwpm_ipmu_get_max_payloads_req |
+ * | #CMD_HWPM_NVTHERM_SET_SAMPLE_RATE | #cmd_hwpm_nvtherm_set_sample_rate_req |
+ * | #CMD_HWPM_NVTHERM_SET_BUBBLE_INTERVAL | #cmd_hwpm_nvtherm_set_bubble_interval_req |
+ * | #CMD_HWPM_NVTHERM_SET_FLEX_CHANNELS | #cmd_hwpm_nvtherm_set_flex_channels_req |
+ * | #CMD_HWPM_ISENSE_GET_SENSOR_CHANNEL | #cmd_hwpm_isense_get_sensor_channel_req |
+ * | #CMD_HWPM_ISENSE_GET_SENSOR_SCALE_FACTOR | #cmd_hwpm_isense_get_sensor_scale_factor_req |
+ * | #CMD_HWPM_ISENSE_GET_SENSOR_OFFSET | #cmd_hwpm_isense_get_sensor_offset_req |
+ * | #CMD_HWPM_ISENSE_GET_SUM_BLOCK_NAME | #cmd_hwpm_isense_get_sum_block_name_req |
+ * | #CMD_HWPM_ISENSE_GET_SUM_BLOCK_INPUTS | #cmd_hwpm_isense_get_sum_block_inputs_req |
+ */
+struct mrq_hwpm_request {
+ uint32_t cmd;
+ union {
+ struct cmd_hwpm_query_abi_req query_abi;
+ struct cmd_hwpm_ipmu_set_triggers_req ipmu_set_triggers;
+ struct cmd_hwpm_ipmu_set_payloads_shifts_req ipmu_set_payloads_shifts;
+ struct cmd_hwpm_ipmu_get_max_payloads_req ipmu_get_max_payloads;
+ struct cmd_hwpm_nvtherm_set_sample_rate_req nvtherm_set_sample_rate;
+ struct cmd_hwpm_nvtherm_set_bubble_interval_req nvtherm_set_bubble_interval;
+ struct cmd_hwpm_nvtherm_set_flex_channels_req nvtherm_set_flex_channels;
+ struct cmd_hwpm_isense_get_sensor_name_req isense_get_sensor_name;
+ struct cmd_hwpm_isense_get_sensor_channel_req isense_get_sensor_channel;
+ struct cmd_hwpm_isense_get_sensor_scale_factor_req isense_get_sensor_scale_factor;
+ struct cmd_hwpm_isense_get_sensor_offset_req isense_get_sensor_offset;
+ struct cmd_hwpm_isense_get_sum_block_name_req isense_get_sum_block_name;
+ struct cmd_hwpm_isense_get_sum_block_inputs_req isense_get_sum_block_inputs;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for the #MRQ_HWPM -command
+ *
+ * | Sub-command | Response payload |
+ * | ---------------------------------------- | --------------------------------------------- |
+ * | #CMD_HWPM_QUERY_ABI | - |
+ * | #CMD_HWPM_IPMU_SET_TRIGGERS | - |
+ * | #CMD_HWPM_IPMU_SET_PAYLOADS_SHIFTS | - |
+ * | #CMD_HWPM_IPMU_GET_MAX_PAYLOADS | #cmd_hwpm_ipmu_get_max_payloads_resp |
+ * | #CMD_HWPM_NVTHERM_SET_SAMPLE_RATE | - |
+ * | #CMD_HWPM_NVTHERM_SET_BUBBLE_INTERVAL | - |
+ * | #CMD_HWPM_NVTHERM_SET_FLEX_CHANNELS | - |
+ * | #CMD_HWPM_ISENSE_GET_SENSOR_NAME | #cmd_hwpm_isense_get_sensor_name_resp |
+ * | #CMD_HWPM_ISENSE_GET_SENSOR_CHANNEL | #cmd_hwpm_isense_get_sensor_channel_resp |
+ * | #CMD_HWPM_ISENSE_GET_SENSOR_SCALE_FACTOR | #cmd_hwpm_isense_get_sensor_scale_factor_resp |
+ * | #CMD_HWPM_ISENSE_GET_SENSOR_OFFSET | #cmd_hwpm_isense_get_sensor_offset_resp |
+ * | #CMD_HWPM_ISENSE_GET_SUM_BLOCK_NAME | #cmd_hwpm_isense_get_sum_block_name_resp |
+ * | #CMD_HWPM_ISENSE_GET_SUM_BLOCK_INPUTS | #cmd_hwpm_isense_get_sum_block_inputs_resp |
+ */
+struct mrq_hwpm_response {
+ uint32_t err;
+ union {
+ struct cmd_hwpm_ipmu_get_max_payloads_resp ipmu_get_max_payloads;
+ struct cmd_hwpm_isense_get_sensor_name_resp isense_get_sensor_name;
+ struct cmd_hwpm_isense_get_sensor_channel_resp isense_get_sensor_channel;
+ struct cmd_hwpm_isense_get_sensor_scale_factor_resp isense_get_sensor_scale_factor;
+ struct cmd_hwpm_isense_get_sensor_offset_resp isense_get_sensor_offset;
+ struct cmd_hwpm_isense_get_sum_block_name_resp isense_get_sum_block_name;
+ struct cmd_hwpm_isense_get_sum_block_inputs_resp isense_get_sum_block_inputs;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} HWPM */
+/** @endcond */
+
+/** @cond (bpmp_tb500)
+ * @ingroup MRQ_Codes
+ * @def MRQ_DVFS
+ * @brief Configure DVFS functionality
+ *
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_dvfs_request
+ *
+ * @addtogroup DVFS
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_DVFS.
+ */
+enum mrq_dvfs_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_DVFS sub-command.
+ *
+ * mrq_response:err is 0 if the specified request is
+ * supported and -#BPMP_ENODEV otherwise.
+ */
+ CMD_DVFS_QUERY_ABI = 1,
+
+ /**
+ * @brief Configure DVFS controller
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_DVFS is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_DVFS_SET_CTRL_STATE = 2,
+
+ /**
+ * @brief Configure DVFS manager
+ *
+ * mrq_response:err is defined as:
+ *
+ * | Value | Description |
+ * | -------------- | ------------------------------------------- |
+ * | 0 | Success |
+ * | -#BPMP_ENODEV | #MRQ_DVFS is not supported by BPMP-FW. |
+ * | -#BPMP_ENOTSUP | Subcommand is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_DVFS_SET_MGR_STATE = 3,
+
+ /**
+ * @brief Largest supported #MRQ_DVFS sub-command identifier + 1
+ */
+ CMD_DVFS_MAX,
+};
+
+/**
+ * @brief Request data for #MRQ_DVFS sub-command #CMD_DVFS_QUERY_ABI
+ */
+struct cmd_dvfs_query_abi_req {
+ /** @brief Sub-command identifier from @ref mrq_dvfs_cmd */
+ uint32_t cmd_code;
+} BPMP_ABI_PACKED;
+
+struct cmd_dvfs_set_ctrl_state_req {
+ /** @brief Controller ID from @ref bpmp_dvfs_ctrl_ids */
+ uint32_t ctrl_id;
+ /** @brief Controller enable state */
+ uint32_t enable;
+} BPMP_ABI_PACKED;
+
+struct cmd_dvfs_set_mgr_state_req {
+ /** @brief Manager ID from @ref bpmp_dvfs_mgr_ids */
+ uint32_t mgr_id;
+ /** @brief Manager enable state */
+ uint32_t enable;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_DVFS -command
+ *
+ * | Sub-command | Request payload |
+ * | ---------------------------------------- | -------------------------------------------- |
+ * | #CMD_DVFS_QUERY_ABI | #cmd_dvfs_query_abi_req |
+ * | #CMD_DVFS_SET_CTRL_STATE | #cmd_dvfs_set_ctrl_state_req |
+ * | #CMD_DVFS_SET_MGR_STATE | #cmd_dvfs_set_mgr_state_req |
+ */
+struct mrq_dvfs_request {
+ uint32_t cmd;
+ union {
+ struct cmd_dvfs_query_abi_req query_abi;
+ struct cmd_dvfs_set_ctrl_state_req set_ctrl_state;
+ struct cmd_dvfs_set_mgr_state_req set_mgr_state;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} DVFS */
+/** @endcond */
+
+/** @cond (bpmp_tb500)
+ * @ingroup MRQ_Codes
+ * @def MRQ_PPP_PROFILE
+ * @brief Get power/performance profile configuration settings.
+ *
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_ppp_profile_request
+ * * Response Payload: @ref mrq_ppp_profile_response
+ *
+ * @addtogroup PPP
+ * @{
+ */
+
+/**
+ * @brief Sub-command identifiers for #MRQ_PPP_PROFILE.
+ */
+enum mrq_ppp_profile_cmd {
+ /**
+ * @brief Check whether the BPMP-FW supports the specified
+ * #MRQ_PPP_PROFILE sub-command.
+ *
+ * mrq_ppp_profile_response:err is 0 if the specified request is
+ * supported and -#BPMP_ENOTSUP otherwise.
+ */
+
+ CMD_PPP_PROFILE_QUERY_ABI = 0,
+ /**
+ * @brief Query the BPMP for the CPU core and SLC slice configuration associated
+ * with a given Power/Performance Profile (PPP).
+ *
+ * mrq_ppp_profile_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|------------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENOTSUP | #MRQ_PPP_PROFILE is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_PPP_PROFILE_QUERY_MASKS = 1,
+ /**
+ * @brief Query BPMP for the CPU mask corresponding to a requested
+ * number of active CPU cores.
+ *
+ * mrq_ppp_profile_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|------------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENOTSUP | #MRQ_PPP_PROFILE is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_PPP_CORE_QUERY_CPU_MASK = 2,
+ /**
+ * @brief Query BPMP-FW for the currently available Power/Performance Profiles.
+ *
+ * mrq_ppp_profile_response:err is defined as:
+ *
+ * | Value | Description |
+ * |----------------|------------------------------------------------|
+ * | 0 | Success |
+ * | -#BPMP_ENOTSUP | #MRQ_PPP_PROFILE is not supported by BPMP-FW. |
+ * | -#BPMP_EINVAL | Invalid request parameters. |
+ */
+ CMD_PPP_AVAILABLE_QUERY = 3,
+};
+
+/**
+ * @brief Request data for #MRQ_PPP_PROFILE sub-command
+ * #CMD_PPP_PROFILE_QUERY_ABI
+ */
+struct cmd_ppp_profile_query_abi_req {
+ /** @brief Sub-command identifier from @ref mrq_ppp_profile_cmd */
+ uint32_t cmd_code;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_PPP_PROFILE sub-command
+ * #CMD_PPP_AVAILABLE_QUERY
+ */
+struct cmd_ppp_available_query_resp {
+ /**
+ * @brief Bitmask of available profiles.
+ * Bit N = 1 ⇒ profile N is available
+ */
+ uint32_t avail_ppp_mask;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_PPP_PROFILE sub-command
+ * #CMD_PPP_PROFILE_QUERY_MASKS
+ */
+struct cmd_ppp_profile_query_masks_req {
+ /** @brief power/perf profile identifier */
+ uint32_t profile_id;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for #MRQ_PPP_PROFILE sub-command
+ * #CMD_PPP_PROFILE_QUERY_MASKS
+ */
+struct cmd_ppp_profile_query_masks_resp {
+ /** @brief Enabled cores in this profile */
+ uint32_t num_active_cores;
+ /** @brief Enabled SLC slices in this profile */
+ uint32_t num_active_slcs;
+ /** @brief Number of valid words in active_core_masks array */
+ uint32_t max_num_core_words;
+ /** @brief Number of valid words in active_slc_masks array */
+ uint32_t max_num_slc_words;
+ /** @brief Enabled cores bit mask (bit N = 1 => core N enabled) */
+ uint32_t active_core_masks[8];
+ /** @brief Enabled SLC slices bit mask (bit N = 1 => SLC slice N enabled) */
+ uint32_t active_slc_masks[8];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request data for #MRQ_PPP_PROFILE sub-command
+ * #CMD_PPP_CORE_QUERY_CPU_MASK
+ */
+struct cmd_ppp_core_query_cpu_mask_req {
+ /** @brief Requested number of active cores */
+ uint32_t num_cores;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response data for #MRQ_PPP_PROFILE sub-command
+ * #CMD_PPP_CORE_QUERY_CPU_MASK
+ */
+struct cmd_ppp_core_query_cpu_mask_resp {
+ /** @brief Number of valid words in active_core_masks array */
+ uint32_t max_num_words;
+ /** @brief Enabled CPU core bitmask (bit N = 1 ⇒ core N enabled) */
+ uint32_t active_core_masks[8];
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Request payload for the #MRQ_PPP_PROFILE -command
+ *
+ * | Sub-command | Request payload |
+ * |-------------------------------|----------------------------------------|
+ * | #CMD_PPP_PROFILE_QUERY_ABI | #cmd_ppp_profile_query_abi_req |
+ * | #CMD_PPP_PROFILE_QUERY_MASKS | #cmd_ppp_profile_query_masks_req |
+ * | #CMD_PPP_CORE_QUERY_CPU_MASK | #cmd_ppp_core_query_cpu_mask_req |
+ * | #CMD_PPP_AVAILABLE_QUERY | - |
+ */
+struct mrq_ppp_profile_request {
+ /** @brief Sub-command ID from @ref mrq_ppp_profile_cmd. */
+ uint32_t cmd;
+ union {
+ struct cmd_ppp_profile_query_abi_req query_abi;
+ struct cmd_ppp_profile_query_masks_req ppp_profile_masks_req;
+ struct cmd_ppp_core_query_cpu_mask_req ppp_core_mask_req;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/**
+ * @brief Response payload for the #MRQ_PPP_PROFILE -command.
+ *
+ * | Sub-command | Response payload |
+ * |-------------------------------|----------------------------------------|
+ * | #CMD_PPP_PROFILE_QUERY_ABI | - |
+ * | #CMD_PPP_PROFILE_QUERY_MASKS | #cmd_ppp_profile_query_masks_resp |
+ * | #CMD_PPP_CORE_QUERY_CPU_MASK | #cmd_ppp_core_query_cpu_mask_resp |
+ * | #CMD_PPP_AVAILABLE_QUERY | #cmd_ppp_available_query_resp |
+ */
+struct mrq_ppp_profile_response {
+ uint32_t err;
+ union {
+ struct cmd_ppp_profile_query_masks_resp ppp_profile_masks_resp;
+ struct cmd_ppp_core_query_cpu_mask_resp ppp_core_mask_resp;
+ struct cmd_ppp_available_query_resp ppp_avail_query_resp;
+ } BPMP_UNION_ANON;
+} BPMP_ABI_PACKED;
+
+/** @} PPP */
+/** @endcond */
/**
* @addtogroup Error_Codes
@@ -3953,6 +6728,8 @@ struct mrq_gears_response {
#define BPMP_ENOSYS 38
/** @brief Invalid slot */
#define BPMP_EBADSLT 57
+/** @brief No data */
+#define BPMP_ENODATA 61
/** @brief Invalid message */
#define BPMP_EBADMSG 77
/** @brief Operation not supported */
--
2.52.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 2/5] firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function
2026-03-19 16:01 [PATCH 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:01 ` [PATCH 1/5] soc/tegra: Update BPMP ABI header Thierry Reding
@ 2026-03-19 16:01 ` Thierry Reding
2026-03-19 16:01 ` [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Thierry Reding
` (2 subsequent siblings)
4 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-19 16:01 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Some device tree bindings need to specify a parameter along with a BPMP
phandle reference to designate the ID associated with a given controller
that needs to interoperate with BPMP. Typically this is specified as an
extra cell in the nvidia,bpmp property, so add a helper to parse this ID
while resolving the phandle reference.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/firmware/tegra/bpmp.c | 34 ++++++++++++++++++++++++++++++++++
include/soc/tegra/bpmp.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c
index e74bba7ccc44..753472b53bd8 100644
--- a/drivers/firmware/tegra/bpmp.c
+++ b/drivers/firmware/tegra/bpmp.c
@@ -32,6 +32,40 @@ channel_to_ops(struct tegra_bpmp_channel *channel)
return bpmp->soc->ops;
}
+struct tegra_bpmp *tegra_bpmp_get_with_id(struct device *dev, unsigned int *id)
+{
+ struct platform_device *pdev;
+ struct of_phandle_args args;
+ struct tegra_bpmp *bpmp;
+ int err;
+
+ err = __of_parse_phandle_with_args(dev->of_node, "nvidia,bpmp", NULL,
+ 1, 0, &args);
+ if (err < 0)
+ return ERR_PTR(err);
+
+ pdev = of_find_device_by_node(args.np);
+ if (!pdev) {
+ bpmp = ERR_PTR(-ENODEV);
+ goto put;
+ }
+
+ bpmp = platform_get_drvdata(pdev);
+ if (!bpmp) {
+ bpmp = ERR_PTR(-EPROBE_DEFER);
+ put_device(&pdev->dev);
+ goto put;
+ }
+
+ if (id)
+ *id = args.args[0];
+
+put:
+ of_node_put(args.np);
+ return bpmp;
+}
+EXPORT_SYMBOL_GPL(tegra_bpmp_get_with_id);
+
struct tegra_bpmp *tegra_bpmp_get(struct device *dev)
{
struct platform_device *pdev;
diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h
index f5e4ac5b8cce..424188c100d9 100644
--- a/include/soc/tegra/bpmp.h
+++ b/include/soc/tegra/bpmp.h
@@ -127,6 +127,7 @@ struct tegra_bpmp_message {
#if IS_ENABLED(CONFIG_TEGRA_BPMP)
struct tegra_bpmp *tegra_bpmp_get(struct device *dev);
+struct tegra_bpmp *tegra_bpmp_get_with_id(struct device *dev, unsigned int *id);
void tegra_bpmp_put(struct tegra_bpmp *bpmp);
int tegra_bpmp_transfer_atomic(struct tegra_bpmp *bpmp,
struct tegra_bpmp_message *msg);
--
2.52.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-19 16:01 [PATCH 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:01 ` [PATCH 1/5] soc/tegra: Update BPMP ABI header Thierry Reding
2026-03-19 16:01 ` [PATCH 2/5] firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function Thierry Reding
@ 2026-03-19 16:01 ` Thierry Reding
2026-03-19 16:11 ` Krzysztof Kozlowski
` (2 more replies)
2026-03-19 16:01 ` [PATCH 4/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:01 ` [PATCH 5/5] arm64: tegra: Add PCI controllers on Tegra264 Thierry Reding
4 siblings, 3 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-19 16:01 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
The six PCIe controllers found on Tegra264 are of two types: one is used
for the internal GPU and therefore is not connected to a UPHY and the
remaining five controllers are typically routed to a PCI slot and have
additional controls for the physical link.
While these controllers can be switched into endpoint mode, this binding
describes the root complex mode only.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
.../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
new file mode 100644
index 000000000000..56d69de2788b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 PCIe controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra264-pcie
+
+ reg:
+ minItems: 4
+ maxItems: 5
+
+ reg-names:
+ minItems: 4
+ maxItems: 5
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+
+ dma-coherent: true
+
+ nvidia,bpmp:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ Must contain a pair of phandle (to the BPMP controller node) and
+ controller ID. The following are the controller IDs for each controller:
+
+ 0: C0
+ 1: C1
+ 2: C2
+ 3: C3
+ 4: C4
+ 5: C5
+ items:
+ - items:
+ - description: phandle to the BPMP controller node
+ - description: PCIe controller ID
+ maximum: 5
+
+unevaluatedProperties: false
+
+required:
+ - interrupt-map
+ - interrupt-map-mask
+ - iommu-map
+ - msi-map
+ - nvidia,bpmp
+
+allOf:
+ - $ref: /schemas/pci/pci-host-bridge.yaml#
+ - oneOf:
+ - description: C0 controller (no UPHY)
+ properties:
+ reg:
+ items:
+ - description: application layer registers
+ - description: transaction layer registers
+ - description: privileged transaction layer registers
+ - description: ECAM-compatible configuration space
+
+ reg-names:
+ items:
+ - const: xal
+ - const: xtl
+ - const: xtl-pri
+ - const: ecam
+
+ - description: C1-C5 controllers (with UPHY)
+ properties:
+ reg:
+ items:
+ - description: application layer registers
+ - description: transaction layer registers
+ - description: privileged transaction layer registers
+ - description: data link/physical layer registers
+ - description: ECAM-compatible configuration space
+
+ items:
+ - const: xal
+ - const: xtl
+ - const: xtl-pri
+ - const: xpl
+ - const: ecam
--
2.52.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 4/5] PCI: tegra: Add Tegra264 support
2026-03-19 16:01 [PATCH 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
` (2 preceding siblings ...)
2026-03-19 16:01 ` [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Thierry Reding
@ 2026-03-19 16:01 ` Thierry Reding
2026-03-19 16:14 ` Krzysztof Kozlowski
2026-03-19 17:46 ` Bjorn Helgaas
2026-03-19 16:01 ` [PATCH 5/5] arm64: tegra: Add PCI controllers on Tegra264 Thierry Reding
4 siblings, 2 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-19 16:01 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The
driver is very small, with its main purpose being to set up the address
translation registers and then creating a standard PCI host using ECAM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/pci/controller/Kconfig | 8 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-tegra264.c | 506 +++++++++++++++++++++++++
3 files changed, 515 insertions(+)
create mode 100644 drivers/pci/controller/pcie-tegra264.c
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index e72ac6934379..36abee65eca1 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -257,6 +257,14 @@ config PCI_TEGRA
Say Y here if you want support for the PCIe host controller found
on NVIDIA Tegra SoCs.
+config PCIE_TEGRA264
+ bool "NVIDIA Tegra264 PCIe controller"
+ depends on ARCH_TEGRA || COMPILE_TEST
+ depends on PCI_MSI
+ help
+ Say Y here if you want support for the PCIe host controller found
+ on NVIDIA Tegra264 SoCs.
+
config PCIE_RCAR_HOST
bool "Renesas R-Car PCIe controller (host mode)"
depends on ARCH_RENESAS || COMPILE_TEST
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index ac8db283f0fe..d478743b5142 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o
obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
+obj-$(CONFIG_PCIE_TEGRA264) += pcie-tegra264.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controller/pcie-tegra264.c
new file mode 100644
index 000000000000..0c8351b88941
--- /dev/null
+++ b/drivers/pci/controller/pcie-tegra264.c
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
+/*
+ * PCIe host controller driver for Tegra264 SoC
+ *
+ * Author: Manikanta Maddireddy <mmaddireddy@nvidia.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/init.h>
+#include <linux/interconnect.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci-ecam.h>
+#include <linux/pci.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <soc/tegra/bpmp.h>
+#include <soc/tegra/bpmp-abi.h>
+#include <soc/tegra/fuse.h>
+
+#include "../pci.h"
+
+#define PCIE_LINK_UP_DELAY 10000 /* 10 msec */
+#define PCIE_LINK_UP_TIMEOUT 1000000 /* 1 s */
+
+/* XAL registers */
+#define XAL_RC_ECAM_BASE_HI 0x00
+#define XAL_RC_ECAM_BASE_LO 0x04
+#define XAL_RC_ECAM_BUSMASK 0x08
+#define XAL_RC_IO_BASE_HI 0x0c
+#define XAL_RC_IO_BASE_LO 0x10
+#define XAL_RC_IO_LIMIT_HI 0x14
+#define XAL_RC_IO_LIMIT_LO 0x18
+#define XAL_RC_MEM_32BIT_BASE_HI 0x1c
+#define XAL_RC_MEM_32BIT_BASE_LO 0x20
+#define XAL_RC_MEM_32BIT_LIMIT_HI 0x24
+#define XAL_RC_MEM_32BIT_LIMIT_LO 0x28
+#define XAL_RC_MEM_64BIT_BASE_HI 0x2c
+#define XAL_RC_MEM_64BIT_BASE_LO 0x30
+#define XAL_RC_MEM_64BIT_LIMIT_HI 0x34
+#define XAL_RC_MEM_64BIT_LIMIT_LO 0x38
+#define XAL_RC_BAR_CNTL_STANDARD 0x40
+#define XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN BIT(0)
+#define XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN BIT(1)
+#define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN BIT(2)
+
+/* XTL registers */
+#define XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS 0x58
+#define XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS_DLL_ACTIVE BIT(29)
+
+#define XTL_RC_PCIE_CFG_LINK_STATUS 0x5a
+
+#define XTL_RC_MGMT_PERST_CONTROL 0x218
+#define XTL_RC_MGMT_PERST_CONTROL_PERST_O_N BIT(0)
+
+#define XTL_RC_MGMT_CLOCK_CONTROL 0x47C
+#define XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT BIT(9)
+
+struct tegra264_pcie {
+ struct device *dev;
+ bool link_state;
+
+ /* I/O memory */
+ void __iomem *xal;
+ void __iomem *xtl;
+ void __iomem *ecam;
+
+ /* bridge configuration */
+ struct pci_config_window *cfg;
+ struct pci_host_bridge *bridge;
+
+ /* wake IRQ */
+ struct gpio_desc *wake_gpio;
+ unsigned int wake_irq;
+
+ /* BPMP and bandwidth management */
+ struct icc_path *icc_path;
+ struct tegra_bpmp *bpmp;
+ u32 ctl_id;
+};
+
+static int tegra264_pcie_parse_dt(struct tegra264_pcie *pcie)
+{
+ int err;
+
+ pcie->wake_gpio = devm_gpiod_get_optional(pcie->dev, "nvidia,pex-wake",
+ GPIOD_IN);
+ if (IS_ERR(pcie->wake_gpio))
+ return PTR_ERR(pcie->wake_gpio);
+
+ if (pcie->wake_gpio) {
+ device_init_wakeup(pcie->dev, true);
+
+ err = gpiod_to_irq(pcie->wake_gpio);
+ if (err < 0) {
+ dev_err(pcie->dev, "failed to get wake IRQ: %d\n", err);
+ return err;
+ }
+
+ pcie->wake_irq = (unsigned int)err;
+ }
+
+ return 0;
+}
+
+static void tegra264_pcie_bpmp_set_rp_state(struct tegra264_pcie *pcie)
+{
+ struct tegra_bpmp_message msg;
+ struct mrq_pcie_request req;
+ int err;
+
+ memset(&req, 0, sizeof(req));
+
+ req.cmd = CMD_PCIE_RP_CONTROLLER_OFF;
+ req.rp_ctrlr_off.rp_controller = pcie->ctl_id;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.mrq = MRQ_PCIE;
+ msg.tx.data = &req;
+ msg.tx.size = sizeof(req);
+
+ err = tegra_bpmp_transfer(pcie->bpmp, &msg);
+ if (err)
+ dev_info(pcie->dev, "failed to turn off PCIe #%u: %d\n",
+ pcie->ctl_id, err);
+
+ if (msg.rx.ret)
+ dev_info(pcie->dev, "failed to turn off PCIe #%u: %d\n",
+ pcie->ctl_id, msg.rx.ret);
+}
+
+static void tegra264_pcie_icc_set(struct tegra264_pcie *pcie)
+{
+ u32 value, speed, width, bw;
+ int err;
+
+ value = readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS);
+ speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, value);
+ width = FIELD_GET(PCI_EXP_LNKSTA_NLW, value);
+
+ bw = width * (PCIE_SPEED2MBS_ENC(speed) / BITS_PER_BYTE);
+ value = MBps_to_icc(bw);
+
+ err = icc_set_bw(pcie->icc_path, bw, bw);
+ if (err < 0)
+ dev_err(pcie->dev,
+ "failed to request bandwidth (%u MBps): %d\n",
+ bw, err);
+}
+
+/*
+ * The various memory regions used by the controller (I/O, memory, ECAM) are
+ * set up during early boot and have hardware-level protections in place. If
+ * the DT ranges don't match what's been setup, the controller won't be able
+ * to write the address endpoints properly, so make sure to validate that DT
+ * and firmware programming agree on these ranges.
+ */
+static bool tegra264_pcie_check_ranges(struct platform_device *pdev)
+{
+ struct tegra264_pcie *pcie = platform_get_drvdata(pdev);
+ struct device_node *np = pcie->dev->of_node;
+ struct of_pci_range_parser parser;
+ phys_addr_t phys, limit, hi, lo;
+ struct of_pci_range range;
+ struct resource *res;
+ bool status = true;
+ u32 value;
+ int err;
+
+ err = of_pci_range_parser_init(&parser, np);
+ if (err < 0)
+ return false;
+
+ for_each_of_pci_range(&parser, &range) {
+ unsigned long type = range.flags & IORESOURCE_TYPE_BITS;
+ unsigned int addr_hi, addr_lo, limit_hi, limit_lo;
+ phys_addr_t start, end, mask;
+ const char *region = NULL;
+
+ end = range.cpu_addr + range.size - 1;
+ start = range.cpu_addr;
+
+ switch (type) {
+ case IORESOURCE_IO:
+ addr_hi = XAL_RC_IO_BASE_HI;
+ addr_lo = XAL_RC_IO_BASE_LO;
+ limit_hi = XAL_RC_IO_LIMIT_HI;
+ limit_lo = XAL_RC_IO_LIMIT_LO;
+ mask = SZ_64K - 1;
+ region = "I/O";
+ break;
+
+ case IORESOURCE_MEM:
+ if (range.flags & IORESOURCE_PREFETCH) {
+ addr_hi = XAL_RC_MEM_64BIT_BASE_HI;
+ addr_lo = XAL_RC_MEM_64BIT_BASE_LO;
+ limit_hi = XAL_RC_MEM_64BIT_LIMIT_HI;
+ limit_lo = XAL_RC_MEM_64BIT_LIMIT_LO;
+ region = "prefetchable memory";
+ } else {
+ addr_hi = XAL_RC_MEM_32BIT_BASE_HI;
+ addr_lo = XAL_RC_MEM_32BIT_BASE_LO;
+ limit_hi = XAL_RC_MEM_32BIT_LIMIT_HI;
+ limit_lo = XAL_RC_MEM_32BIT_LIMIT_LO;
+ region = "memory";
+ }
+
+ mask = SZ_1M - 1;
+ break;
+ }
+
+ /* not interested in anything that's not I/O or memory */
+ if (!region)
+ continue;
+
+ hi = readl(pcie->xal + addr_hi);
+ lo = readl(pcie->xal + addr_lo);
+ phys = hi << 32 | lo;
+
+ hi = readl(pcie->xal + limit_hi);
+ lo = readl(pcie->xal + limit_lo);
+ limit = hi << 32 | lo | mask;
+
+ if (phys != start || limit != end) {
+ dev_err(pcie->dev,
+ "%s region mismatch: %pap-%pap -> %pap-%pap\n",
+ region, &phys, &limit, &start, &end);
+ status = false;
+ }
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam");
+ if (!res)
+ return false;
+
+ hi = readl(pcie->xal + XAL_RC_ECAM_BASE_HI);
+ lo = readl(pcie->xal + XAL_RC_ECAM_BASE_LO);
+ phys = hi << 32 | lo;
+
+ value = readl(pcie->xal + XAL_RC_ECAM_BUSMASK);
+ limit = phys + ((value + 1) << 20) - 1;
+
+ if (phys != res->start || limit != res->end) {
+ dev_err(pcie->dev,
+ "ECAM region mismatch: %pap-%pap -> %pap-%pap\n",
+ &phys, &limit, &res->start, &res->end);
+ status = false;
+ }
+
+ return status;
+}
+
+static void tegra264_pcie_init(struct tegra264_pcie *pcie)
+{
+ u32 value;
+
+ if (!tegra_is_silicon()) {
+ dev_info(pcie->dev,
+ "skipping link state for PCIe #%u in simulation\n",
+ pcie->ctl_id);
+ pcie->link_state = true;
+ return;
+ }
+
+ /* Poll every 10 msec for 1 sec to link up */
+ readl_poll_timeout(pcie->ecam + XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS,
+ value, value & XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS_DLL_ACTIVE,
+ PCIE_LINK_UP_DELAY, PCIE_LINK_UP_TIMEOUT);
+
+ if (value & XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS_DLL_ACTIVE) {
+ /* Per PCIe r5.0, 6.6.1 wait for 100ms after DLL up */
+ msleep(100);
+ dev_info(pcie->dev, "PCIe #%u link is up (speed: %d)\n",
+ pcie->ctl_id, (value & 0xf0000) >> 16);
+ pcie->link_state = true;
+ tegra264_pcie_icc_set(pcie);
+ } else {
+ dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id);
+
+ value = readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL);
+
+ /** Set link state only when link fails and no hot-plug feature is present */
+ if ((value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT) == 0) {
+ dev_info(pcie->dev,
+ "PCIe #%u link is down and not hotplug-capable, turning off\n",
+ pcie->ctl_id);
+ tegra264_pcie_bpmp_set_rp_state(pcie);
+ pcie->link_state = false;
+ } else {
+ pcie->link_state = true;
+ }
+ }
+}
+
+static int tegra264_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pci_host_bridge *bridge;
+ struct tegra264_pcie *pcie;
+ struct resource_entry *bus;
+ struct resource *res;
+ int err;
+
+ bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie));
+ if (!bridge) {
+ dev_err(dev, "failed to allocate host bridge\n");
+ return -ENOMEM;
+ }
+
+ pcie = pci_host_bridge_priv(bridge);
+ platform_set_drvdata(pdev, pcie);
+ pcie->bridge = bridge;
+ pcie->dev = dev;
+
+ err = pinctrl_pm_select_default_state(dev);
+ if (err < 0) {
+ dev_err(dev, "failed to configure sideband pins: %d\n", err);
+ return err;
+ }
+
+ err = tegra264_pcie_parse_dt(pcie);
+ if (err < 0)
+ return dev_err_probe(dev, err, "failed to parse device tree");
+
+ pcie->xal = devm_platform_ioremap_resource_byname(pdev, "xal");
+ if (IS_ERR(pcie->xal)) {
+ err = PTR_ERR(pcie->xal);
+ dev_err(dev, "failed to map xal memory: %d\n", err);
+ return err;
+ }
+
+ pcie->xtl = devm_platform_ioremap_resource_byname(pdev, "xtl-pri");
+ if (IS_ERR(pcie->xtl)) {
+ err = PTR_ERR(pcie->xtl);
+ dev_err(dev, "failed to map xtl-pri memory: %d\n", err);
+ return err;
+ }
+
+ bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
+ if (!bus) {
+ dev_err(dev, "failed to get bus resource\n");
+ return -ENODEV;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam");
+ if (!res) {
+ dev_err(dev, "failed to get ECAM resource\n");
+ return -ENXIO;
+ }
+
+ pcie->icc_path = devm_of_icc_get(&pdev->dev, "write");
+ if (IS_ERR(pcie->icc_path))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->icc_path),
+ "failed to get ICC");
+
+ pcie->cfg = pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops);
+ if (IS_ERR(pcie->cfg)) {
+ err = PTR_ERR(pcie->cfg);
+ dev_err(dev, "failed to create ECAM: %d\n", err);
+ return err;
+ }
+
+ bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;
+ bridge->sysdata = pcie->cfg;
+ pcie->ecam = pcie->cfg->win;
+
+ /*
+ * Parse BPMP property only for silicon, as interaction with BPMP is
+ * not needed for other platforms.
+ */
+ if (tegra_is_silicon()) {
+ pcie->bpmp = tegra_bpmp_get_with_id(dev, &pcie->ctl_id);
+ if (IS_ERR(pcie->bpmp)) {
+ err = PTR_ERR(pcie->bpmp);
+ dev_err(dev, "failed to get BPMP: %d\n", err);
+ goto free;
+ }
+ }
+
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
+ /* sanity check that programmed ranges match what's in DT */
+ if (!tegra264_pcie_check_ranges(pdev)) {
+ err = -EINVAL;
+ goto put_pm;
+ }
+
+ tegra264_pcie_init(pcie);
+
+ if (!pcie->link_state)
+ goto put_pm;
+
+ err = pci_host_probe(bridge);
+ if (err < 0) {
+ dev_err(dev, "failed to register host: %d\n", err);
+ goto put_pm;
+ }
+
+ return err;
+
+put_pm:
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
+ if (tegra_is_silicon())
+ tegra_bpmp_put(pcie->bpmp);
+free:
+ pci_ecam_free(pcie->cfg);
+ return err;
+}
+
+static void tegra264_pcie_remove(struct platform_device *pdev)
+{
+ struct tegra264_pcie *pcie = platform_get_drvdata(pdev);
+
+ /*
+ * If we undo tegra264_pcie_init() then link goes down and need
+ * controller reset to bring up the link again. Remove intention is
+ * to clean up the root bridge and re-enumerate during bind.
+ */
+ pci_lock_rescan_remove();
+ pci_stop_root_bus(pcie->bridge->bus);
+ pci_remove_root_bus(pcie->bridge->bus);
+ pci_unlock_rescan_remove();
+
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+ if (tegra_is_silicon())
+ tegra_bpmp_put(pcie->bpmp);
+
+ pci_ecam_free(pcie->cfg);
+}
+
+static int tegra264_pcie_suspend_noirq(struct device *dev)
+{
+ struct tegra264_pcie *pcie = dev_get_drvdata(dev);
+ int err;
+
+ if (pcie->wake_gpio && device_may_wakeup(dev)) {
+ err = enable_irq_wake(pcie->wake_irq);
+ if (err < 0)
+ dev_err(dev, "failed to enable wake IRQ: %d\n", err);
+ }
+
+ return 0;
+}
+
+static int tegra264_pcie_resume_noirq(struct device *dev)
+{
+ struct tegra264_pcie *pcie = dev_get_drvdata(dev);
+ int err;
+
+ if (pcie->wake_gpio && device_may_wakeup(dev)) {
+ err = disable_irq_wake(pcie->wake_irq);
+ if (err < 0)
+ dev_err(dev, "failed to disable wake IRQ: %d\n", err);
+ }
+
+ if (pcie->link_state == false)
+ return 0;
+
+ tegra264_pcie_init(pcie);
+
+ return 0;
+}
+
+static const struct dev_pm_ops tegra264_pcie_pm_ops = {
+ .resume_noirq = tegra264_pcie_resume_noirq,
+ .suspend_noirq = tegra264_pcie_suspend_noirq,
+};
+
+static const struct of_device_id tegra264_pcie_of_match[] = {
+ {
+ .compatible = "nvidia,tegra264-pcie",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, tegra264_pcie_of_match);
+
+static struct platform_driver tegra264_pcie_driver = {
+ .probe = tegra264_pcie_probe,
+ .remove = tegra264_pcie_remove,
+ .driver = {
+ .name = "tegra264-pcie",
+ .pm = &tegra264_pcie_pm_ops,
+ .of_match_table = tegra264_pcie_of_match,
+ },
+};
+module_platform_driver(tegra264_pcie_driver);
+
+MODULE_AUTHOR("Manikanta Maddireddy <mmaddireddy@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra264 PCIe host controller driver");
+MODULE_LICENSE("GPL");
--
2.52.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 5/5] arm64: tegra: Add PCI controllers on Tegra264
2026-03-19 16:01 [PATCH 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
` (3 preceding siblings ...)
2026-03-19 16:01 ` [PATCH 4/5] PCI: tegra: Add Tegra264 support Thierry Reding
@ 2026-03-19 16:01 ` Thierry Reding
4 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-19 16:01 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
From: Thierry Reding <treding@nvidia.com>
A total of six PCIe controllers can be found on Tegra264. One of them is
used internally for the integrated GPU while the other five can go to a
variety of connectors like full PCIe slots or M.2.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 248 ++++++++++++++++++++---
1 file changed, 221 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 24cc2c51a272..6fb0bf4bf2e2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -32,7 +32,7 @@ bus@0 {
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;
+ ranges = <0x00 0x00000000 0x00 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */
misc@100000 {
compatible = "nvidia,tegra234-misc";
@@ -3356,9 +3356,10 @@ bus@8100000000 {
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */
- <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
- <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
+ ranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable memory (32-bit, 512 MiB) */
+ <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */
+ <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
smmu1: iommu@5000000 {
compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
@@ -3402,23 +3403,23 @@ cmdqv2: cmdqv@6200000 {
mc: memory-controller@8020000 {
compatible = "nvidia,tegra264-mc";
- reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */
- <0x00 0x8040000 0x0 0x20000>, /* MC 0 */
- <0x00 0x8060000 0x0 0x20000>, /* MC 1 */
- <0x00 0x8080000 0x0 0x20000>, /* MC 2 */
- <0x00 0x80a0000 0x0 0x20000>, /* MC 3 */
- <0x00 0x80c0000 0x0 0x20000>, /* MC 4 */
- <0x00 0x80e0000 0x0 0x20000>, /* MC 5 */
- <0x00 0x8100000 0x0 0x20000>, /* MC 6 */
- <0x00 0x8120000 0x0 0x20000>, /* MC 7 */
- <0x00 0x8140000 0x0 0x20000>, /* MC 8 */
- <0x00 0x8160000 0x0 0x20000>, /* MC 9 */
- <0x00 0x8180000 0x0 0x20000>, /* MC 10 */
- <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */
- <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */
- <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */
- <0x00 0x8200000 0x0 0x20000>, /* MC 14 */
- <0x00 0x8220000 0x0 0x20000>; /* MC 15 */
+ reg = <0x000 0x8020000 0x0 0x20000>, /* MC broadcast */
+ <0x000 0x8040000 0x0 0x20000>, /* MC 0 */
+ <0x000 0x8060000 0x0 0x20000>, /* MC 1 */
+ <0x000 0x8080000 0x0 0x20000>, /* MC 2 */
+ <0x000 0x80a0000 0x0 0x20000>, /* MC 3 */
+ <0x000 0x80c0000 0x0 0x20000>, /* MC 4 */
+ <0x000 0x80e0000 0x0 0x20000>, /* MC 5 */
+ <0x000 0x8100000 0x0 0x20000>, /* MC 6 */
+ <0x000 0x8120000 0x0 0x20000>, /* MC 7 */
+ <0x000 0x8140000 0x0 0x20000>, /* MC 8 */
+ <0x000 0x8160000 0x0 0x20000>, /* MC 9 */
+ <0x000 0x8180000 0x0 0x20000>, /* MC 10 */
+ <0x000 0x81a0000 0x0 0x20000>, /* MC 11 */
+ <0x000 0x81c0000 0x0 0x20000>, /* MC 12 */
+ <0x000 0x81e0000 0x0 0x20000>, /* MC 13 */
+ <0x000 0x8200000 0x0 0x20000>, /* MC 14 */
+ <0x000 0x8220000 0x0 0x20000>; /* MC 15 */
reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7", "ch8", "ch9",
"ch10", "ch11", "ch12", "ch13", "ch14",
@@ -3437,12 +3438,12 @@ mc: memory-controller@8020000 {
#size-cells = <2>;
/* limit the DMA range for memory clients to [39:0] */
- dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
+ dma-ranges = <0x000 0x0 0x000 0x0 0x100 0x0>;
emc: external-memory-controller@8800000 {
compatible = "nvidia,tegra264-emc";
- reg = <0x00 0x8800000 0x0 0x20000>,
- <0x00 0x8890000 0x0 0x20000>;
+ reg = <0x000 0x8800000 0x0 0x20000>,
+ <0x000 0x8890000 0x0 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA264_CLK_EMC>,
<&bpmp TEGRA264_CLK_DBB_UPHY0>;
@@ -3493,6 +3494,38 @@ cmdqv4: cmdqv@b200000 {
status = "disabled";
};
+ pci@c000000 {
+ compatible = "nvidia,tegra264-pcie";
+ reg = <0x00 0x0c000000 0x0 0x00004000>,
+ <0x00 0x0c004000 0x0 0x00001000>,
+ <0x00 0x0c005000 0x0 0x00001000>,
+ <0xd0 0xb0000000 0x0 0x10000000>;
+ reg-names = "xal", "xtl", "xtl-pri", "ecam";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0x00>;
+ #interrupt-cells = <0x1>;
+
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommu-map = <0x0 &smmu2 0x10000 0x10000>;
+ msi-map = <0x0 &its 0x210000 0x10000>;
+ dma-coherent;
+
+ ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */
+ <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */
+ <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
+ bus-range = <0x0 0xff>;
+
+ nvidia,bpmp = <&bpmp 0>;
+ status = "disabled";
+ };
+
i2c14: i2c@c410000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c410000 0x0 0x10000>;
@@ -3720,7 +3753,7 @@ bus@8800000000 {
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;
+ ranges = <0x00 0x00000000 0x88 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */
smmu3: iommu@6000000 {
compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
@@ -3765,8 +3798,169 @@ bus@a800000000 {
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */
- <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
+ ranges = <0x00 0x00000000 0xa8 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
+ <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
+
+ pci@8400000 {
+ compatible = "nvidia,tegra264-pcie";
+ reg = <0x00 0x08400000 0x0 0x00004000>,
+ <0x00 0x08404000 0x0 0x00001000>,
+ <0x00 0x08405000 0x0 0x00001000>,
+ <0x00 0x08410000 0x0 0x00010000>,
+ <0xa8 0xb0000000 0x0 0x10000000>;
+ reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0x01>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 IRQ_TYPE_LEVEL_HIGH>, /* INTA */
+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 IRQ_TYPE_LEVEL_HIGH>, /* INTB */
+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 IRQ_TYPE_LEVEL_HIGH>, /* INTC */
+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 IRQ_TYPE_LEVEL_HIGH>; /* INTD */
+
+ iommu-map = <0x0 &smmu1 0x10000 0x10000>;
+ msi-map = <0x0 &its 0x110000 0x10000>;
+ dma-coherent;
+
+ ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, /* I/O */
+ <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-prefetchable memory */
+ <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
+ bus-range = <0x00 0xff>;
+
+ nvidia,bpmp = <&bpmp 1>;
+ status = "disabled";
+ };
+
+ pci@8420000 {
+ compatible = "nvidia,tegra264-pcie";
+ reg = <0x00 0x08420000 0x0 0x00004000>,
+ <0x00 0x08424000 0x0 0x00001000>,
+ <0x00 0x08425000 0x0 0x00001000>,
+ <0x00 0x08430000 0x0 0x00010000>,
+ <0xb0 0xb0000000 0x0 0x10000000>;
+ reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0x02>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 917 IRQ_TYPE_LEVEL_HIGH>, /* INTA */
+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 918 IRQ_TYPE_LEVEL_HIGH>, /* INTB */
+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 919 IRQ_TYPE_LEVEL_HIGH>, /* INTC */
+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 920 IRQ_TYPE_LEVEL_HIGH>; /* INTD */
+
+ iommu-map = <0x0 &smmu1 0x20000 0x10000>;
+ msi-map = <0x0 &its 0x120000 0x10000>;
+ dma-coherent;
+
+ ranges = <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>, /* I/O */
+ <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-prefetchable memory */
+ <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
+ bus-range = <0x00 0xff>;
+
+ nvidia,bpmp = <&bpmp 2>;
+ status = "disabled";
+ };
+
+ pci@8440000 {
+ compatible = "nvidia,tegra264-pcie";
+ reg = <0x00 0x08440000 0x0 0x00004000>,
+ <0x00 0x08444000 0x0 0x00001000>,
+ <0x00 0x08445000 0x0 0x00001000>,
+ <0x00 0x08450000 0x0 0x00010000>,
+ <0xb8 0xb0000000 0x0 0x10000000>;
+ reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0x03>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 926 IRQ_TYPE_LEVEL_HIGH>, /* INTA */
+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 927 IRQ_TYPE_LEVEL_HIGH>, /* INTB */
+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 928 IRQ_TYPE_LEVEL_HIGH>, /* INTC */
+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 929 IRQ_TYPE_LEVEL_HIGH>; /* INTD */
+
+ iommu-map = <0x0 &smmu1 0x30000 0x10000>;
+ msi-map = <0x0 &its 0x130000 0x10000>;
+ dma-coherent;
+
+ ranges = <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>, /* I/O */
+ <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-prefetchable memory */
+ <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
+ bus-range = <0x00 0xff>;
+
+ nvidia,bpmp = <&bpmp 3>;
+ status = "disabled";
+ };
+
+ pci@8460000 {
+ compatible = "nvidia,tegra264-pcie";
+ reg = <0x00 0x08460000 0x0 0x00004000>,
+ <0x00 0x08464000 0x0 0x00001000>,
+ <0x00 0x08465000 0x0 0x00001000>,
+ <0x00 0x08470000 0x0 0x00010000>,
+ <0xc0 0xb0000000 0x0 0x10000000>;
+ reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0x04>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 935 IRQ_TYPE_LEVEL_HIGH>, /* INTA */
+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 936 IRQ_TYPE_LEVEL_HIGH>, /* INTB */
+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 937 IRQ_TYPE_LEVEL_HIGH>, /* INTC */
+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 938 IRQ_TYPE_LEVEL_HIGH>; /* INTD */
+
+ iommu-map = <0x0 &smmu1 0x40000 0x10000>;
+ msi-map = <0x0 &its 0x140000 0x10000>;
+ dma-coherent;
+
+ ranges = <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>, /* I/O */
+ <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-prefetchable memory */
+ <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
+ bus-range = <0x00 0xff>;
+
+ nvidia,bpmp = <&bpmp 4>;
+ status = "disabled";
+ };
+
+ pci@8480000 {
+ compatible = "nvidia,tegra264-pcie";
+ reg = <0x00 0x08480000 0x0 0x00004000>,
+ <0x00 0x08484000 0x0 0x00001000>,
+ <0x00 0x08485000 0x0 0x00001000>,
+ <0x00 0x08490000 0x0 0x00010000>,
+ <0xc8 0xb0000000 0x0 0x10000000>;
+ reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0x05>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 944 IRQ_TYPE_LEVEL_HIGH>, /* INTA */
+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 945 IRQ_TYPE_LEVEL_HIGH>, /* INTB */
+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 946 IRQ_TYPE_LEVEL_HIGH>, /* INTC */
+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 947 IRQ_TYPE_LEVEL_HIGH>; /* INTD */
+
+ iommu-map = <0x0 &smmu1 0x50000 0x10000>;
+ msi-map = <0x0 &its 0x150000 0x10000>;
+ dma-coherent;
+
+ ranges = <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>, /* I/O */
+ <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-prefetchable memory */
+ <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */
+ bus-range = <0x00 0xff>;
+
+ nvidia,bpmp = <&bpmp 5>;
+ status = "disabled";
+ };
};
cpus {
--
2.52.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-19 16:01 ` [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Thierry Reding
@ 2026-03-19 16:11 ` Krzysztof Kozlowski
2026-03-20 10:56 ` Thierry Reding
2026-03-19 17:53 ` Rob Herring (Arm)
2026-03-19 21:26 ` Rob Herring
2 siblings, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-19 16:11 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
On 19/03/2026 17:01, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The six PCIe controllers found on Tegra264 are of two types: one is used
> for the internal GPU and therefore is not connected to a UPHY and the
> remaining five controllers are typically routed to a PCI slot and have
> additional controls for the physical link.
>
> While these controllers can be switched into endpoint mode, this binding
> describes the root complex mode only.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> 1 file changed, 92 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> new file mode 100644
> index 000000000000..56d69de2788b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra264 PCIe controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> + compatible:
> + const: nvidia,tegra264-pcie
> +
> + reg:
> + minItems: 4
> + maxItems: 5
> +
> + reg-names:
> + minItems: 4
> + maxItems: 5
> +
> + interrupts:
> + minItems: 1
> + maxItems: 4
> +
> + dma-coherent: true
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle (to the BPMP controller node) and
> + controller ID. The following are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - description: phandle to the BPMP controller node
> + - description: PCIe controller ID
> + maximum: 5
> +
> +unevaluatedProperties: false
This goes before example
> +
> +required:
> + - interrupt-map
> + - interrupt-map-mask
> + - iommu-map
> + - msi-map
> + - nvidia,bpmp
> +
> +allOf:
> + - $ref: /schemas/pci/pci-host-bridge.yaml#
> + - oneOf:
> + - description: C0 controller (no UPHY)
It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
> + properties:
> + reg:
> + items:
> + - description: application layer registers
> + - description: transaction layer registers
> + - description: privileged transaction layer registers
> + - description: ECAM-compatible configuration space
> +
> + reg-names:
> + items:
> + - const: xal
> + - const: xtl
> + - const: xtl-pri
> + - const: ecam
> +
> + - description: C1-C5 controllers (with UPHY)
> + properties:
> + reg:
> + items:
> + - description: application layer registers
> + - description: transaction layer registers
> + - description: privileged transaction layer registers
> + - description: data link/physical layer registers
> + - description: ECAM-compatible configuration space
> +
> + items:
> + - const: xal
> + - const: xtl
> + - const: xtl-pri
> + - const: xpl
> + - const: ecam
All of above are part of top level.
And speaking about example - where is it? How can you then test (verify)
this?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/5] PCI: tegra: Add Tegra264 support
2026-03-19 16:01 ` [PATCH 4/5] PCI: tegra: Add Tegra264 support Thierry Reding
@ 2026-03-19 16:14 ` Krzysztof Kozlowski
2026-03-20 10:39 ` Thierry Reding
2026-03-19 17:46 ` Bjorn Helgaas
1 sibling, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-19 16:14 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
On 19/03/2026 17:01, Thierry Reding wrote:
> obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
> obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
> diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controller/pcie-tegra264.c
> new file mode 100644
> index 000000000000..0c8351b88941
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-tegra264.c
> @@ -0,0 +1,506 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +// SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
Don't use that tag, please, but standard Copyright.
> +static int tegra264_pcie_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct pci_host_bridge *bridge;
> + struct tegra264_pcie *pcie;
> + struct resource_entry *bus;
> + struct resource *res;
> + int err;
> +
> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie));
> + if (!bridge) {
> + dev_err(dev, "failed to allocate host bridge\n");
> + return -ENOMEM;
> + }
> +
> + pcie = pci_host_bridge_priv(bridge);
> + platform_set_drvdata(pdev, pcie);
> + pcie->bridge = bridge;
> + pcie->dev = dev;
> +
> + err = pinctrl_pm_select_default_state(dev);
> + if (err < 0) {
> + dev_err(dev, "failed to configure sideband pins: %d\n", err);
> + return err;
> + }
> +
> + err = tegra264_pcie_parse_dt(pcie);
> + if (err < 0)
> + return dev_err_probe(dev, err, "failed to parse device tree");
> +
> + pcie->xal = devm_platform_ioremap_resource_byname(pdev, "xal");
> + if (IS_ERR(pcie->xal)) {
> + err = PTR_ERR(pcie->xal);
> + dev_err(dev, "failed to map xal memory: %d\n", err);
> + return err;
What's with this syntax here? This is just one call return
dev_err_probe. Looks like you are sending us some old code, instead of
use recent drivers starting point.
> + }
> +
> + pcie->xtl = devm_platform_ioremap_resource_byname(pdev, "xtl-pri");
> + if (IS_ERR(pcie->xtl)) {
> + err = PTR_ERR(pcie->xtl);
> + dev_err(dev, "failed to map xtl-pri memory: %d\n", err);
> + return err;
> + }
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] soc/tegra: Update BPMP ABI header
2026-03-19 16:01 ` [PATCH 1/5] soc/tegra: Update BPMP ABI header Thierry Reding
@ 2026-03-19 16:15 ` Krzysztof Kozlowski
2026-03-20 9:34 ` Thierry Reding
0 siblings, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-19 16:15 UTC (permalink / raw)
To: Thierry Reding, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Jon Hunter, linux-pci, devicetree, linux-tegra
On 19/03/2026 17:01, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> This update primarily adds various new commands and MRQs for Tegra264,
> but also contains a few new annotations and fixes.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> include/soc/tegra/bpmp-abi.h | 4565 +++++++++++++++++++++++++++-------
> 1 file changed, 3671 insertions(+), 894 deletions(-)
>
> diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
> index 39bb3f87e28d..6cf6442395f1 100644
> --- a/include/soc/tegra/bpmp-abi.h
> +++ b/include/soc/tegra/bpmp-abi.h
> @@ -1,6 +1,6 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> /*
> - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
> + * SPDX-FileCopyrightText: Copyright (c) 2014-2025, NVIDIA CORPORATION. All rights reserved.
You just replaced correct syntax with discouraged (as in not welcomed
upstream) SPDX tag.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/5] PCI: tegra: Add Tegra264 support
2026-03-19 16:01 ` [PATCH 4/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:14 ` Krzysztof Kozlowski
@ 2026-03-19 17:46 ` Bjorn Helgaas
2026-03-20 10:34 ` Thierry Reding
1 sibling, 1 reply; 25+ messages in thread
From: Bjorn Helgaas @ 2026-03-19 17:46 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
On Thu, Mar 19, 2026 at 05:01:08PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The
> driver is very small, with its main purpose being to set up the address
> translation registers and then creating a standard PCI host using ECAM.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/pci/controller/Kconfig | 8 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-tegra264.c | 506 +++++++++++++++++++++++++
> 3 files changed, 515 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-tegra264.c
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index e72ac6934379..36abee65eca1 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -257,6 +257,14 @@ config PCI_TEGRA
> Say Y here if you want support for the PCIe host controller found
> on NVIDIA Tegra SoCs.
Should the PCI_TEGRA menu item ("NVIDIA Tegra PCIe controller") and
this text be clarified somehow to make them clearly separate?
> +config PCIE_TEGRA264
> + bool "NVIDIA Tegra264 PCIe controller"
> + depends on ARCH_TEGRA || COMPILE_TEST
> + depends on PCI_MSI
> + help
> + Say Y here if you want support for the PCIe host controller found
> + on NVIDIA Tegra264 SoCs.
> + * PCIe host controller driver for Tegra264 SoC
> + *
> + * Author: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Manikanta doesn't appear in the signed-off-by or other tags above.
Not really an issue for me; just a question of whether this is
accurate.
> +#define PCIE_LINK_UP_DELAY 10000 /* 10 msec */
> +#define PCIE_LINK_UP_TIMEOUT 1000000 /* 1 s */
Use something from drivers/pci/pci.h if possible. If not, please add
units suffixes to the name, e.g., it looks like these are in "_US".
PCIE_LINK_WAIT_MAX_RETRIES and PCIE_LINK_WAIT_SLEEP_MS look like
they're used in similar ways in other drivers.
> +/* XAL registers */
> +#define XAL_RC_ECAM_BASE_HI 0x00
> +#define XAL_RC_ECAM_BASE_LO 0x04
> +#define XAL_RC_ECAM_BUSMASK 0x08
> +#define XAL_RC_IO_BASE_HI 0x0c
> ...
> +#define XTL_RC_MGMT_CLOCK_CONTROL 0x47C
Inconsistent use of upper/lower-case hex with above.
> +struct tegra264_pcie {
> + struct device *dev;
> + bool link_state;
"link_state" being true/false doesn't read quite right because
true/false isn't a "state". I guess true means "link is up"?
> +static int tegra264_pcie_parse_dt(struct tegra264_pcie *pcie)
> +{
> + int err;
> +
> + pcie->wake_gpio = devm_gpiod_get_optional(pcie->dev, "nvidia,pex-wake",
> + GPIOD_IN);
> + if (IS_ERR(pcie->wake_gpio))
> + return PTR_ERR(pcie->wake_gpio);
> +
> + if (pcie->wake_gpio) {
> + device_init_wakeup(pcie->dev, true);
> +
> + err = gpiod_to_irq(pcie->wake_gpio);
> + if (err < 0) {
> + dev_err(pcie->dev, "failed to get wake IRQ: %d\n", err);
Does %pe work here (and below)?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/core-api/printk-formats.rst?id=v6.19#n96
> +static void tegra264_pcie_bpmp_set_rp_state(struct tegra264_pcie *pcie)
> +{
> + struct tegra_bpmp_message msg;
> + struct mrq_pcie_request req;
> + int err;
> +
> + memset(&req, 0, sizeof(req));
I think "struct mrq_pcie_request req = {}" is equivalent, also for
msg. No real preference from me.
> +static void tegra264_pcie_init(struct tegra264_pcie *pcie)
> +{
> + u32 value;
> +
> + if (!tegra_is_silicon()) {
> + dev_info(pcie->dev,
> + "skipping link state for PCIe #%u in simulation\n",
> + pcie->ctl_id);
> + pcie->link_state = true;
> + return;
> + }
> +
> + /* Poll every 10 msec for 1 sec to link up */
> + readl_poll_timeout(pcie->ecam + XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS,
> + value, value & XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS_DLL_ACTIVE,
> + PCIE_LINK_UP_DELAY, PCIE_LINK_UP_TIMEOUT);
> +
> + if (value & XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS_DLL_ACTIVE) {
> + /* Per PCIe r5.0, 6.6.1 wait for 100ms after DLL up */
> + msleep(100);
Looks like possibly PCIE_RESET_CONFIG_WAIT_MS?
> + dev_info(pcie->dev, "PCIe #%u link is up (speed: %d)\n",
> + pcie->ctl_id, (value & 0xf0000) >> 16);
> + pcie->link_state = true;
> + tegra264_pcie_icc_set(pcie);
> + } else {
> + dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id);
> +
> + value = readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL);
> +
> + /** Set link state only when link fails and no hot-plug feature is present */
/* (not /**), and wrap to fit in 78 columns.
> + if ((value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT) == 0) {
> + dev_info(pcie->dev,
> + "PCIe #%u link is down and not hotplug-capable, turning off\n",
> + pcie->ctl_id);
> + tegra264_pcie_bpmp_set_rp_state(pcie);
> + pcie->link_state = false;
> + } else {
> + pcie->link_state = true;
> + }
> + }
> +}
> +
> +static int tegra264_pcie_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct pci_host_bridge *bridge;
> + struct tegra264_pcie *pcie;
> + struct resource_entry *bus;
> + struct resource *res;
> + int err;
> +
> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie));
> + if (!bridge) {
> + dev_err(dev, "failed to allocate host bridge\n");
> + return -ENOMEM;
Looks like this and others below could use:
if (!bridge)
return dev_err_probe(dev, -ENOMEM, "failed ...");
> +static const struct dev_pm_ops tegra264_pcie_pm_ops = {
> + .resume_noirq = tegra264_pcie_resume_noirq,
> + .suspend_noirq = tegra264_pcie_suspend_noirq,
> +};
Should this use DEFINE_NOIRQ_DEV_PM_OPS() or similar to avoid warnings
when CONFIG_PM_SLEEP, etc are not enabled?
> +static const struct of_device_id tegra264_pcie_of_match[] = {
> + {
> + .compatible = "nvidia,tegra264-pcie",
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, tegra264_pcie_of_match);
> +
> +static struct platform_driver tegra264_pcie_driver = {
> + .probe = tegra264_pcie_probe,
> + .remove = tegra264_pcie_remove,
> + .driver = {
> + .name = "tegra264-pcie",
> + .pm = &tegra264_pcie_pm_ops,
> + .of_match_table = tegra264_pcie_of_match,
> + },
> +};
> +module_platform_driver(tegra264_pcie_driver);
> +
> +MODULE_AUTHOR("Manikanta Maddireddy <mmaddireddy@nvidia.com>");
> +MODULE_DESCRIPTION("NVIDIA Tegra264 PCIe host controller driver");
> +MODULE_LICENSE("GPL");
> --
> 2.52.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-19 16:01 ` [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Thierry Reding
2026-03-19 16:11 ` Krzysztof Kozlowski
@ 2026-03-19 17:53 ` Rob Herring (Arm)
2026-03-19 21:26 ` Rob Herring
2 siblings, 0 replies; 25+ messages in thread
From: Rob Herring (Arm) @ 2026-03-19 17:53 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-tegra, Krzysztof Kozlowski, Manivannan Sadhasivam,
Conor Dooley, Bjorn Helgaas, Jon Hunter, devicetree,
Lorenzo Pieralisi, Krzysztof Wilczyński, linux-pci
On Thu, 19 Mar 2026 17:01:07 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The six PCIe controllers found on Tegra264 are of two types: one is used
> for the internal GPU and therefore is not connected to a UPHY and the
> remaining five controllers are typically routed to a PCI slot and have
> additional controls for the physical link.
>
> While these controllers can be switched into endpoint mode, this binding
> describes the root complex mode only.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> 1 file changed, 92 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml:61:5: [warning] wrong indentation: expected 6 but found 4 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260319160110.2131954-4-thierry.reding@kernel.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-19 16:01 ` [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Thierry Reding
2026-03-19 16:11 ` Krzysztof Kozlowski
2026-03-19 17:53 ` Rob Herring (Arm)
@ 2026-03-19 21:26 ` Rob Herring
2026-03-20 9:39 ` Thierry Reding
2 siblings, 1 reply; 25+ messages in thread
From: Rob Herring @ 2026-03-19 21:26 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Jon Hunter, linux-pci, devicetree, linux-tegra
On Thu, Mar 19, 2026 at 11:01 AM Thierry Reding
<thierry.reding@kernel.org> wrote:
>
> From: Thierry Reding <treding@nvidia.com>
>
> The six PCIe controllers found on Tegra264 are of two types: one is used
> for the internal GPU and therefore is not connected to a UPHY and the
> remaining five controllers are typically routed to a PCI slot and have
> additional controls for the physical link.
>
> While these controllers can be switched into endpoint mode, this binding
> describes the root complex mode only.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> 1 file changed, 92 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> new file mode 100644
> index 000000000000..56d69de2788b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra264 PCIe controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> + compatible:
> + const: nvidia,tegra264-pcie
> +
> + reg:
> + minItems: 4
> + maxItems: 5
> +
> + reg-names:
> + minItems: 4
> + maxItems: 5
> +
> + interrupts:
> + minItems: 1
> + maxItems: 4
> +
> + dma-coherent: true
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle (to the BPMP controller node) and
> + controller ID. The following are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - description: phandle to the BPMP controller node
> + - description: PCIe controller ID
> + maximum: 5
> +
> +unevaluatedProperties: false
> +
> +required:
> + - interrupt-map
> + - interrupt-map-mask
> + - iommu-map
> + - msi-map
> + - nvidia,bpmp
> +
> +allOf:
> + - $ref: /schemas/pci/pci-host-bridge.yaml#
> + - oneOf:
> + - description: C0 controller (no UPHY)
> + properties:
> + reg:
> + items:
> + - description: application layer registers
> + - description: transaction layer registers
> + - description: privileged transaction layer registers
> + - description: ECAM-compatible configuration space
> +
> + reg-names:
> + items:
> + - const: xal
> + - const: xtl
> + - const: xtl-pri
> + - const: ecam
> +
> + - description: C1-C5 controllers (with UPHY)
> + properties:
> + reg:
> + items:
> + - description: application layer registers
> + - description: transaction layer registers
> + - description: privileged transaction layer registers
> + - description: data link/physical layer registers
> + - description: ECAM-compatible configuration space
> +
> + items:
> + - const: xal
> + - const: xtl
> + - const: xtl-pri
> + - const: xpl
Put this entry last since it is the optional one. Then you can move
all of this to the top-level and get rid of the duplication.
> + - const: ecam
> --
> 2.52.0
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] soc/tegra: Update BPMP ABI header
2026-03-19 16:15 ` Krzysztof Kozlowski
@ 2026-03-20 9:34 ` Thierry Reding
2026-03-20 9:44 ` Krzysztof Kozlowski
2026-03-20 12:46 ` Krzysztof Kozlowski
0 siblings, 2 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-20 9:34 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 1392 bytes --]
On Thu, Mar 19, 2026 at 05:15:56PM +0100, Krzysztof Kozlowski wrote:
> On 19/03/2026 17:01, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > This update primarily adds various new commands and MRQs for Tegra264,
> > but also contains a few new annotations and fixes.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > include/soc/tegra/bpmp-abi.h | 4565 +++++++++++++++++++++++++++-------
> > 1 file changed, 3671 insertions(+), 894 deletions(-)
> >
> > diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
> > index 39bb3f87e28d..6cf6442395f1 100644
> > --- a/include/soc/tegra/bpmp-abi.h
> > +++ b/include/soc/tegra/bpmp-abi.h
> > @@ -1,6 +1,6 @@
> > -/* SPDX-License-Identifier: GPL-2.0-only */
> > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> > /*
> > - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
> > + * SPDX-FileCopyrightText: Copyright (c) 2014-2025, NVIDIA CORPORATION. All rights reserved.
>
> You just replaced correct syntax with discouraged (as in not welcomed
> upstream) SPDX tag.
Fair enough, I'm dropping the tag. I didn't know it was actively
discouraged and I don't see this documented anywhere. I suppose I should
go and drop similar tags from various other sources. Looks like we've
been introducing this recently for Tegra.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-19 21:26 ` Rob Herring
@ 2026-03-20 9:39 ` Thierry Reding
2026-03-20 13:06 ` Rob Herring
0 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2026-03-20 9:39 UTC (permalink / raw)
To: Rob Herring
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Jon Hunter, linux-pci, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 4742 bytes --]
On Thu, Mar 19, 2026 at 04:26:31PM -0500, Rob Herring wrote:
> On Thu, Mar 19, 2026 at 11:01 AM Thierry Reding
> <thierry.reding@kernel.org> wrote:
> >
> > From: Thierry Reding <treding@nvidia.com>
> >
> > The six PCIe controllers found on Tegra264 are of two types: one is used
> > for the internal GPU and therefore is not connected to a UPHY and the
> > remaining five controllers are typically routed to a PCI slot and have
> > additional controls for the physical link.
> >
> > While these controllers can be switched into endpoint mode, this binding
> > describes the root complex mode only.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> > 1 file changed, 92 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > new file mode 100644
> > index 000000000000..56d69de2788b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > @@ -0,0 +1,92 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra264 PCIe controller
> > +
> > +maintainers:
> > + - Thierry Reding <thierry.reding@gmail.com>
> > + - Jon Hunter <jonathanh@nvidia.com>
> > +
> > +properties:
> > + compatible:
> > + const: nvidia,tegra264-pcie
> > +
> > + reg:
> > + minItems: 4
> > + maxItems: 5
> > +
> > + reg-names:
> > + minItems: 4
> > + maxItems: 5
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + dma-coherent: true
> > +
> > + nvidia,bpmp:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + Must contain a pair of phandle (to the BPMP controller node) and
> > + controller ID. The following are the controller IDs for each controller:
> > +
> > + 0: C0
> > + 1: C1
> > + 2: C2
> > + 3: C3
> > + 4: C4
> > + 5: C5
> > + items:
> > + - items:
> > + - description: phandle to the BPMP controller node
> > + - description: PCIe controller ID
> > + maximum: 5
> > +
> > +unevaluatedProperties: false
> > +
> > +required:
> > + - interrupt-map
> > + - interrupt-map-mask
> > + - iommu-map
> > + - msi-map
> > + - nvidia,bpmp
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > + - oneOf:
> > + - description: C0 controller (no UPHY)
> > + properties:
> > + reg:
> > + items:
> > + - description: application layer registers
> > + - description: transaction layer registers
> > + - description: privileged transaction layer registers
> > + - description: ECAM-compatible configuration space
> > +
> > + reg-names:
> > + items:
> > + - const: xal
> > + - const: xtl
> > + - const: xtl-pri
> > + - const: ecam
> > +
> > + - description: C1-C5 controllers (with UPHY)
> > + properties:
> > + reg:
> > + items:
> > + - description: application layer registers
> > + - description: transaction layer registers
> > + - description: privileged transaction layer registers
> > + - description: data link/physical layer registers
> > + - description: ECAM-compatible configuration space
> > +
> > + items:
> > + - const: xal
> > + - const: xtl
> > + - const: xtl-pri
> > + - const: xpl
>
> Put this entry last since it is the optional one. Then you can move
> all of this to the top-level and get rid of the duplication.
I understand this concern and was actually on the fence about this
myself. The reason why I ultimately went with this variant is for two
reasons:
1. XPL does not exist for controller 0, the variant above makes that
very explicit. It explicitly documents that controller 0 is used
for internal purposes and cannot be connected to an external port
like the other five controllers.
2. The ECAM region is part of a memory region specifically reserved
for configuration space, whereas all of the other regions are
from the controller's MMIO region. I find the DT hard to read if
the two are interleaved.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] soc/tegra: Update BPMP ABI header
2026-03-20 9:34 ` Thierry Reding
@ 2026-03-20 9:44 ` Krzysztof Kozlowski
2026-03-20 9:49 ` Krzysztof Kozlowski
2026-03-20 12:46 ` Krzysztof Kozlowski
1 sibling, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-20 9:44 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
On 20/03/2026 10:34, Thierry Reding wrote:
> On Thu, Mar 19, 2026 at 05:15:56PM +0100, Krzysztof Kozlowski wrote:
>> On 19/03/2026 17:01, Thierry Reding wrote:
>>> From: Thierry Reding <treding@nvidia.com>
>>>
>>> This update primarily adds various new commands and MRQs for Tegra264,
>>> but also contains a few new annotations and fixes.
>>>
>>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>>> ---
>>> include/soc/tegra/bpmp-abi.h | 4565 +++++++++++++++++++++++++++-------
>>> 1 file changed, 3671 insertions(+), 894 deletions(-)
>>>
>>> diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
>>> index 39bb3f87e28d..6cf6442395f1 100644
>>> --- a/include/soc/tegra/bpmp-abi.h
>>> +++ b/include/soc/tegra/bpmp-abi.h
>>> @@ -1,6 +1,6 @@
>>> -/* SPDX-License-Identifier: GPL-2.0-only */
>>> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
>>> /*
>>> - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
>>> + * SPDX-FileCopyrightText: Copyright (c) 2014-2025, NVIDIA CORPORATION. All rights reserved.
>>
>> You just replaced correct syntax with discouraged (as in not welcomed
>> upstream) SPDX tag.
>
> Fair enough, I'm dropping the tag. I didn't know it was actively
> discouraged and I don't see this documented anywhere. I suppose I should
I am trying to get it somehow documented as permissive, v4 is waiting
for some time.
> go and drop similar tags from various other sources. Looks like we've
> been introducing this recently for Tegra.
I do not have opinion whether we should replace the tags, it does not
matter for me, but I would simply not use it in new code.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] soc/tegra: Update BPMP ABI header
2026-03-20 9:44 ` Krzysztof Kozlowski
@ 2026-03-20 9:49 ` Krzysztof Kozlowski
2026-03-20 10:52 ` Thierry Reding
0 siblings, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-20 9:49 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
On 20/03/2026 10:44, Krzysztof Kozlowski wrote:
> On 20/03/2026 10:34, Thierry Reding wrote:
>> On Thu, Mar 19, 2026 at 05:15:56PM +0100, Krzysztof Kozlowski wrote:
>>> On 19/03/2026 17:01, Thierry Reding wrote:
>>>> From: Thierry Reding <treding@nvidia.com>
>>>>
>>>> This update primarily adds various new commands and MRQs for Tegra264,
>>>> but also contains a few new annotations and fixes.
>>>>
>>>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>>>> ---
>>>> include/soc/tegra/bpmp-abi.h | 4565 +++++++++++++++++++++++++++-------
>>>> 1 file changed, 3671 insertions(+), 894 deletions(-)
>>>>
>>>> diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
>>>> index 39bb3f87e28d..6cf6442395f1 100644
>>>> --- a/include/soc/tegra/bpmp-abi.h
>>>> +++ b/include/soc/tegra/bpmp-abi.h
>>>> @@ -1,6 +1,6 @@
>>>> -/* SPDX-License-Identifier: GPL-2.0-only */
>>>> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
I missed this part here - that's license change. This has like 10
different authors, so you must be explicit about it in commit msg and
you must get their acks.
>>>> /*
>>>> - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
>>>> + * SPDX-FileCopyrightText: Copyright (c) 2014-2025, NVIDIA CORPORATION. All rights reserved.
>>>
>>> You just replaced correct syntax with discouraged (as in not welcomed
>>> upstream) SPDX tag.
>>
>> Fair enough, I'm dropping the tag. I didn't know it was actively
>> discouraged and I don't see this documented anywhere. I suppose I should
>
> I am trying to get it somehow documented as permissive, v4 is waiting
> for some time.
>
... feel free to encourage/review my change to get the tag officially
supported.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/5] PCI: tegra: Add Tegra264 support
2026-03-19 17:46 ` Bjorn Helgaas
@ 2026-03-20 10:34 ` Thierry Reding
2026-03-20 14:27 ` Bjorn Helgaas
0 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2026-03-20 10:34 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 7720 bytes --]
On Thu, Mar 19, 2026 at 12:46:39PM -0500, Bjorn Helgaas wrote:
> On Thu, Mar 19, 2026 at 05:01:08PM +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The
> > driver is very small, with its main purpose being to set up the address
> > translation registers and then creating a standard PCI host using ECAM.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > drivers/pci/controller/Kconfig | 8 +
> > drivers/pci/controller/Makefile | 1 +
> > drivers/pci/controller/pcie-tegra264.c | 506 +++++++++++++++++++++++++
> > 3 files changed, 515 insertions(+)
> > create mode 100644 drivers/pci/controller/pcie-tegra264.c
> >
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index e72ac6934379..36abee65eca1 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -257,6 +257,14 @@ config PCI_TEGRA
> > Say Y here if you want support for the PCIe host controller found
> > on NVIDIA Tegra SoCs.
>
> Should the PCI_TEGRA menu item ("NVIDIA Tegra PCIe controller") and
> this text be clarified somehow to make them clearly separate?
Good point. I'm adding "(Tegra20 through Tegra186)" to the PCI_TEGRA
option description.
> > +config PCIE_TEGRA264
> > + bool "NVIDIA Tegra264 PCIe controller"
> > + depends on ARCH_TEGRA || COMPILE_TEST
> > + depends on PCI_MSI
> > + help
> > + Say Y here if you want support for the PCIe host controller found
> > + on NVIDIA Tegra264 SoCs.
>
> > + * PCIe host controller driver for Tegra264 SoC
> > + *
> > + * Author: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>
> Manikanta doesn't appear in the signed-off-by or other tags above.
> Not really an issue for me; just a question of whether this is
> accurate.
You're right. I should've added a Signed-off-by for Manikanta. I'm
dropping this line here, though, because there's already a MODULE_AUTHOR
line at the end of the file.
>
> > +#define PCIE_LINK_UP_DELAY 10000 /* 10 msec */
> > +#define PCIE_LINK_UP_TIMEOUT 1000000 /* 1 s */
>
> Use something from drivers/pci/pci.h if possible. If not, please add
> units suffixes to the name, e.g., it looks like these are in "_US".
>
> PCIE_LINK_WAIT_MAX_RETRIES and PCIE_LINK_WAIT_SLEEP_MS look like
> they're used in similar ways in other drivers.
I see a bunch of implementations that use custom defines, if you don't
mind I'll have a go and unifying this a little. Most implementations
seem to use usleep_range(90000, 100000) with 10 retries.
>
> > +/* XAL registers */
> > +#define XAL_RC_ECAM_BASE_HI 0x00
> > +#define XAL_RC_ECAM_BASE_LO 0x04
> > +#define XAL_RC_ECAM_BUSMASK 0x08
> > +#define XAL_RC_IO_BASE_HI 0x0c
> > ...
> > +#define XTL_RC_MGMT_CLOCK_CONTROL 0x47C
>
> Inconsistent use of upper/lower-case hex with above.
Fixed.
> > +struct tegra264_pcie {
> > + struct device *dev;
> > + bool link_state;
>
> "link_state" being true/false doesn't read quite right because
> true/false isn't a "state". I guess true means "link is up"?
I've renamed this field to "link_up" so it's less ambiguous.
> > +static int tegra264_pcie_parse_dt(struct tegra264_pcie *pcie)
> > +{
> > + int err;
> > +
> > + pcie->wake_gpio = devm_gpiod_get_optional(pcie->dev, "nvidia,pex-wake",
> > + GPIOD_IN);
> > + if (IS_ERR(pcie->wake_gpio))
> > + return PTR_ERR(pcie->wake_gpio);
> > +
> > + if (pcie->wake_gpio) {
> > + device_init_wakeup(pcie->dev, true);
> > +
> > + err = gpiod_to_irq(pcie->wake_gpio);
> > + if (err < 0) {
> > + dev_err(pcie->dev, "failed to get wake IRQ: %d\n", err);
>
> Does %pe work here (and below)?
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/core-api/printk-formats.rst?id=v6.19#n96
It won't work in this particular case because %pe needs an ERR_PTR-
encoded error code. For the other messages it's probably better to move
to dev_err_probe() as Krzysztof suggested.
>
> > +static void tegra264_pcie_bpmp_set_rp_state(struct tegra264_pcie *pcie)
> > +{
> > + struct tegra_bpmp_message msg;
> > + struct mrq_pcie_request req;
> > + int err;
> > +
> > + memset(&req, 0, sizeof(req));
>
> I think "struct mrq_pcie_request req = {}" is equivalent, also for
> msg. No real preference from me.
Me neither. "= {}" saves two extra lines, so I guess it wins.
>
> > +static void tegra264_pcie_init(struct tegra264_pcie *pcie)
> > +{
> > + u32 value;
> > +
> > + if (!tegra_is_silicon()) {
> > + dev_info(pcie->dev,
> > + "skipping link state for PCIe #%u in simulation\n",
> > + pcie->ctl_id);
> > + pcie->link_state = true;
> > + return;
> > + }
> > +
> > + /* Poll every 10 msec for 1 sec to link up */
> > + readl_poll_timeout(pcie->ecam + XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS,
> > + value, value & XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS_DLL_ACTIVE,
> > + PCIE_LINK_UP_DELAY, PCIE_LINK_UP_TIMEOUT);
> > +
> > + if (value & XTL_RC_PCIE_CFG_LINK_CONTROL_STATUS_DLL_ACTIVE) {
> > + /* Per PCIe r5.0, 6.6.1 wait for 100ms after DLL up */
> > + msleep(100);
>
> Looks like possibly PCIE_RESET_CONFIG_WAIT_MS?
Yeah, looks about right. I'm not sure if we really need it in addition
to the polling above, but probably okay for an extra safe margin.
> > + dev_info(pcie->dev, "PCIe #%u link is up (speed: %d)\n",
> > + pcie->ctl_id, (value & 0xf0000) >> 16);
> > + pcie->link_state = true;
> > + tegra264_pcie_icc_set(pcie);
> > + } else {
> > + dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id);
> > +
> > + value = readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL);
> > +
> > + /** Set link state only when link fails and no hot-plug feature is present */
>
> /* (not /**), and wrap to fit in 78 columns.
>
> > + if ((value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT) == 0) {
> > + dev_info(pcie->dev,
> > + "PCIe #%u link is down and not hotplug-capable, turning off\n",
> > + pcie->ctl_id);
> > + tegra264_pcie_bpmp_set_rp_state(pcie);
> > + pcie->link_state = false;
> > + } else {
> > + pcie->link_state = true;
> > + }
> > + }
> > +}
> > +
> > +static int tegra264_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct pci_host_bridge *bridge;
> > + struct tegra264_pcie *pcie;
> > + struct resource_entry *bus;
> > + struct resource *res;
> > + int err;
> > +
> > + bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie));
> > + if (!bridge) {
> > + dev_err(dev, "failed to allocate host bridge\n");
> > + return -ENOMEM;
>
> Looks like this and others below could use:
>
> if (!bridge)
> return dev_err_probe(dev, -ENOMEM, "failed ...");
Guess everybody wants to use this now. I tend not to like it because it
has some issues with wrapping (because of the return, the _probe suffix
and the error code, it tends to go beyond 80 characters, cancelling out
many of the benefits). I see the extra benefit for cases where probe
deferral is a possibility, so that's where I usually do use it.
Anyway, I'll convert these since both you and Krzysztof requested it.
> > +static const struct dev_pm_ops tegra264_pcie_pm_ops = {
> > + .resume_noirq = tegra264_pcie_resume_noirq,
> > + .suspend_noirq = tegra264_pcie_suspend_noirq,
> > +};
>
> Should this use DEFINE_NOIRQ_DEV_PM_OPS() or similar to avoid warnings
> when CONFIG_PM_SLEEP, etc are not enabled?
Yes, that's a good point.
Thanks,
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/5] PCI: tegra: Add Tegra264 support
2026-03-19 16:14 ` Krzysztof Kozlowski
@ 2026-03-20 10:39 ` Thierry Reding
0 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-20 10:39 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 2617 bytes --]
On Thu, Mar 19, 2026 at 05:14:03PM +0100, Krzysztof Kozlowski wrote:
> On 19/03/2026 17:01, Thierry Reding wrote:
> > obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
> > obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
> > obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
> > diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controller/pcie-tegra264.c
> > new file mode 100644
> > index 000000000000..0c8351b88941
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-tegra264.c
> > @@ -0,0 +1,506 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +// SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
>
> Don't use that tag, please, but standard Copyright.
Done.
> > +static int tegra264_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct pci_host_bridge *bridge;
> > + struct tegra264_pcie *pcie;
> > + struct resource_entry *bus;
> > + struct resource *res;
> > + int err;
> > +
> > + bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie));
> > + if (!bridge) {
> > + dev_err(dev, "failed to allocate host bridge\n");
> > + return -ENOMEM;
> > + }
> > +
> > + pcie = pci_host_bridge_priv(bridge);
> > + platform_set_drvdata(pdev, pcie);
> > + pcie->bridge = bridge;
> > + pcie->dev = dev;
> > +
> > + err = pinctrl_pm_select_default_state(dev);
> > + if (err < 0) {
> > + dev_err(dev, "failed to configure sideband pins: %d\n", err);
> > + return err;
> > + }
> > +
> > + err = tegra264_pcie_parse_dt(pcie);
> > + if (err < 0)
> > + return dev_err_probe(dev, err, "failed to parse device tree");
> > +
> > + pcie->xal = devm_platform_ioremap_resource_byname(pdev, "xal");
> > + if (IS_ERR(pcie->xal)) {
> > + err = PTR_ERR(pcie->xal);
> > + dev_err(dev, "failed to map xal memory: %d\n", err);
> > + return err;
>
> What's with this syntax here? This is just one call return
> dev_err_probe. Looks like you are sending us some old code, instead of
> use recent drivers starting point.
It's not old code, just me being old and used to the old ways. I don't
see much point in dev_err_probe() for some of these cases because there
is no probe deferral and then dev_err_probe() is just extra overhead.
It's also much clunkier to use because it almost always requires
wrapping lines and then what's left of any benefits is pretty much
dissipated.
I get that it's the shiny new thing, but honestly, I don't think we're
doing ourselves any favours by blindly using it everywhere.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] soc/tegra: Update BPMP ABI header
2026-03-20 9:49 ` Krzysztof Kozlowski
@ 2026-03-20 10:52 ` Thierry Reding
0 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-20 10:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
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On Fri, Mar 20, 2026 at 10:49:43AM +0100, Krzysztof Kozlowski wrote:
> On 20/03/2026 10:44, Krzysztof Kozlowski wrote:
> > On 20/03/2026 10:34, Thierry Reding wrote:
> >> On Thu, Mar 19, 2026 at 05:15:56PM +0100, Krzysztof Kozlowski wrote:
> >>> On 19/03/2026 17:01, Thierry Reding wrote:
> >>>> From: Thierry Reding <treding@nvidia.com>
> >>>>
> >>>> This update primarily adds various new commands and MRQs for Tegra264,
> >>>> but also contains a few new annotations and fixes.
> >>>>
> >>>> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >>>> ---
> >>>> include/soc/tegra/bpmp-abi.h | 4565 +++++++++++++++++++++++++++-------
> >>>> 1 file changed, 3671 insertions(+), 894 deletions(-)
> >>>>
> >>>> diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
> >>>> index 39bb3f87e28d..6cf6442395f1 100644
> >>>> --- a/include/soc/tegra/bpmp-abi.h
> >>>> +++ b/include/soc/tegra/bpmp-abi.h
> >>>> @@ -1,6 +1,6 @@
> >>>> -/* SPDX-License-Identifier: GPL-2.0-only */
> >>>> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
>
> I missed this part here - that's license change. This has like 10
> different authors, so you must be explicit about it in commit msg and
> you must get their acks.
I'm not a lawyer, but any non-NVIDIA contributions to this file were a
license header changes by Thomas and typofixes by a random assortment of
people. I don't think any of those changes qualify as copyrightable or
licensable.
> >>>> /*
> >>>> - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
> >>>> + * SPDX-FileCopyrightText: Copyright (c) 2014-2025, NVIDIA CORPORATION. All rights reserved.
> >>>
> >>> You just replaced correct syntax with discouraged (as in not welcomed
> >>> upstream) SPDX tag.
> >>
> >> Fair enough, I'm dropping the tag. I didn't know it was actively
> >> discouraged and I don't see this documented anywhere. I suppose I should
> >
> > I am trying to get it somehow documented as permissive, v4 is waiting
> > for some time.
> >
>
> ... feel free to encourage/review my change to get the tag officially
> supported.
I've never thought about it much, but now that I have I almost prefer
the variant without the tag. I guess if there were a usecase where
people wanted to extract the copyright from kernel sources for some
reason it might make some sense, though given the state of the kernel
that would require an awful lot of churn and it'd probably be easier
to just extract the data using regular expressions.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-19 16:11 ` Krzysztof Kozlowski
@ 2026-03-20 10:56 ` Thierry Reding
0 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2026-03-20 10:56 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 4969 bytes --]
On Thu, Mar 19, 2026 at 05:11:17PM +0100, Krzysztof Kozlowski wrote:
> On 19/03/2026 17:01, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > The six PCIe controllers found on Tegra264 are of two types: one is used
> > for the internal GPU and therefore is not connected to a UPHY and the
> > remaining five controllers are typically routed to a PCI slot and have
> > additional controls for the physical link.
> >
> > While these controllers can be switched into endpoint mode, this binding
> > describes the root complex mode only.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> > 1 file changed, 92 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > new file mode 100644
> > index 000000000000..56d69de2788b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > @@ -0,0 +1,92 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra264 PCIe controller
> > +
> > +maintainers:
> > + - Thierry Reding <thierry.reding@gmail.com>
> > + - Jon Hunter <jonathanh@nvidia.com>
> > +
> > +properties:
> > + compatible:
> > + const: nvidia,tegra264-pcie
> > +
> > + reg:
> > + minItems: 4
> > + maxItems: 5
> > +
> > + reg-names:
> > + minItems: 4
> > + maxItems: 5
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + dma-coherent: true
> > +
> > + nvidia,bpmp:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + Must contain a pair of phandle (to the BPMP controller node) and
> > + controller ID. The following are the controller IDs for each controller:
> > +
> > + 0: C0
> > + 1: C1
> > + 2: C2
> > + 3: C3
> > + 4: C4
> > + 5: C5
> > + items:
> > + - items:
> > + - description: phandle to the BPMP controller node
> > + - description: PCIe controller ID
> > + maximum: 5
> > +
> > +unevaluatedProperties: false
>
> This goes before example
>
> > +
> > +required:
> > + - interrupt-map
> > + - interrupt-map-mask
> > + - iommu-map
> > + - msi-map
> > + - nvidia,bpmp
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > + - oneOf:
> > + - description: C0 controller (no UPHY)
>
> It does not look like you tested the bindings, at least after quick
> look. Please run `make dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> Maybe you need to update your dtschema and yamllint. Don't rely on
> distro packages for dtschema and be sure you are using the latest
> released dtschema.
I certainly validated the DTBs resulting from this series and didn't see
any issues. I thought that previously also ran the linter and bindings
checks, but it looks like it doesn't, so I'll need to update my script
to do so explicitly.
dtschema should be up-to-date as well.
>
> > + properties:
> > + reg:
> > + items:
> > + - description: application layer registers
> > + - description: transaction layer registers
> > + - description: privileged transaction layer registers
> > + - description: ECAM-compatible configuration space
> > +
> > + reg-names:
> > + items:
> > + - const: xal
> > + - const: xtl
> > + - const: xtl-pri
> > + - const: ecam
> > +
> > + - description: C1-C5 controllers (with UPHY)
> > + properties:
> > + reg:
> > + items:
> > + - description: application layer registers
> > + - description: transaction layer registers
> > + - description: privileged transaction layer registers
> > + - description: data link/physical layer registers
> > + - description: ECAM-compatible configuration space
> > +
> > + items:
> > + - const: xal
> > + - const: xtl
> > + - const: xtl-pri
> > + - const: xpl
> > + - const: ecam
>
> All of above are part of top level.
>
> And speaking about example - where is it? How can you then test (verify)
> this?
I'm using the DTB resulting from the last patch in this series to
validate an actual example. I suppose I can extract an example into the
bindings, but I thought this was no longer a strict requirement.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/5] soc/tegra: Update BPMP ABI header
2026-03-20 9:34 ` Thierry Reding
2026-03-20 9:44 ` Krzysztof Kozlowski
@ 2026-03-20 12:46 ` Krzysztof Kozlowski
1 sibling, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-20 12:46 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
On 20/03/2026 10:34, Thierry Reding wrote:
>>> diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h
>>> index 39bb3f87e28d..6cf6442395f1 100644
>>> --- a/include/soc/tegra/bpmp-abi.h
>>> +++ b/include/soc/tegra/bpmp-abi.h
>>> @@ -1,6 +1,6 @@
>>> -/* SPDX-License-Identifier: GPL-2.0-only */
>>> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
>>> /*
>>> - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
>>> + * SPDX-FileCopyrightText: Copyright (c) 2014-2025, NVIDIA CORPORATION. All rights reserved.
>>
>> You just replaced correct syntax with discouraged (as in not welcomed
>> upstream) SPDX tag.
>
> Fair enough, I'm dropping the tag. I didn't know it was actively
> discouraged and I don't see this documented anywhere. I suppose I should
> go and drop similar tags from various other sources. Looks like we've
> been introducing this recently for Tegra.
Just now Greg took my patch, so the tag is officially allowed. :)
Whether is preferred, depends whom you ask, so feel free to ignore my
feedback to replace it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-20 9:39 ` Thierry Reding
@ 2026-03-20 13:06 ` Rob Herring
2026-03-20 13:48 ` Thierry Reding
0 siblings, 1 reply; 25+ messages in thread
From: Rob Herring @ 2026-03-20 13:06 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Jon Hunter, linux-pci, devicetree, linux-tegra
On Fri, Mar 20, 2026 at 4:39 AM Thierry Reding
<thierry.reding@kernel.org> wrote:
>
> On Thu, Mar 19, 2026 at 04:26:31PM -0500, Rob Herring wrote:
> > On Thu, Mar 19, 2026 at 11:01 AM Thierry Reding
> > <thierry.reding@kernel.org> wrote:
> > >
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > The six PCIe controllers found on Tegra264 are of two types: one is used
> > > for the internal GPU and therefore is not connected to a UPHY and the
> > > remaining five controllers are typically routed to a PCI slot and have
> > > additional controls for the physical link.
> > >
> > > While these controllers can be switched into endpoint mode, this binding
> > > describes the root complex mode only.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > > .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> > > 1 file changed, 92 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > new file mode 100644
> > > index 000000000000..56d69de2788b
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > @@ -0,0 +1,92 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: NVIDIA Tegra264 PCIe controller
> > > +
> > > +maintainers:
> > > + - Thierry Reding <thierry.reding@gmail.com>
> > > + - Jon Hunter <jonathanh@nvidia.com>
> > > +
> > > +properties:
> > > + compatible:
> > > + const: nvidia,tegra264-pcie
> > > +
> > > + reg:
> > > + minItems: 4
> > > + maxItems: 5
> > > +
> > > + reg-names:
> > > + minItems: 4
> > > + maxItems: 5
> > > +
> > > + interrupts:
> > > + minItems: 1
> > > + maxItems: 4
> > > +
> > > + dma-coherent: true
> > > +
> > > + nvidia,bpmp:
> > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > + description: |
> > > + Must contain a pair of phandle (to the BPMP controller node) and
> > > + controller ID. The following are the controller IDs for each controller:
> > > +
> > > + 0: C0
> > > + 1: C1
> > > + 2: C2
> > > + 3: C3
> > > + 4: C4
> > > + 5: C5
> > > + items:
> > > + - items:
> > > + - description: phandle to the BPMP controller node
> > > + - description: PCIe controller ID
> > > + maximum: 5
> > > +
> > > +unevaluatedProperties: false
> > > +
> > > +required:
> > > + - interrupt-map
> > > + - interrupt-map-mask
> > > + - iommu-map
> > > + - msi-map
> > > + - nvidia,bpmp
> > > +
> > > +allOf:
> > > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > > + - oneOf:
> > > + - description: C0 controller (no UPHY)
> > > + properties:
> > > + reg:
> > > + items:
> > > + - description: application layer registers
> > > + - description: transaction layer registers
> > > + - description: privileged transaction layer registers
> > > + - description: ECAM-compatible configuration space
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: xal
> > > + - const: xtl
> > > + - const: xtl-pri
> > > + - const: ecam
> > > +
> > > + - description: C1-C5 controllers (with UPHY)
> > > + properties:
> > > + reg:
> > > + items:
> > > + - description: application layer registers
> > > + - description: transaction layer registers
> > > + - description: privileged transaction layer registers
> > > + - description: data link/physical layer registers
> > > + - description: ECAM-compatible configuration space
> > > +
> > > + items:
> > > + - const: xal
> > > + - const: xtl
> > > + - const: xtl-pri
> > > + - const: xpl
> >
> > Put this entry last since it is the optional one. Then you can move
> > all of this to the top-level and get rid of the duplication.
>
> I understand this concern and was actually on the fence about this
> myself. The reason why I ultimately went with this variant is for two
> reasons:
>
> 1. XPL does not exist for controller 0, the variant above makes that
> very explicit. It explicitly documents that controller 0 is used
> for internal purposes and cannot be connected to an external port
> like the other five controllers.
That doesn't really matter to the schema because it can never check
that unless you have 2 different compatibles (and you shouldn't).
> 2. The ECAM region is part of a memory region specifically reserved
> for configuration space, whereas all of the other regions are
> from the controller's MMIO region. I find the DT hard to read if
> the two are interleaved.
I was also going to suggest putting ECAM first just to align with the
generic host binding. That would make it slightly easier to rewrite
the node if you decided to make it a firmware initialized controller.
But if you really want it all as-is, fine.
Rob
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-20 13:06 ` Rob Herring
@ 2026-03-20 13:48 ` Thierry Reding
2026-03-20 15:58 ` Rob Herring
0 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2026-03-20 13:48 UTC (permalink / raw)
To: Rob Herring
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Jon Hunter, linux-pci, devicetree, linux-tegra
[-- Attachment #1: Type: text/plain, Size: 6001 bytes --]
On Fri, Mar 20, 2026 at 08:06:26AM -0500, Rob Herring wrote:
> On Fri, Mar 20, 2026 at 4:39 AM Thierry Reding
> <thierry.reding@kernel.org> wrote:
> >
> > On Thu, Mar 19, 2026 at 04:26:31PM -0500, Rob Herring wrote:
> > > On Thu, Mar 19, 2026 at 11:01 AM Thierry Reding
> > > <thierry.reding@kernel.org> wrote:
> > > >
> > > > From: Thierry Reding <treding@nvidia.com>
> > > >
> > > > The six PCIe controllers found on Tegra264 are of two types: one is used
> > > > for the internal GPU and therefore is not connected to a UPHY and the
> > > > remaining five controllers are typically routed to a PCI slot and have
> > > > additional controls for the physical link.
> > > >
> > > > While these controllers can be switched into endpoint mode, this binding
> > > > describes the root complex mode only.
> > > >
> > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > ---
> > > > .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> > > > 1 file changed, 92 insertions(+)
> > > > create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > > new file mode 100644
> > > > index 000000000000..56d69de2788b
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > > @@ -0,0 +1,92 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: NVIDIA Tegra264 PCIe controller
> > > > +
> > > > +maintainers:
> > > > + - Thierry Reding <thierry.reding@gmail.com>
> > > > + - Jon Hunter <jonathanh@nvidia.com>
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + const: nvidia,tegra264-pcie
> > > > +
> > > > + reg:
> > > > + minItems: 4
> > > > + maxItems: 5
> > > > +
> > > > + reg-names:
> > > > + minItems: 4
> > > > + maxItems: 5
> > > > +
> > > > + interrupts:
> > > > + minItems: 1
> > > > + maxItems: 4
> > > > +
> > > > + dma-coherent: true
> > > > +
> > > > + nvidia,bpmp:
> > > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > > + description: |
> > > > + Must contain a pair of phandle (to the BPMP controller node) and
> > > > + controller ID. The following are the controller IDs for each controller:
> > > > +
> > > > + 0: C0
> > > > + 1: C1
> > > > + 2: C2
> > > > + 3: C3
> > > > + 4: C4
> > > > + 5: C5
> > > > + items:
> > > > + - items:
> > > > + - description: phandle to the BPMP controller node
> > > > + - description: PCIe controller ID
> > > > + maximum: 5
> > > > +
> > > > +unevaluatedProperties: false
> > > > +
> > > > +required:
> > > > + - interrupt-map
> > > > + - interrupt-map-mask
> > > > + - iommu-map
> > > > + - msi-map
> > > > + - nvidia,bpmp
> > > > +
> > > > +allOf:
> > > > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > > > + - oneOf:
> > > > + - description: C0 controller (no UPHY)
> > > > + properties:
> > > > + reg:
> > > > + items:
> > > > + - description: application layer registers
> > > > + - description: transaction layer registers
> > > > + - description: privileged transaction layer registers
> > > > + - description: ECAM-compatible configuration space
> > > > +
> > > > + reg-names:
> > > > + items:
> > > > + - const: xal
> > > > + - const: xtl
> > > > + - const: xtl-pri
> > > > + - const: ecam
> > > > +
> > > > + - description: C1-C5 controllers (with UPHY)
> > > > + properties:
> > > > + reg:
> > > > + items:
> > > > + - description: application layer registers
> > > > + - description: transaction layer registers
> > > > + - description: privileged transaction layer registers
> > > > + - description: data link/physical layer registers
> > > > + - description: ECAM-compatible configuration space
> > > > +
> > > > + items:
> > > > + - const: xal
> > > > + - const: xtl
> > > > + - const: xtl-pri
> > > > + - const: xpl
> > >
> > > Put this entry last since it is the optional one. Then you can move
> > > all of this to the top-level and get rid of the duplication.
> >
> > I understand this concern and was actually on the fence about this
> > myself. The reason why I ultimately went with this variant is for two
> > reasons:
> >
> > 1. XPL does not exist for controller 0, the variant above makes that
> > very explicit. It explicitly documents that controller 0 is used
> > for internal purposes and cannot be connected to an external port
> > like the other five controllers.
>
> That doesn't really matter to the schema because it can never check
> that unless you have 2 different compatibles (and you shouldn't).
I know that, the documentation would be more for developers/users rather
than the validation tools.
> > 2. The ECAM region is part of a memory region specifically reserved
> > for configuration space, whereas all of the other regions are
> > from the controller's MMIO region. I find the DT hard to read if
> > the two are interleaved.
>
> I was also going to suggest putting ECAM first just to align with the
> generic host binding. That would make it slightly easier to rewrite
> the node if you decided to make it a firmware initialized controller.
Huh... I hadn't considered that. I think that would be a compromise that
I can very well live with.
Thierry
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/5] PCI: tegra: Add Tegra264 support
2026-03-20 10:34 ` Thierry Reding
@ 2026-03-20 14:27 ` Bjorn Helgaas
0 siblings, 0 replies; 25+ messages in thread
From: Bjorn Helgaas @ 2026-03-20 14:27 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jon Hunter, linux-pci, devicetree, linux-tegra
On Fri, Mar 20, 2026 at 11:34:53AM +0100, Thierry Reding wrote:
> On Thu, Mar 19, 2026 at 12:46:39PM -0500, Bjorn Helgaas wrote:
> > On Thu, Mar 19, 2026 at 05:01:08PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The
> > > driver is very small, with its main purpose being to set up the address
> > > translation registers and then creating a standard PCI host using ECAM.
> > > +#define PCIE_LINK_UP_DELAY 10000 /* 10 msec */
> > > +#define PCIE_LINK_UP_TIMEOUT 1000000 /* 1 s */
> >
> > Use something from drivers/pci/pci.h if possible. If not, please add
> > units suffixes to the name, e.g., it looks like these are in "_US".
> >
> > PCIE_LINK_WAIT_MAX_RETRIES and PCIE_LINK_WAIT_SLEEP_MS look like
> > they're used in similar ways in other drivers.
>
> I see a bunch of implementations that use custom defines, if you don't
> mind I'll have a go and unifying this a little. Most implementations
> seem to use usleep_range(90000, 100000) with 10 retries.
That would be awesome!
> > > + err = gpiod_to_irq(pcie->wake_gpio);
> > > + if (err < 0) {
> > > + dev_err(pcie->dev, "failed to get wake IRQ: %d\n", err);
> >
> > Does %pe work here (and below)?
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/core-api/printk-formats.rst?id=v6.19#n96
>
> It won't work in this particular case because %pe needs an ERR_PTR-
> encoded error code. For the other messages it's probably better to move
> to dev_err_probe() as Krzysztof suggested.
We could use dev_err(dev, "..., %pe\n", ERR_PTR(err)). It's kind of ugly,
but seems like a fairly common style. I wish we had a simpler way to do
this; it seems like a shame to print a negative number when we have the
symbols available.
Bjorn
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
2026-03-20 13:48 ` Thierry Reding
@ 2026-03-20 15:58 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2026-03-20 15:58 UTC (permalink / raw)
To: Thierry Reding
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Krzysztof Kozlowski, Conor Dooley,
Jon Hunter, linux-pci, devicetree, linux-tegra
On Fri, Mar 20, 2026 at 8:48 AM Thierry Reding
<thierry.reding@kernel.org> wrote:
>
> On Fri, Mar 20, 2026 at 08:06:26AM -0500, Rob Herring wrote:
> > On Fri, Mar 20, 2026 at 4:39 AM Thierry Reding
> > <thierry.reding@kernel.org> wrote:
> > >
> > > On Thu, Mar 19, 2026 at 04:26:31PM -0500, Rob Herring wrote:
> > > > On Thu, Mar 19, 2026 at 11:01 AM Thierry Reding
> > > > <thierry.reding@kernel.org> wrote:
> > > > >
> > > > > From: Thierry Reding <treding@nvidia.com>
> > > > >
> > > > > The six PCIe controllers found on Tegra264 are of two types: one is used
> > > > > for the internal GPU and therefore is not connected to a UPHY and the
> > > > > remaining five controllers are typically routed to a PCI slot and have
> > > > > additional controls for the physical link.
> > > > >
> > > > > While these controllers can be switched into endpoint mode, this binding
> > > > > describes the root complex mode only.
> > > > >
> > > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > > ---
> > > > > .../bindings/pci/nvidia,tegra264-pcie.yaml | 92 +++++++++++++++++++
> > > > > 1 file changed, 92 insertions(+)
> > > > > create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..56d69de2788b
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > > > > @@ -0,0 +1,92 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > +%YAML 1.2
> > > > > +---
> > > > > +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > +
> > > > > +title: NVIDIA Tegra264 PCIe controller
> > > > > +
> > > > > +maintainers:
> > > > > + - Thierry Reding <thierry.reding@gmail.com>
> > > > > + - Jon Hunter <jonathanh@nvidia.com>
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + const: nvidia,tegra264-pcie
> > > > > +
> > > > > + reg:
> > > > > + minItems: 4
> > > > > + maxItems: 5
> > > > > +
> > > > > + reg-names:
> > > > > + minItems: 4
> > > > > + maxItems: 5
> > > > > +
> > > > > + interrupts:
> > > > > + minItems: 1
> > > > > + maxItems: 4
> > > > > +
> > > > > + dma-coherent: true
> > > > > +
> > > > > + nvidia,bpmp:
> > > > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > > > + description: |
> > > > > + Must contain a pair of phandle (to the BPMP controller node) and
> > > > > + controller ID. The following are the controller IDs for each controller:
> > > > > +
> > > > > + 0: C0
> > > > > + 1: C1
> > > > > + 2: C2
> > > > > + 3: C3
> > > > > + 4: C4
> > > > > + 5: C5
> > > > > + items:
> > > > > + - items:
> > > > > + - description: phandle to the BPMP controller node
> > > > > + - description: PCIe controller ID
> > > > > + maximum: 5
> > > > > +
> > > > > +unevaluatedProperties: false
> > > > > +
> > > > > +required:
> > > > > + - interrupt-map
> > > > > + - interrupt-map-mask
> > > > > + - iommu-map
> > > > > + - msi-map
> > > > > + - nvidia,bpmp
> > > > > +
> > > > > +allOf:
> > > > > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > > > > + - oneOf:
> > > > > + - description: C0 controller (no UPHY)
> > > > > + properties:
> > > > > + reg:
> > > > > + items:
> > > > > + - description: application layer registers
> > > > > + - description: transaction layer registers
> > > > > + - description: privileged transaction layer registers
> > > > > + - description: ECAM-compatible configuration space
> > > > > +
> > > > > + reg-names:
> > > > > + items:
> > > > > + - const: xal
> > > > > + - const: xtl
> > > > > + - const: xtl-pri
> > > > > + - const: ecam
> > > > > +
> > > > > + - description: C1-C5 controllers (with UPHY)
> > > > > + properties:
> > > > > + reg:
> > > > > + items:
> > > > > + - description: application layer registers
> > > > > + - description: transaction layer registers
> > > > > + - description: privileged transaction layer registers
> > > > > + - description: data link/physical layer registers
> > > > > + - description: ECAM-compatible configuration space
> > > > > +
> > > > > + items:
> > > > > + - const: xal
> > > > > + - const: xtl
> > > > > + - const: xtl-pri
> > > > > + - const: xpl
> > > >
> > > > Put this entry last since it is the optional one. Then you can move
> > > > all of this to the top-level and get rid of the duplication.
> > >
> > > I understand this concern and was actually on the fence about this
> > > myself. The reason why I ultimately went with this variant is for two
> > > reasons:
> > >
> > > 1. XPL does not exist for controller 0, the variant above makes that
> > > very explicit. It explicitly documents that controller 0 is used
> > > for internal purposes and cannot be connected to an external port
> > > like the other five controllers.
> >
> > That doesn't really matter to the schema because it can never check
> > that unless you have 2 different compatibles (and you shouldn't).
>
> I know that, the documentation would be more for developers/users rather
> than the validation tools.
You can add whatever documentation you want to express that without
needlessly complicating the schema for no validation purpose. Arguably
if the schema is shorter, that documentation will be easier to see.
Rob
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2026-03-20 15:58 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-03-19 16:01 [PATCH 0/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:01 ` [PATCH 1/5] soc/tegra: Update BPMP ABI header Thierry Reding
2026-03-19 16:15 ` Krzysztof Kozlowski
2026-03-20 9:34 ` Thierry Reding
2026-03-20 9:44 ` Krzysztof Kozlowski
2026-03-20 9:49 ` Krzysztof Kozlowski
2026-03-20 10:52 ` Thierry Reding
2026-03-20 12:46 ` Krzysztof Kozlowski
2026-03-19 16:01 ` [PATCH 2/5] firmware: tegra: bpmp: Add tegra_bpmp_get_with_id() function Thierry Reding
2026-03-19 16:01 ` [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Thierry Reding
2026-03-19 16:11 ` Krzysztof Kozlowski
2026-03-20 10:56 ` Thierry Reding
2026-03-19 17:53 ` Rob Herring (Arm)
2026-03-19 21:26 ` Rob Herring
2026-03-20 9:39 ` Thierry Reding
2026-03-20 13:06 ` Rob Herring
2026-03-20 13:48 ` Thierry Reding
2026-03-20 15:58 ` Rob Herring
2026-03-19 16:01 ` [PATCH 4/5] PCI: tegra: Add Tegra264 support Thierry Reding
2026-03-19 16:14 ` Krzysztof Kozlowski
2026-03-20 10:39 ` Thierry Reding
2026-03-19 17:46 ` Bjorn Helgaas
2026-03-20 10:34 ` Thierry Reding
2026-03-20 14:27 ` Bjorn Helgaas
2026-03-19 16:01 ` [PATCH 5/5] arm64: tegra: Add PCI controllers on Tegra264 Thierry Reding
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