Re: [PATCH 3/5] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller

[Thierry Reding <thierry.reding@kernel.org>]

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On Thu, Mar 19, 2026 at 05:11:17PM +0100, Krzysztof Kozlowski wrote:
> On 19/03/2026 17:01, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > The six PCIe controllers found on Tegra264 are of two types: one is used
> > for the internal GPU and therefore is not connected to a UPHY and the
> > remaining five controllers are typically routed to a PCI slot and have
> > additional controls for the physical link.
> > 
> > While these controllers can be switched into endpoint mode, this binding
> > describes the root complex mode only.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  .../bindings/pci/nvidia,tegra264-pcie.yaml    | 92 +++++++++++++++++++
> >  1 file changed, 92 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > new file mode 100644
> > index 000000000000..56d69de2788b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
> > @@ -0,0 +1,92 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra264 PCIe controller
> > +
> > +maintainers:
> > +  - Thierry Reding <thierry.reding@gmail.com>
> > +  - Jon Hunter <jonathanh@nvidia.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: nvidia,tegra264-pcie
> > +
> > +  reg:
> > +    minItems: 4
> > +    maxItems: 5
> > +
> > +  reg-names:
> > +    minItems: 4
> > +    maxItems: 5
> > +
> > +  interrupts:
> > +    minItems: 1
> > +    maxItems: 4
> > +
> > +  dma-coherent: true
> > +
> > +  nvidia,bpmp:
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    description: |
> > +      Must contain a pair of phandle (to the BPMP controller node) and
> > +      controller ID. The following are the controller IDs for each controller:
> > +
> > +      0: C0
> > +      1: C1
> > +      2: C2
> > +      3: C3
> > +      4: C4
> > +      5: C5
> > +    items:
> > +      - items:
> > +          - description: phandle to the BPMP controller node
> > +          - description: PCIe controller ID
> > +            maximum: 5
> > +
> > +unevaluatedProperties: false
> 
> This goes before example
> 
> > +
> > +required:
> > +  - interrupt-map
> > +  - interrupt-map-mask
> > +  - iommu-map
> > +  - msi-map
> > +  - nvidia,bpmp
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-host-bridge.yaml#
> > +  - oneOf:
> > +    - description: C0 controller (no UPHY)
> 
> It does not look like you tested the bindings, at least after quick
> look. Please run `make dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> Maybe you need to update your dtschema and yamllint. Don't rely on
> distro packages for dtschema and be sure you are using the latest
> released dtschema.

I certainly validated the DTBs resulting from this series and didn't see
any issues. I thought that previously also ran the linter and bindings
checks, but it looks like it doesn't, so I'll need to update my script
to do so explicitly.

dtschema should be up-to-date as well.

> 
> > +      properties:
> > +        reg:
> > +          items:
> > +            - description: application layer registers
> > +            - description: transaction layer registers
> > +            - description: privileged transaction layer registers
> > +            - description: ECAM-compatible configuration space
> > +
> > +        reg-names:
> > +          items:
> > +            - const: xal
> > +            - const: xtl
> > +            - const: xtl-pri
> > +            - const: ecam
> > +
> > +    - description: C1-C5 controllers (with UPHY)
> > +      properties:
> > +        reg:
> > +          items:
> > +            - description: application layer registers
> > +            - description: transaction layer registers
> > +            - description: privileged transaction layer registers
> > +            - description: data link/physical layer registers
> > +            - description: ECAM-compatible configuration space
> > +
> > +      items:
> > +        - const: xal
> > +        - const: xtl
> > +        - const: xtl-pri
> > +        - const: xpl
> > +        - const: ecam
> 
> All of above are part of top level.
> 
> And speaking about example - where is it? How can you then test (verify)
> this?

I'm using the DTB resulting from the last patch in this series to
validate an actual example. I suppose I can extract an example into the
bindings, but I thought this was no longer a strict requirement.

Thierry

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