From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D10C1C6FD1D for ; Fri, 17 Mar 2023 12:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229499AbjCQMKH (ORCPT ); Fri, 17 Mar 2023 08:10:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229639AbjCQMKG (ORCPT ); Fri, 17 Mar 2023 08:10:06 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE7174743D for ; Fri, 17 Mar 2023 05:09:58 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id bi9so6168029lfb.12 for ; Fri, 17 Mar 2023 05:09:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679054997; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=jNiR0NLTuJj+aWp4YB9vTYSgpZApuVfwOdJ5ZUsnGj0=; b=YcGwRdgSUFM5T1XagjtlvRNmVe4Jf7NuzX+OWI7+j3ovglq4UV/JKpah/ATZQasTG6 rwkRVwxVIeG5yVHBjuefiW9ETbkBVgDgpZfTRkQh0m5y+wJFjEitN4kLIEqI2CnC3kxz /iuweDgmIkQ7NOR+eVh180t3UrWe4FSPNjUqmafK8JZl6j0pius6GpDc4MS4Dple9BHx EdR1BWZYTdUUvJktXdxJoWYsH8HVEB5yL3J3Glp4NxV4eAvL0A8kjJ6sTAG55u108YPz XJT4J3p/EW3FWugSjA3LOwOlbLyroTbfHa3YGw5ZLCcFAq5THSe3TeKG5FPScqOw88zA 2paA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679054997; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jNiR0NLTuJj+aWp4YB9vTYSgpZApuVfwOdJ5ZUsnGj0=; b=cSY5S9SgyTeylX/z2nUDfSXW5IZUK3SgfR6PCGOKRjweH3pVWYbFdBVQOuKoZzNmbK e761aF9lvkIiCOy89TAW446ueVuqkcUepaS3BO/GKaZoPNq0CJD7gUiUVpOI4GgZCWaj wWnq1PHmQz45DxVg1ndnxsQscASxesxNe3DnmYJ9FijEmzR1SelSWpDu5O219lBcfgKX guTaL2T5dNBWk0aLW0DKb8F1rvPjBTeQCjICRJTDp5CuVMA5xVaLgLrXsC2ayIXSzb3m TxIP7guyros1iUJtXM5+t89sRK+1bsqUuMrifw1MBobzFzPvWexF5etB7EDygOGEXmAP 8q4Q== X-Gm-Message-State: AO0yUKVozotgCuUGCdhB3Scs1UhtLP7Uxzw++YVCbvv9k1iQ8PVshlQY wDloPauvFFUoR5OuIAR5fWU0jw== X-Google-Smtp-Source: AK7set/J4wuWg4OytN80EDGFmX2hbBh16ONc9kAfE7OVJZXwNRrc3IJx9b1HCdYwn/r8MRS+n9Q9cQ== X-Received: by 2002:a05:6512:406:b0:4e9:59cd:4171 with SMTP id u6-20020a056512040600b004e959cd4171mr1956040lfk.60.1679054996939; Fri, 17 Mar 2023 05:09:56 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id r10-20020a056512102a00b004e7b84c6419sm343432lfr.192.2023.03.17.05.09.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Mar 2023 05:09:56 -0700 (PDT) Message-ID: Date: Fri, 17 Mar 2023 14:09:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v5 4/5] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy Content-Language: en-GB To: Neil Armstrong , Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230206-topic-sm8450-upstream-dp-controller-v5-0-a27f1b26ebe8@linaro.org> <20230206-topic-sm8450-upstream-dp-controller-v5-4-a27f1b26ebe8@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v5-4-a27f1b26ebe8@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 17/03/2023 11:12, Neil Armstrong wrote: > The QMP PHY is a USB3/DP combo phy, switch to the newly > documented bindings and register the clocks to the GCC > and DISPCC controllers. > > Reviewed-by: Dmitry Baryshkov > Reviewed-by: Konrad Dybcio > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 +++++++++++++----------------------- > 1 file changed, 15 insertions(+), 27 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 69695eb83897..0b5a151ce138 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -748,7 +749,7 @@ gcc: clock-controller@100000 { > <&ufs_mem_phy_lanes 0>, > <&ufs_mem_phy_lanes 1>, > <&ufs_mem_phy_lanes 2>, > - <0>; > + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > clock-names = "bi_tcxo", > "sleep_clk", > "pcie_0_pipe_clk", > @@ -2034,37 +2035,24 @@ usb_1_hsphy: phy@88e3000 { > resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > }; > > - usb_1_qmpphy: phy-wrapper@88e9000 { > - compatible = "qcom,sm8450-qmp-usb3-phy"; > - reg = <0 0x088e9000 0 0x200>, > - <0 0x088e8000 0 0x20>; > - status = "disabled"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > + usb_1_qmpphy: phy@88e8000 { > + compatible = "qcom,sm8450-qmp-usb3-dp-phy"; > + reg = <0 0x088e8000 0 0x4000>; This should be 0x3000 too, like 8350 > > clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > <&rpmhcc RPMH_CXO_CLK>, > - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > - clock-names = "aux", "ref_clk_src", "com_aux"; > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; > > resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > <&gcc GCC_USB3_PHY_PRIM_BCR>; > reset-names = "phy", "common"; > > - usb_1_ssphy: phy@88e9200 { > - reg = <0 0x088e9200 0 0x200>, > - <0 0x088e9400 0 0x200>, > - <0 0x088e9c00 0 0x400>, > - <0 0x088e9600 0 0x200>, > - <0 0x088e9800 0 0x200>, > - <0 0x088e9a00 0 0x100>; > - #phy-cells = <0>; > - #clock-cells = <0>; > - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > - clock-names = "pipe0"; > - clock-output-names = "usb3_phy_pipe_clk_src"; > - }; > + #clock-cells = <1>; > + #phy-cells = <1>; > + > + status = "disabled"; > }; > > remoteproc_slpi: remoteproc@2400000 { > @@ -2972,8 +2960,8 @@ dispcc: clock-controller@af00000 { > <&mdss_dsi0_phy 1>, > <&mdss_dsi1_phy 0>, > <&mdss_dsi1_phy 1>, > - <0>, /* dp0 */ > - <0>, > + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, > <0>, /* dp1 */ > <0>, > <0>, /* dp2 */ > @@ -4168,7 +4156,7 @@ usb_1_dwc3: usb@a600000 { > iommus = <&apps_smmu 0x0 0x0>; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; > phy-names = "usb2-phy", "usb3-phy"; > }; > }; > -- With best wishes Dmitry