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Thu, 27 Mar 2025 12:03:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CD.mail.protection.outlook.com (10.167.240.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Thu, 27 Mar 2025 12:03:16 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id DF25B4160CA0; Thu, 27 Mar 2025 20:03:15 +0800 (CST) Message-ID: Date: Thu, 27 Mar 2025 20:03:15 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/7] Enhance the PCIe controller driver To: Manikandan Karunakaran Pillai , "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kw@linux.com" , "manivannan.sadhasivam@linaro.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , Milind Parab Cc: "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20250327105429.2947013-1-mpillai@cadence.com> Content-Language: en-US From: Hans Zhang In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2025 12:03:16.5092 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 985b5fc2-93bf-4fc6-0771-08dd6d275bbe X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CD.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR06MB7049 Hi Manikandan, You should update your patch to V2, not no version at all. Best regards, Hans On 2025/3/27 18:59, Manikandan Karunakaran Pillai wrote: > EXTERNAL EMAIL > > Enhances the exiting Cadence PCIe controller drivers to support second > generation PCIe controller also referred as HPA(High Performance > Architecture) controllers. > > The patch set enhances the Cadence PCIe driver for the new high > performance architecture changes. The "compatible" property in DTS > is added with more strings to support the new platform architecture > and the register maps that change with it. The driver read register > and write register functions take the updated offset stored from the > platform driver to access the registers. The driver now supports > the legacy and HPA architecture, with the legacy code being changed > minimal. The TI SoC continues to be supported with the changes > incorporated. The changes are also in tune with how multiple platforms > are supported in related drivers. > > Patch 1/7 - DTS related changes for property "compatible" > Patch 2/7 - Updates the header file with relevant register offsets and > bit definitions > Patch 3/7 - Platform related code changes > Patch 4/7 - PCIe EP related code changes > Patch 5/7 - Header file is updated with register offsets and updated > read and write register functions > Patch 6/7 - Support for multiple arch by using registered callbacks > Patch 7/7 - TIJ72X board is updated to use the new approach > > Comments from the earlier patch submission on the same enhancements are > taken into consideration. The previous submitted patch links is > https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com/ > > The scripts/checkpatch.pl has been run on the patches with and without > --strict. With the --strict option, 4 checks are generated on 1 patch > (patch 0002 of the series), which can be ignored. There are no code > fixes required for these checks. The rest of the 'scripts/checkpatch.pl' > is clean. > > The changes are tested on TI platforms. The legacy controller changes are > tested on an TI J7200 EVM and HPA changes are planned for on an FPGA > platform available within Cadence. > > Manikandan K Pillai (7): > dt-bindings: pci: cadence: Extend compatible for new platform > configurations > PCI: cadence: Add header support for PCIe next generation controllers > PCI: cadence: Add platform related architecture and register > information > PCI: cadence: Add support for PCIe Endpoint HPA controllers > PCI: cadence: Update the PCIe controller register address offsets > PCI: cadence: Add callback functions for Root Port and EP controller > PCI: cadence: Update support for TI J721e boards > > .../bindings/pci/cdns,cdns-pcie-ep.yaml | 12 +- > .../bindings/pci/cdns,cdns-pcie-host.yaml | 119 +++++- > drivers/pci/controller/cadence/pci-j721e.c | 8 + > .../pci/controller/cadence/pcie-cadence-ep.c | 184 +++++++-- > .../controller/cadence/pcie-cadence-host.c | 264 ++++++++++-- > .../controller/cadence/pcie-cadence-plat.c | 145 +++++++ > drivers/pci/controller/cadence/pcie-cadence.c | 217 +++++++++- > drivers/pci/controller/cadence/pcie-cadence.h | 380 +++++++++++++++++- > 8 files changed, 1259 insertions(+), 70 deletions(-) > > -- > 2.27.0 > >