From: Neil Armstrong <neil.armstrong@linaro.org>
To: Joe Sandom <jsandom@axon.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/5] arm64: dts: qcom: sm8550: add PCIe port labels
Date: Tue, 7 Apr 2026 19:32:29 +0200 [thread overview]
Message-ID: <ab8e8dfb-1b89-4533-9d00-b7b09de5dee8@linaro.org> (raw)
In-Reply-To: <20260407-rb5gen2-dts-v2-2-d0c7f447ee73@axon.com>
On 4/7/26 17:46, Joe Sandom wrote:
> Add labels to the root port nodes (pcie0_port0, pcie1_port0) to
> allow board DTS files to reference them for adding endpoint devices
> to each pcie root port.
>
> Update the pcieport0 reference to pcie0_port0 in sm8550-hdk.dts and
> sm8550-qrd.dts to match the label rename in sm8550.dtsi.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +-
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +-
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> index ee13e6136a8259d28540e718851e094f74ead278..e821b731bdc496c872703723df02ae9b9b0233b5 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> @@ -1012,7 +1012,7 @@ &pcie0 {
> status = "okay";
> };
>
> -&pcieport0 {
> +&pcie0_port0 {
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> index 2fb2e0be5e4c6b597f20f332cdf063daa2664205..cf63109ff7bf7b6fc827f108e22e82b8b04273c1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
> @@ -912,7 +912,7 @@ &pcie0 {
> status = "okay";
> };
>
> -&pcieport0 {
> +&pcie0_port0 {
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 055ca931c04859f3a312eb9921aeb7a8cc676822..54308cbde40732da072177eab533582c155df590 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2098,7 +2098,7 @@ opp-16000000-3 {
> };
> };
>
> - pcieport0: pcie@0 {
> + pcie0_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> @@ -2300,7 +2300,7 @@ opp-32000000-4 {
> };
> };
>
> - pcie@0 {
> + pcie1_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
next prev parent reply other threads:[~2026-04-07 17:32 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-07 15:46 [PATCH v2 0/5] arm64: dts: qcom: add QCS8550 RB5Gen2 support Joe Sandom via B4 Relay
2026-04-07 15:46 ` [PATCH v2 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions Joe Sandom via B4 Relay
2026-04-07 17:38 ` Neil Armstrong
2026-04-09 11:41 ` Joe Sandom
2026-04-07 15:46 ` [PATCH v2 2/5] arm64: dts: qcom: sm8550: add PCIe port labels Joe Sandom via B4 Relay
2026-04-07 17:32 ` Neil Armstrong [this message]
2026-04-09 1:45 ` Dmitry Baryshkov
2026-04-07 15:46 ` [PATCH v2 3/5] arm64: dts: qcom: sm8550: move IPA properties to SoC device tree Joe Sandom via B4 Relay
2026-04-09 1:45 ` Dmitry Baryshkov
2026-04-07 15:46 ` [PATCH v2 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board Joe Sandom via B4 Relay
2026-04-07 15:46 ` [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support Joe Sandom via B4 Relay
2026-04-08 9:57 ` Konrad Dybcio
2026-04-08 12:35 ` Neil Armstrong
2026-04-08 13:15 ` Konrad Dybcio
2026-04-09 11:23 ` Joe Sandom
2026-04-09 11:24 ` Konrad Dybcio
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