[PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[Zichar Zhang]

From: "Zichar.Zhang" <zichar.zhang@cixtech.com>

Add the optional 'clock-names' property to specify the name of the GPIO
controller's input clock, aligning with standard clock binding conventions.
This complements the existing 'clocks' property and ensures proper clock
handling in device tree descriptions.

Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com>
---
 Documentation/devicetree/bindings/gpio/cdns,gpio.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
index a84d60b39459..c242b31edcbf 100644
--- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
@@ -24,6 +24,12 @@ properties:
   clocks:
     maxItems: 1
 
+  clock-names:
+    description:
+      Optional name for the GPIO controller input clock.
+    minItems: 1
+    maxItems: 1
+
   ngpios:
     minimum: 1
     maximum: 32
-- 
2.34.1

[PATCH 2/2] arm64: dts: cix: add FCH(S0)/S5 GPIO controllers for sky1

[Zichar Zhang]

From: "Zichar.Zhang" <zichar.zhang@cixtech.com>

Add Cadence GPIO controller nodes for Sky1 FCH(S0) and S5 domains in
sky1.dtsi, and enable those controllers on sky1-orion-o6.

Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com>
---
 arch/arm64/boot/dts/cix/sky1-orion-o6.dts |  28 +++++
 arch/arm64/boot/dts/cix/sky1.dtsi         | 123 ++++++++++++++++++++++
 2 files changed, 151 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
index 4dee8cd0b86d..4dc76e0135ee 100644
--- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
@@ -89,3 +89,31 @@ &pcie_x1_1_rc {
 &uart2 {
 	status = "okay";
 };
+
+&s5_gpio0 {
+	status = "okay";
+};
+
+&s5_gpio1 {
+	status = "okay";
+};
+
+&s5_gpio2 {
+	status = "okay";
+};
+
+&fch_gpio0 {
+	status = "okay";
+};
+
+&fch_gpio1 {
+	status = "okay";
+};
+
+&fch_gpio2 {
+	status = "okay";
+};
+
+&fch_gpio3 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 72f3b195a927..9ceaf8f68e83 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -185,6 +185,13 @@ psci {
 		method = "smc";
 	};
 
+	s5_gpio_apb_clk: s5-gpio-apb-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "s5_gpio_apb_clk";
+	};
+
 	soc@0 {
 		compatible = "simple-bus";
 		ranges = <0 0 0 0 0x20 0>;
@@ -354,6 +361,74 @@ syscon: syscon@4160000 {
 			#reset-cells = <1>;
 		};
 
+		fch_gpio0: gpio-controller@4120000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x0 0x4120000 0x0 0x1000>;
+			clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
+			clock-names = "fch_gpio_apb_clk";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
+		fch_gpio1: gpio-controller@4130000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x0 0x4130000 0x0 0x1000>;
+			clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
+			clock-names = "fch_gpio_apb_clk";
+
+			interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
+		fch_gpio2: gpio-controller@4140000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x0 0x4140000 0x0 0x1000>;
+			clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
+			clock-names = "fch_gpio_apb_clk";
+
+			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
+		fch_gpio3: gpio-controller@4150000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x0 0x4150000 0x0 0x1000>;
+			clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
+			clock-names = "fch_gpio_apb_clk";
+
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <17>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
 		iomuxc: pinctrl@4170000 {
 			compatible = "cix,sky1-pinctrl";
 			reg = <0x0 0x04170000 0x0 0x1000>;
@@ -587,6 +662,54 @@ s5_syscon: syscon@16000000 {
 			#reset-cells = <1>;
 		};
 
+		s5_gpio0: gpio-controller@16004000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x0 0x16004000 0x0 0x1000>;
+			clocks = <&s5_gpio_apb_clk>;
+
+			interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
+		s5_gpio1: gpio-controller@16005000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x0 0x16005000 0x0 0x1000>;
+			clocks = <&s5_gpio_apb_clk>;
+
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <10>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
+		s5_gpio2: gpio-controller@16006000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x0 0x16006000 0x0 0x1000>;
+			clocks = <&s5_gpio_apb_clk>;
+
+			interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <10>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
 		iomuxc_s5: pinctrl@16007000 {
 			compatible = "cix,sky1-pinctrl-s5";
 			reg = <0x0 0x16007000 0x0 0x1000>;
-- 
2.34.1

Re: [PATCH 2/2] arm64: dts: cix: add FCH(S0)/S5 GPIO controllers for sky1

[Linus Walleij]

On Fri, Mar 6, 2026 at 10:32 AM Zichar Zhang <zichar.zhang@cixtech.com> wrote:

> From: "Zichar.Zhang" <zichar.zhang@cixtech.com>
>
> Add Cadence GPIO controller nodes for Sky1 FCH(S0) and S5 domains in
> sky1.dtsi, and enable those controllers on sky1-orion-o6.
>
> Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com>

Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

Re: [PATCH 2/2] arm64: dts: cix: add FCH(S0)/S5 GPIO controllers for sky1

[Krzysztof Kozlowski]

On Fri, Mar 06, 2026 at 05:32:38PM +0800, Zichar Zhang wrote:
> From: "Zichar.Zhang" <zichar.zhang@cixtech.com>
> 
> Add Cadence GPIO controller nodes for Sky1 FCH(S0) and S5 domains in
> sky1.dtsi, and enable those controllers on sky1-orion-o6.
> 
> Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com>
> ---
>  arch/arm64/boot/dts/cix/sky1-orion-o6.dts |  28 +++++
>  arch/arm64/boot/dts/cix/sky1.dtsi         | 123 ++++++++++++++++++++++
>  2 files changed, 151 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> index 4dee8cd0b86d..4dc76e0135ee 100644
> --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> @@ -89,3 +89,31 @@ &pcie_x1_1_rc {
>  &uart2 {
>  	status = "okay";
>  };
> +
> +&s5_gpio0 {

I already asked cixtech contributors to read DTS coding style. More than
once. Does it mean I need to ask EACH contributor that? Maybe create
internal guideline to avoid trivial mistakes?

> +	status = "okay";
> +};
> +
> +&s5_gpio1 {
> +	status = "okay";
> +};
> +
> +&s5_gpio2 {
> +	status = "okay";
> +};
> +
> +&fch_gpio0 {
> +	status = "okay";
> +};
> +
> +&fch_gpio1 {
> +	status = "okay";
> +};
> +
> +&fch_gpio2 {
> +	status = "okay";
> +};
> +
> +&fch_gpio3 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> index 72f3b195a927..9ceaf8f68e83 100644
> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> @@ -185,6 +185,13 @@ psci {
>  		method = "smc";
>  	};
>  
> +	s5_gpio_apb_clk: s5-gpio-apb-clk {

Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "s5_gpio_apb_clk";
> +	};
> +
>  	soc@0 {
>  		compatible = "simple-bus";
>  		ranges = <0 0 0 0 0x20 0>;
> @@ -354,6 +361,74 @@ syscon: syscon@4160000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		fch_gpio0: gpio-controller@4120000 {

Again, read DTS coding style.

> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x0 0x4120000 0x0 0x1000>;
> +			clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
> +			clock-names = "fch_gpio_apb_clk";

This is pointless name. GPIO block does not take some "fch" input. You
just called the input clock based on clock output which is completely
misunderstanding of the DTS.

Best regards,
Krzysztof

Re: [PATCH 2/2] arm64: dts: cix: add FCH(S0)/S5 GPIO controllers for sky1

[Zichar Zhang]

On Sat, Mar 07, 2026 at 04:22:39PM +0100, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On Fri, Mar 06, 2026 at 05:32:38PM +0800, Zichar Zhang wrote:
> > From: "Zichar.Zhang" <zichar.zhang@cixtech.com>
> >
> > Add Cadence GPIO controller nodes for Sky1 FCH(S0) and S5 domains in
> > sky1.dtsi, and enable those controllers on sky1-orion-o6.
> >
> > Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com>
> > ---
> >  arch/arm64/boot/dts/cix/sky1-orion-o6.dts |  28 +++++
> >  arch/arm64/boot/dts/cix/sky1.dtsi         | 123 ++++++++++++++++++++++
> >  2 files changed, 151 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> > index 4dee8cd0b86d..4dc76e0135ee 100644
> > --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> > +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> > @@ -89,3 +89,31 @@ &pcie_x1_1_rc {
> >  &uart2 {
> >       status = "okay";
> >  };
> > +
> > +&s5_gpio0 {
> 
> I already asked cixtech contributors to read DTS coding style. More than
> once. Does it mean I need to ask EACH contributor that? Maybe create
> internal guideline to avoid trivial mistakes?

Thanks, I’m working on the next revision of this patch.
I have reordered the s5_gpioX and fch_gpioX nodes alphabetically
in the next version of the patch.

> 
> > +     status = "okay";
> > +};
> > +
> > +&s5_gpio1 {
> > +     status = "okay";
> > +};
> > +
> > +&s5_gpio2 {
> > +     status = "okay";
> > +};
> > +
> > +&fch_gpio0 {
> > +     status = "okay";
> > +};
> > +
> > +&fch_gpio1 {
> > +     status = "okay";
> > +};
> > +
> > +&fch_gpio2 {
> > +     status = "okay";
> > +};
> > +
> > +&fch_gpio3 {
> > +     status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> > index 72f3b195a927..9ceaf8f68e83 100644
> > --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> > +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> > @@ -185,6 +185,13 @@ psci {
> >               method = "smc";
> >       };
> >
> > +     s5_gpio_apb_clk: s5-gpio-apb-clk {
> 
> Please use name for all fixed clocks which matches current format
> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> any other options).
> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml

I have changed node name as "clock-100000000":
s5_gpio_apb_clk: clock-100000000 {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <100000000>;
                clock-output-names = "s5_gpio_apb_clk";
}

> 
> > +             compatible = "fixed-clock";
> > +             #clock-cells = <0>;
> > +             clock-frequency = <100000000>;
> > +             clock-output-names = "s5_gpio_apb_clk";
> > +     };
> > +
> >       soc@0 {
> >               compatible = "simple-bus";
> >               ranges = <0 0 0 0 0x20 0>;
> > @@ -354,6 +361,74 @@ syscon: syscon@4160000 {
> >                       #reset-cells = <1>;
> >               };
> >
> > +             fch_gpio0: gpio-controller@4120000 {
> 
> Again, read DTS coding style.
> 
> > +                     compatible = "cdns,gpio-r1p02";
> > +                     reg = <0x0 0x4120000 0x0 0x1000>;
> > +                     clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>;
> > +                     clock-names = "fch_gpio_apb_clk";
> 
> This is pointless name. GPIO block does not take some "fch" input. You
> just called the input clock based on clock output which is completely
> misunderstanding of the DTS.

Thanks, I will remove the property "clock-names" as well as the changes
in yaml file.

fch is a hardware "module" in the Sky1 chip. This module is powered down
when the system enters the S3 and S5 states. It contains several GPIO
controllers, so we refer to them as "fch_gpio". In contrast, "s5_gpio"
remains powered in the S5 state.

Based on the hierarchy, the clock input for fch_gpio on the APB bus is
named fch_gpio_apb_clk. By the same logic, the clock ID macro is named
CLK_TREE_FCH_GPIO_APB.

Best regards,
Zichar Zhang

Re: [PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[Linus Walleij]

Hi Zichar,

On Fri, Mar 6, 2026 at 10:32 AM Zichar Zhang <zichar.zhang@cixtech.com> wrote:

> +  clock-names:
> +    description:
> +      Optional name for the GPIO controller input clock.
> +    minItems: 1
> +    maxItems: 1

I think clock-names: true should suffice, but the binding maintainers
can say how
they want it.

I would suggest to also add:

  gpio-ranges:
    minItems: 1
    maxItems: 32

At this point even if you're not using it FTM. This will make it
possible to later
map the GPIOs to the pin controller and control pin configuration from the
GPIO subsystem.

Yours,
Linus Walleij

Re: [PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[Krzysztof Kozlowski]

On Fri, Mar 06, 2026 at 11:10:35AM +0100, Linus Walleij wrote:
> Hi Zichar,
> 
> On Fri, Mar 6, 2026 at 10:32 AM Zichar Zhang <zichar.zhang@cixtech.com> wrote:
> 
> > +  clock-names:
> > +    description:
> > +      Optional name for the GPIO controller input clock.
> > +    minItems: 1
> > +    maxItems: 1
> 
> I think clock-names: true should suffice, but the binding maintainers

There is no need for clock names in the first place. It's pointless here.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[Zichar Zhang]

On Fri, Mar 06, 2026 at 11:10:35AM +0100, Linus Walleij wrote:
> [You don't often get email from linusw@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> EXTERNAL EMAIL
> 
> Hi Zichar,
> 
> On Fri, Mar 6, 2026 at 10:32 AM Zichar Zhang <zichar.zhang@cixtech.com> wrote:
> 
> > +  clock-names:
> > +    description:
> > +      Optional name for the GPIO controller input clock.
> > +    minItems: 1
> > +    maxItems: 1
> 
> I think clock-names: true should suffice, but the binding maintainers
> can say how
> they want it.
> 
> I would suggest to also add:
> 
>   gpio-ranges:
>     minItems: 1
>     maxItems: 32
> 
> At this point even if you're not using it FTM. This will make it
> possible to later
> map the GPIOs to the pin controller and control pin configuration from the
> GPIO subsystem.

Thanks. Given that cdns,gpio.yaml already defines "ngpios", would it make
sense to use it for the "gpio-ranges" definition?

Best regards,
Zichar Zhang

Re: [PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[Linus Walleij]

On Wed, Mar 11, 2026 at 1:08 PM Zichar Zhang <zichar.zhang@cixtech.com> wrote:
> On Fri, Mar 06, 2026 at 11:10:35AM +0100, Linus Walleij wrote:
> > [You don't often get email from linusw@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > EXTERNAL EMAIL
> >
> > Hi Zichar,
> >
> > On Fri, Mar 6, 2026 at 10:32 AM Zichar Zhang <zichar.zhang@cixtech.com> wrote:
> >
> > > +  clock-names:
> > > +    description:
> > > +      Optional name for the GPIO controller input clock.
> > > +    minItems: 1
> > > +    maxItems: 1
> >
> > I think clock-names: true should suffice, but the binding maintainers
> > can say how
> > they want it.
> >
> > I would suggest to also add:
> >
> >   gpio-ranges:
> >     minItems: 1
> >     maxItems: 32
> >
> > At this point even if you're not using it FTM. This will make it
> > possible to later
> > map the GPIOs to the pin controller and control pin configuration from the
> > GPIO subsystem.
>
> Thanks. Given that cdns,gpio.yaml already defines "ngpios", would it make
> sense to use it for the "gpio-ranges" definition?

You mean like

maxItems: (ngpios) ? ngpios : 32

or something like that?

I don't think YAML can do variables that way, but Rob might know better.

We sure know 32 is a cap.

Yours,
Linus Walleij

Re: [PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[Krzysztof Kozlowski]

On Fri, Mar 06, 2026 at 05:32:37PM +0800, Zichar Zhang wrote:
> From: "Zichar.Zhang" <zichar.zhang@cixtech.com>
> 
> Add the optional 'clock-names' property to specify the name of the GPIO
> controller's input clock, aligning with standard clock binding conventions.

No, there are no such standard clock binding conventions. DT maintainer
tells you that.

Otherwise explain me where did we document such convention?

> This complements the existing 'clocks' property and ensures proper clock
> handling in device tree descriptions.
> 
> Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com>

Messed From/DCO.

Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.

> ---
>  Documentation/devicetree/bindings/gpio/cdns,gpio.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> index a84d60b39459..c242b31edcbf 100644
> --- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> @@ -24,6 +24,12 @@ properties:
>    clocks:
>      maxItems: 1
>  
> +  clock-names:
> +    description:
> +      Optional name for the GPIO controller input clock.
> +    minItems: 1

Nope. From where did you take such syntax? Missing proper constraints
for names.

I don't see reason for this in the first place and your commit msg is
really poor in explaining WHY you are doing this.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: gpio: cdns: add clock-names property

[Zichar Zhang]

On Sat, Mar 07, 2026 at 04:19:50PM +0100, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On Fri, Mar 06, 2026 at 05:32:37PM +0800, Zichar Zhang wrote:
> > From: "Zichar.Zhang" <zichar.zhang@cixtech.com>
> >
> > Add the optional 'clock-names' property to specify the name of the GPIO
> > controller's input clock, aligning with standard clock binding conventions.
> 
> No, there are no such standard clock binding conventions. DT maintainer
> tells you that.
> 
> Otherwise explain me where did we document such convention?
> 
> > This complements the existing 'clocks' property and ensures proper clock
> > handling in device tree descriptions.
> >
> > Signed-off-by: Zichar Zhang <zichar.zhang@cixtech.com>
> 
> Messed From/DCO.
> 
> Please run scripts/checkpatch.pl on the patches and fix reported
> warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
> patches and (probably) fix more warnings. Some warnings can be ignored,
> especially from --strict run, but the code here looks like it needs a
> fix. Feel free to get in touch if the warning is not clear.

Thanks, Done

> 
> > ---
> >  Documentation/devicetree/bindings/gpio/cdns,gpio.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> > index a84d60b39459..c242b31edcbf 100644
> > --- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> > +++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> > @@ -24,6 +24,12 @@ properties:
> >    clocks:
> >      maxItems: 1
> >
> > +  clock-names:
> > +    description:
> > +      Optional name for the GPIO controller input clock.
> > +    minItems: 1
> 
> Nope. From where did you take such syntax? Missing proper constraints
> for names.
> 
> I don't see reason for this in the first place and your commit msg is
> really poor in explaining WHY you are doing this.

Thanks, I will remove this patch