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X-CSE-ConnectionGUID: pxVf3VwHQL+fYk7dz52gTw== X-CSE-MsgGUID: hDPJWpK0Q7uWf37ZlOAXUg== X-IronPort-AV: E=McAfee;i="6800,10657,11728"; a="74216812" X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="74216812" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 07:05:16 -0700 X-CSE-ConnectionGUID: k1XTfjBJQ4GgdXiZMj5bIg== X-CSE-MsgGUID: D4f9VV8MRY6XIc7GFwtSDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="225290890" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.245.246]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 07:05:11 -0700 Date: Fri, 13 Mar 2026 16:05:08 +0200 From: Andy Shevchenko To: Antoniu Miclaus Cc: Michael Hennerich , Lars-Peter Clausen , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Petre Rodan , Jorge Marques , Marcelo Schmitt , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 4/4] iio: accel: adxl372: add support for ADXL371 Message-ID: References: <20260313115525.85435-1-antoniu.miclaus@analog.com> <20260313115525.85435-5-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260313115525.85435-5-antoniu.miclaus@analog.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Fri, Mar 13, 2026 at 01:54:57PM +0200, Antoniu Miclaus wrote: > Add support for the Analog Devices ADXL371, a +-200g 3-axis MEMS > accelerometer sharing the same register map as the ADXL372 but with > different ODR values (320/640/1280/2560/5120 Hz vs 400/800/1600/3200/ > 6400 Hz), different bandwidth values, and different timer scale > factors for activity/inactivity detection. > > Due to a silicon anomaly (er001) causing FIFO data misalignment on > all current ADXL371 silicon, FIFO and triggered buffer support is > disabled for the ADXL371 - only direct mode reads are supported. ... > +enum adxl371_odr { > + ADXL371_ODR_320HZ, > + ADXL371_ODR_640HZ, > + ADXL371_ODR_1280HZ, > + ADXL371_ODR_2560HZ, > + ADXL371_ODR_5120HZ, > + ADXL371_ODR_NUM, No comma for the terminator entry. > +}; ... > @@ -1217,8 +1258,8 @@ static int adxl372_buffer_setup(struct iio_dev *indio_dev) > return -ENOMEM; > > st->peak_datardy_trig = devm_iio_trigger_alloc(dev, "%s-dev%d-peak", > - indio_dev->name, > - iio_device_id(indio_dev)); > + indio_dev->name, > + iio_device_id(indio_dev)); > if (!st->peak_datardy_trig) > return -ENOMEM; Stray change. It doesn't belong to this patch. -- With Best Regards, Andy Shevchenko