From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: monaco: Add iface clock and power domain for ice sdhc
Date: Tue, 14 Apr 2026 12:30:23 +0200 [thread overview]
Message-ID: <aba25e15-176a-4df4-9d8f-e05d36d52c9e@oss.qualcomm.com> (raw)
In-Reply-To: <20260409-ice_emmc_clock_addition-v2-2-90bbcc057361@oss.qualcomm.com>
On 4/9/26 10:31 AM, Kuldeep Singh wrote:
> Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
> for its own resources. Before accessing ICE hardware during probe, to
> avoid potential unclocked register access issues (when clk_ignore_unused
> is not passed on the kernel command line), in addition to the 'core'
> clock the 'iface' clock should also be turned on by the driver. This can
> only be done if power domain is enabled.
>
> Specify both power domain and the iface clock.
>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
prev parent reply other threads:[~2026-04-14 10:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-09 8:31 [PATCH v2 0/2] Enable iface clock and power domain for kodiak and monaco ice sdhc Kuldeep Singh
2026-04-09 8:31 ` [PATCH v2 1/2] arm64: dts: qcom: kodiak: Add iface clock and power domain for " Kuldeep Singh
2026-04-14 10:30 ` Konrad Dybcio
2026-04-09 8:31 ` [PATCH v2 2/2] arm64: dts: qcom: monaco: " Kuldeep Singh
2026-04-14 10:30 ` Konrad Dybcio [this message]
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