From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>,
lee@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, afd@ti.com, srk@ti.com
Subject: Re: [PATCH v2] dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible
Date: Mon, 5 Feb 2024 09:54:47 +0100 [thread overview]
Message-ID: <abbd450d-8707-4daf-9a31-493c36dbc99c@linaro.org> (raw)
In-Reply-To: <20240204090336.3209063-1-s-vadapalli@ti.com>
On 04/02/2024 10:03, Siddharth Vadapalli wrote:
> The PCIE_CTRL registers within the CTRL_MMR space of TI's J784S4 SoC
> are used to configure the link speed, lane count and mode of operation
> of the respective PCIe instance. Add compatible for allowing the PCIe
> driver to obtain a regmap for the PCIE_CTRL register within the System
> Controller device-tree node in order to configure the PCIe instance
> accordingly.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-02-05 8:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-04 9:03 [PATCH v2] dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible Siddharth Vadapalli
2024-02-05 8:54 ` Krzysztof Kozlowski [this message]
2024-02-08 13:02 ` (subset) " Lee Jones
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