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Fri, 24 Jul 2026 04:00:20 -0700 (PDT) X-Received: by 2002:a17:90b:52cd:b0:387:e0cb:7ee with SMTP id 98e67ed59e1d1-38ec6661b73mr7464179a91.34.1784890820045; Fri, 24 Jul 2026 04:00:20 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38f03af892bsm1290553a91.9.2026.07.24.04.00.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 04:00:19 -0700 (PDT) Message-ID: Date: Fri, 24 Jul 2026 16:30:12 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] clk: qcom: common: Register reset controller only when resets are present To: Philipp Zabel , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov , Vladimir Zapolskiy References: <20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com> <20260723-shikra-audiocorecc-v3-1-90b878ae0d4e@oss.qualcomm.com> <1eca6815953b50fe3f276b64d74be2795b8382aa.camel@pengutronix.de> Content-Language: en-US From: Imran Shaik In-Reply-To: <1eca6815953b50fe3f276b64d74be2795b8382aa.camel@pengutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Pq6jqQM3 c=1 sm=1 tr=0 ts=6a6345c5 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=CcRILfWLW4tHOLBHFjEA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: EuWemhl4K6MoZADMpU3XPp76k9_pap5j X-Proofpoint-ORIG-GUID: EuWemhl4K6MoZADMpU3XPp76k9_pap5j X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA5OSBTYWx0ZWRfX5bgKe+V4FGiM bN3NOMBBBI3lSsM/xIoXo0X+7LJ/PAijcBefG9uaMNujyRb+H3KigWglbuETxOO+2dvT93NazmD qUIQ81a/CHJJYtXz2s+o81WKb2brRQg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA5OSBTYWx0ZWRfX9KkKkqsEay1i gRKVxPc9KTgMyk0aJNLebOnFd1OmtPdkRQA5pQ0l//N1+/8EmxTBmi6HcNU55NsJ3bys20G6cpj b6pfTQBuBsICUtVC3U1Om9hinlhMluFFoeQlXOp4WIYmEfMNlYkLMVtTWYLOX70MU+IX9LUx0gp qYJT/RrYG4cHehS4RMGnxKbga+DRhlqkygkHs08udsK4L3wCSevvfxXCZSCLmVN12p285C6AQIx iwa7CtmeK2ra/J96oAc2tWCEoUXrFadOCral7O2lWSsBySiSrIllQRsY7Sjbh/6VlRky4Onnna2 1GmKMDByF4Zp2LJOx16n4gZ9wRYhGqA0oP1yRLyvHcXZX5UfPKEc2JqWpRfOn0hCw/sDSdotkvr 8gqvAZdUBZWqocW0YdfPeL11kHPAemB6U3CdlTDpfJYVJoPdGY6Wfr0RwqtxiLnxwLiE0bH8d4R d5EX4OACKN+cKH2RWww== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_02,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240099 On 24-07-2026 04:19 pm, Philipp Zabel wrote: > On Do, 2026-07-23 at 21:15 +0530, Imran Shaik wrote: >> Some clock controller descriptors do not define resets. Avoid registering >> a reset controller in such cases by checking desc->num_resets. >> >> Reviewed-by: Konrad Dybcio >> Reviewed-by: Dmitry Baryshkov >> Reviewed-by: Vladimir Zapolskiy >> Signed-off-by: Imran Shaik >> --- >> drivers/clk/qcom/common.c | 24 +++++++++++++----------- >> 1 file changed, 13 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c >> index 2c09abaf1d2a15b7fbbbfeb67c03075381185a00..d6ff83045da8f308dcb9c5836af48090323248de 100644 >> --- a/drivers/clk/qcom/common.c >> +++ b/drivers/clk/qcom/common.c >> @@ -359,17 +359,19 @@ int qcom_cc_really_probe(struct device *dev, >> qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); >> } >> >> - reset = &cc->reset; >> - reset->rcdev.of_node = dev->of_node; >> - reset->rcdev.ops = &qcom_reset_ops; >> - reset->rcdev.owner = dev->driver->owner; >> - reset->rcdev.nr_resets = desc->num_resets; >> - reset->regmap = regmap; >> - reset->reset_map = desc->resets; >> - >> - ret = devm_reset_controller_register(dev, &reset->rcdev); >> - if (ret) >> - goto put_rpm; >> + if (desc->num_resets) { >> + reset = &cc->reset; >> + reset->rcdev.of_node = dev->of_node; >> + reset->rcdev.ops = &qcom_reset_ops; >> + reset->rcdev.owner = dev->driver->owner; >> + reset->rcdev.nr_resets = desc->num_resets; >> + reset->regmap = regmap; >> + reset->reset_map = desc->resets; >> + >> + ret = devm_reset_controller_register(dev, &reset->rcdev); >> + if (ret) >> + goto put_rpm; >> + } >> >> if (desc->gdscs && desc->num_gdscs) { >> scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); > > Is it possible to have num_resets == 0 but num_gdscs > 0? > If so, the now uninitialized reset variable will be dereferenced and > passed into gdsc_register() a few lines below: > > ret = gdsc_register(scd, &reset->rcdev, regmap); > > The whole gdsc reset handling looks very spooky, with > gdsc_(de)assert_reset() calling directly into the rcdev->ops with no > regard for reset control state. > Yes, sashiko also pointed [1] the same issue. I will check further on this and submit the updated change in a separate patch. For now, I'll drop this patch from this series, as it is no longer required after separating AudioCoreCC clocks and resets into different devices. [1] https://lore.kernel.org/all/20260723155515.68A0E1F00A3A@smtp.kernel.org/ Thanks, Imran