From: Brian Masney <bmasney@redhat.com>
To: Xuyang Dong <dongxuyang@eswincomputing.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, troy.mitchell@linux.dev,
ningyu@eswincomputing.com, linmin@eswincomputing.com,
huangyifeng@eswincomputing.com, pinkesh.vaghela@einfochips.com,
ganboing@gmail.com, marcel@ziswiler.com
Subject: Re: [PATCH v15 0/4] Add driver support for ESWIN eic700 SoC clock controller
Date: Mon, 16 Mar 2026 11:04:04 -0400 [thread overview]
Message-ID: <abgb5OcSFbt3FzjI@redhat.com> (raw)
In-Reply-To: <54e32101.4409.19cf56c4aae.Coremail.dongxuyang@eswincomputing.com>
Hi Xuyang (and Stephen),
On Mon, Mar 16, 2026 at 02:54:00PM +0800, Xuyang Dong wrote:
> >
> > The link [1] provides the official documentation for the EIC7700. Section 3.2
> > covers the clock subsystem.
> >
> > [1] https://www.sifive.com/document-file/eic7700x-datasheet
> >
> > Updates:
> > Change in v15:
> > - Updated driver file
> > - Add 'Reviewed-by: Brian Masney <bmasney@redhat.com>' for patch 2/4, 3/4 and 4/4.
> > - Add space between the name and < in MODULE_AUTHOR.
> > - Remove memset_p() and commit in eswin_clk_init().
> > The current implementation ensures that parent clocks are registered
> > before child clocks, thus preventing the creation of invalid clocks.
> >
>
> Hi Stephen,
>
> I received your review comments on v9. After addressing them and submitting
> v10 through v14, I received additional comments from Brian, Bo, Marcel,
> and the kernel test robot.
> v15 now has a Reviewed-by tag from Brian and a Tested-by tag from Marcel.
> Do you have any further comments on v15? I would like to send a GIT PULL
> request for 7.0-rc4 by the end of this week.
> Do you think this is okay?
It's been a month since Stephen posted on the list, so I'm not sure when
he'll be able to reply. I know he's been busy.
https://lore.kernel.org/linux-clk/?q=f%3Asboyd%40kernel.org
If you don't hear from him by rc7 (or even rc6), then I think that you
should send him a pull request. He'll either pull it, or tell you what
needs to change.
Once this driver is in tree, you'll still need to post patches to the
list, get them reviewed on list, and then send Stephen a pull for that
merge window. That's what the other SoC vendors do.
Stephen: I went through all of your v9 review comments for this driver,
and ensured that Xuyang addressed all of your concerns. The only thing
is that drivers/clk/eswin/clk-eic7700.c still includes linux/clk.h,
and you asked if it could be dropped. If we remove it, then it fails to
compile because of the clk notifier support:
drivers/clk/eswin/clk-eic7700.c: In function ‘eic7700_clk_pll_cpu_notifier_cb’:
drivers/clk/eswin/clk-eic7700.c:1270:23: error: ‘PRE_RATE_CHANGE’ undeclared (first use in this function)
1270 | if (action == PRE_RATE_CHANGE) {
| ^~~~~~~~~~~~~~~
drivers/clk/eswin/clk-eic7700.c:1270:23: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/eswin/clk-eic7700.c:1273:30: error: ‘POST_RATE_CHANGE’ undeclared (first use in this function)
1273 | } else if (action == POST_RATE_CHANGE) {
| ^~~~~~~~~~~~~~~~
drivers/clk/eswin/clk-eic7700.c: In function ‘eic7700_clk_probe’:
drivers/clk/eswin/clk-eic7700.c:1313:15: error: implicit declaration of function ‘devm_clk_notifier_register’; did you mean ‘mmu_notifier_register’? [-Wimplicit-function-declaration]
1313 | ret = devm_clk_notifier_register(dev, pll_clk, &clk_data->pll_nb);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
| mmu_notifier_register
These are currently defined in clk.h. This code was present in the v9.
Brian
prev parent reply other threads:[~2026-03-16 15:04 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-03 8:05 [PATCH v15 0/4] Add driver support for ESWIN eic700 SoC clock controller dongxuyang
2026-03-03 8:06 ` [PATCH v15 1/4] dt-bindings: clock: eswin: Documentation for eic7700 SoC dongxuyang
2026-03-25 2:13 ` Stephen Boyd
2026-03-03 8:06 ` [PATCH v15 2/4] clk: divider: Add devm_clk_hw_register_divider_parent_data dongxuyang
2026-03-25 2:12 ` Stephen Boyd
2026-03-03 8:07 ` [PATCH v15 3/4] clk: eswin: Add eic7700 clock driver dongxuyang
2026-03-17 8:05 ` Bo Gan
2026-03-25 2:12 ` Stephen Boyd
2026-03-03 8:07 ` [PATCH v15 4/4] MAINTAINERS: Add entry for ESWIN EIC7700 " dongxuyang
2026-03-25 2:12 ` Stephen Boyd
2026-03-16 6:54 ` [PATCH v15 0/4] Add driver support for ESWIN eic700 SoC clock controller Xuyang Dong
2026-03-16 15:04 ` Brian Masney [this message]
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