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bh=eyhiSFd7TnnR0Y4KPBjzhgYS3ePqfaic4BGkMyXWNsw=; b=mZP9Fh7ks1MBeclBECCuJouLSVmAo1S3kP+g3XJyaJo4EK9nSYO3mHOHz0ekBs8A0/dHe5Apu8wb1N227eM6sES3ZKWHV3Um+PPTp/Ovpy9qc5Gyj9mrDt3O3gOvj0izJOldmf0ZdA/xQs0knMttMDN2FjDp0WS+9dTUaIwb1oc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=ziyao.cc; spf=pass smtp.mailfrom=me@ziyao.cc; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1773725589; s=zmail; d=ziyao.cc; i=me@ziyao.cc; h=Date:Date:From:From:To:To:Cc:Cc:Subject:Subject:Message-ID:References:MIME-Version:Content-Type:In-Reply-To:Message-Id:Reply-To; bh=eyhiSFd7TnnR0Y4KPBjzhgYS3ePqfaic4BGkMyXWNsw=; b=ImJqzBhaykJ7b6/ZZttuDa2mVkhAhgDaSE6bshmKI944v399pbVfoE7pBrw+w0s7 3jyglFuOx3pr6RFQB9UJV8Nx9sIzKyQ0123yzbCRoTT6QXZhGKYysfsaK2IWwFHCq79 tuhORvK26dfLgOeQgY0foUHdkkgE5XaiFrZJ3J44= Received: by mx.zohomail.com with SMTPS id 1773725587000567.8249611127286; Mon, 16 Mar 2026 22:33:07 -0700 (PDT) Date: Tue, 17 Mar 2026 05:32:54 +0000 From: Yao Zi To: wangjia@ultrarisc.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han , Xincheng Zhang , Krzysztof Kozlowski , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver Message-ID: References: <20260316-ultrarisc-pcie-v1-0-ef2946ede698@ultrarisc.com> <20260316-ultrarisc-pcie-v1-4-ef2946ede698@ultrarisc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260316-ultrarisc-pcie-v1-4-ef2946ede698@ultrarisc.com> X-ZohoMailClient: External On Mon, Mar 16, 2026 at 03:07:00PM +0800, Jia Wang via B4 Relay wrote: > From: Xincheng Zhang > > Add DP1000 soc PCIe rc driver. > > Signed-off-by: Xincheng Zhang > Signed-off-by: Jia Wang > --- > drivers/pci/controller/dwc/Kconfig | 15 ++ > drivers/pci/controller/dwc/Makefile | 1 + > drivers/pci/controller/dwc/pcie-designware.h | 22 +++ > drivers/pci/controller/dwc/pcie-ultrarisc.c | 202 +++++++++++++++++++++++++++ > 4 files changed, 240 insertions(+) > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > index d0aa031397fa..0a33891bf7ef 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST > Say Y here if you want PCIe controller support on Toshiba Visconti SoC. > This driver supports TMPV7708 SoC. > > +config PCIE_ULTRARISC > + bool "UltraRISC PCIe host controller" Is there any reason preventing the driver being built as a module? If no, it would be better to change it to "tristate", to allow distribution to customize the configuration for image sizes, etc. > + depends on ARCH_ULTRARISC || COMPILE_TEST > + select PCIE_DW_HOST > + select PCI_MSI > + default y if ARCH_ULTRARISC > + help > + Enables support for the PCIe controller in the UltraRISC SoC. > + This driver supports UR-DP1000 SoC. When selected, it automatically > + enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support > + for MSI-based interrupt handling in the PCIe controller. > + By default, this symbol is enabled when `ARCH_ULTRARISC` is active, > + requiring no further configuration on that platform. > + > + > endmenu > #define PORT_LOGIC_LTSSM_STATE_L0 0x11 Best regards, Yao Zi