Re: [PATCH 4/4] soc: imx: imx8mp-blk-ctrl: expose high performance PLL clock

[Lucas Stach <l.stach@pengutronix.de>]

Am Dienstag, dem 13.12.2022 um 17:01 +0100 schrieb Lucas Stach:
> Expose the high performance PLL as a regular Linux clock, so the
> PCIe PHY can use it when there is no external refclock provided.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/soc/imx/imx8mp-blk-ctrl.c | 99 +++++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
> 
> diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
> index b3d9f6e083ba..ad5aebd640eb 100644
> --- a/drivers/soc/imx/imx8mp-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
> @@ -5,6 +5,7 @@
>   */
>  
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/device.h>
>  #include <linux/interconnect.h>
>  #include <linux/module.h>
> @@ -21,6 +22,15 @@
>  #define  USB_CLOCK_MODULE_EN	BIT(1)
>  #define  PCIE_PHY_APB_RST	BIT(4)
>  #define  PCIE_PHY_INIT_RST	BIT(5)
> +#define GPR_REG1		0x4
> +#define  PLL_LOCK		BIT(13)
> +#define GPR_REG2		0x8
> +#define  P_PLL_MASK		GENMASK(5, 0)
> +#define  M_PLL_MASK		GENMASK(15, 6)
> +#define  S_PLL_MASK		GENMASK(18, 16)
> +#define GPR_REG3		0xc
> +#define  PLL_CKE		BIT(17)
> +#define  PLL_RST		BIT(31)
>  
>  struct imx8mp_blk_ctrl_domain;
>  
> @@ -74,6 +84,94 @@ to_imx8mp_blk_ctrl_domain(struct generic_pm_domain *genpd)
>  	return container_of(genpd, struct imx8mp_blk_ctrl_domain, genpd);
>  }
>  
> +struct clk_hsio_pll {
> +	struct clk_hw	hw;
> +	struct regmap *regmap;
> +};
> +
> +static inline struct clk_hsio_pll *to_clk_hsio_pll(struct clk_hw *hw)
> +{
> +	return container_of(hw, struct clk_hsio_pll, hw);
> +}
> +
> +static int clk_hsio_pll_prepare(struct clk_hw *hw)
> +{
> +	struct clk_hsio_pll *clk = to_clk_hsio_pll(hw);
> +	u32 val;
> +
> +	/* set the PLL configuration */
> +	regmap_update_bits(clk->regmap, GPR_REG2,
> +			   P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
> +			   FIELD_PREP(P_PLL_MASK, 12) |
> +			   FIELD_PREP(M_PLL_MASK, 800) |
> +			   FIELD_PREP(S_PLL_MASK, 4));
> +
> +	/* de-assert PLL reset */
> +	regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST);
> +
> +	/* enable PLL */
> +	regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE);
> +
> +	return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val,
> +					val & PLL_LOCK, 10, 100);
> +}
> +
> +static void clk_hsio_pll_unprepare(struct clk_hw *hw)
> +{
> +	struct clk_hsio_pll *clk = to_clk_hsio_pll(hw);
> +
> +	regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0);
> +}
> +
> +static int clk_hsio_pll_is_prepared(struct clk_hw *hw)
> +{
> +	struct clk_hsio_pll *clk = to_clk_hsio_pll(hw);
> +
> +	return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK);
> +}
> +
> +static unsigned long clk_hsio_pll_recalc_rate(struct clk_hw *hw,
> +					      unsigned long parent_rate)
> +{
> +	return 100000000;
> +}
> +
> +static const struct clk_ops clk_hsio_pll_ops = {
> +	.prepare = clk_hsio_pll_prepare,
> +	.unprepare = clk_hsio_pll_unprepare,
> +	.is_prepared = clk_hsio_pll_is_prepared,
> +	.recalc_rate = clk_hsio_pll_recalc_rate,
> +};
> +
> +int imx8mp_hsio_blk_ctrl_probe(struct imx8mp_blk_ctrl *bc)
> +{
> +	struct clk_hsio_pll *clk_hsio_pll;
> +	struct clk_hw *hw;
> +	struct clk_init_data init = {};
> +	int ret;
> +
> +	printk("%s\n", __func__);

This printk should obviously not be here. Removed locally. I'll wait
for some feedback before sending v2.

Regards,
Lucas

> +
> +	clk_hsio_pll = devm_kzalloc(bc->dev, sizeof(*clk_hsio_pll), GFP_KERNEL);
> +	if (!clk_hsio_pll)
> +		return -ENOMEM;
> +
> +	init.name = "hsio_pll";
> +	init.ops = &clk_hsio_pll_ops;
> +	init.parent_names = (const char *[]){"osc_24m"};
> +	init.num_parents = 1;
> +
> +	clk_hsio_pll->regmap = bc->regmap;
> +	clk_hsio_pll->hw.init = &init;
> +
> +	hw = &clk_hsio_pll->hw;
> +	ret = devm_clk_hw_register(bc->dev, hw);
> +	if (ret)
> +		return ret;
> +
> +	return devm_of_clk_add_hw_provider(bc->dev, of_clk_hw_simple_get, hw);
> +}
> +
>  static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
>  					  struct imx8mp_blk_ctrl_domain *domain)
>  {
> @@ -188,6 +286,7 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
>  
>  static const struct imx8mp_blk_ctrl_data imx8mp_hsio_blk_ctl_dev_data = {
>  	.max_reg = 0x24,
> +	.probe = imx8mp_hsio_blk_ctrl_probe,
>  	.power_on = imx8mp_hsio_blk_ctrl_power_on,
>  	.power_off = imx8mp_hsio_blk_ctrl_power_off,
>  	.power_notifier_fn = imx8mp_hsio_power_notifier,