From: <Claudiu.Beznea@microchip.com>
To: <Conor.Dooley@microchip.com>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
<Daire.McNamara@microchip.com>
Cc: <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v4 10/13] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()
Date: Thu, 8 Sep 2022 06:47:04 +0000 [thread overview]
Message-ID: <ac348009-97bd-919c-3b1a-b12c4d7d5153@microchip.com> (raw)
In-Reply-To: <20220830125249.2373416-10-conor.dooley@microchip.com>
On 30.08.2022 15:52, Conor Dooley wrote:
> The register functions are now comprised of only a single operation
> each and no longer add anything to the driver. Delete them.
>
> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
> drivers/clk/microchip/clk-mpfs.c | 33 ++++++--------------------------
> 1 file changed, 6 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c
> index 60e1e82912fe..538cb589d232 100644
> --- a/drivers/clk/microchip/clk-mpfs.c
> +++ b/drivers/clk/microchip/clk-mpfs.c
> @@ -203,14 +203,6 @@ static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
> MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
> };
>
> -static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw,
> - void __iomem *base)
> -{
> - msspll_hw->base = base;
> -
> - return devm_clk_hw_register(dev, &msspll_hw->hw);
> -}
> -
> static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
> unsigned int num_clks, struct mpfs_clock_data *data)
> {
> @@ -220,7 +212,8 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c
> for (i = 0; i < num_clks; i++) {
> struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
>
> - ret = mpfs_clk_register_msspll(dev, msspll_hw, data->msspll_base);
> + msspll_hw->base = data->msspll_base;
> + ret = devm_clk_hw_register(dev, &msspll_hw->hw);
> if (ret)
> return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
> CLK_MSSPLL);
> @@ -314,14 +307,6 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
> }
> };
>
> -static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw,
> - void __iomem *base)
> -{
> - cfg_hw->cfg.reg = base + cfg_hw->reg_offset;
> -
> - return devm_clk_hw_register(dev, &cfg_hw->hw);
> -}
> -
> static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
> unsigned int num_clks, struct mpfs_clock_data *data)
> {
> @@ -331,7 +316,8 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *
> for (i = 0; i < num_clks; i++) {
> struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
>
> - ret = mpfs_clk_register_cfg(dev, cfg_hw, data->base);
> + cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
> + ret = devm_clk_hw_register(dev, &cfg_hw->hw);
> if (ret)
> return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
> cfg_hw->id);
> @@ -454,14 +440,6 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
> CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
> };
>
> -static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw,
> - void __iomem *base)
> -{
> - periph_hw->periph.reg = base + REG_SUBBLK_CLOCK_CR;
> -
> - return devm_clk_hw_register(dev, &periph_hw->hw);
> -}
> -
> static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
> int num_clks, struct mpfs_clock_data *data)
> {
> @@ -471,7 +449,8 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c
> for (i = 0; i < num_clks; i++) {
> struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
>
> - ret = mpfs_clk_register_periph(dev, periph_hw, data->base);
> + periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
> + ret = devm_clk_hw_register(dev, &periph_hw->hw);
> if (ret)
> return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
> periph_hw->id);
next prev parent reply other threads:[~2022-09-08 6:47 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-30 12:50 [PATCH v4 00/13] PolarFire SoC reset controller & clock cleanups Conor Dooley
2022-08-30 12:52 ` [PATCH v4 01/13] clk: microchip: mpfs: fix clk_cfg array bounds violation Conor Dooley
2022-08-31 17:03 ` Conor.Dooley
2022-09-08 6:44 ` Claudiu.Beznea
2022-09-08 6:48 ` Conor.Dooley
2022-09-09 11:01 ` Conor.Dooley
2022-08-30 12:52 ` [PATCH v4 02/13] dt-bindings: clk: microchip: mpfs: add reset controller support Conor Dooley
2022-08-30 12:52 ` [PATCH v4 03/13] clk: microchip: mpfs: add reset controller Conor Dooley
2022-09-08 6:45 ` Claudiu.Beznea
2022-08-30 12:52 ` [PATCH v4 04/13] reset: add polarfire soc reset support Conor Dooley
2022-09-08 6:44 ` Claudiu.Beznea
2022-08-30 12:52 ` [PATCH v4 05/13] MAINTAINERS: add polarfire soc reset controller Conor Dooley
2022-08-30 12:52 ` [PATCH v4 06/13] riscv: dts: microchip: add mpfs specific macb reset support Conor Dooley
2022-08-30 12:52 ` [PATCH v4 07/13] clk: microchip: mpfs: add MSS pll's set & round rate Conor Dooley
2022-09-08 6:46 ` Claudiu.Beznea
2022-08-30 12:52 ` [PATCH v4 08/13] clk: microchip: mpfs: move id & offset out of clock structs Conor Dooley
2022-09-08 6:46 ` Claudiu.Beznea
2022-08-30 12:52 ` [PATCH v4 09/13] clk: microchip: mpfs: simplify control reg access Conor Dooley
2022-09-08 6:46 ` Claudiu.Beznea
2022-08-30 12:52 ` [PATCH v4 10/13] clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() Conor Dooley
2022-09-08 6:47 ` Claudiu.Beznea [this message]
2022-08-30 12:52 ` [PATCH v4 11/13] clk: microchip: mpfs: convert cfg_clk to clk_divider Conor Dooley
2022-09-08 6:47 ` Claudiu.Beznea
2022-08-30 12:52 ` [PATCH v4 12/13] clk: microchip: mpfs: convert periph_clk to clk_gate Conor Dooley
2022-09-08 6:47 ` Claudiu.Beznea
2022-08-30 12:52 ` [PATCH v4 13/13] clk: microchip: mpfs: update module authorship & licencing Conor Dooley
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