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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2cafd073194sm283615eec.28.2026.04.01.20.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 20:10:33 -0700 (PDT) Date: Wed, 1 Apr 2026 20:10:31 -0700 From: Mike Tipton To: Luca Weiss Cc: Konrad Dybcio , Krzysztof Kozlowski , Taniya Das , Georgi Djakov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/5] dt-bindings: clock: qcom,milos-camcc: Document interconnect path Message-ID: References: <20260116-milos-camcc-icc-v1-0-400b7fcd156a@fairphone.com> <20260116-milos-camcc-icc-v1-2-400b7fcd156a@fairphone.com> <20260117-efficient-fractal-sloth-aaf7c2@quoll> <59d9f7ff-4111-4304-a76c-40f4000545f5@oss.qualcomm.com> <9f8619d4-43ac-4bc0-9598-c498d59a27b8@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Authority-Analysis: v=2.4 cv=WMlyn3sR c=1 sm=1 tr=0 ts=69cdde2a cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=W6naqKN7AAAA:8 a=hMnAP9elBZEPa_KQw-IA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 a=Xp8b5NkTPdl8jt_qJiRs:22 X-Proofpoint-GUID: YI2MMq9qC0v_q_OQORAEu9mQJAdk7uDy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAyMDAyNyBTYWx0ZWRfX49rW0l0eUrTI T5AVa+htJLmzczAgy/lTMK/tb1jijGA4Zm25FRvVktLEAqTrWs+km5hxXEmfBgvNdrN0NscHn8S J+cFXPBCgDWgfkgAris3/lRVrccBNc/NSqdi/gB+FPCRdSg5brf1q3g6S+GCrYOvM1hQazaC4zK SfqR7Vz1SpibZVJNBw5gukrRUNDdtN5LdCi8aLWgLv5A9m2oukebwTaaKNRkl+9cIA5v/oZvtq7 PfKdeXNhXBAZ2P6C9sYY9M1vFwkPkkJG6l99P098G/iGUgeUxanPq8EHUs89G6nHDf4OPob3HWq YeTkwRmFtDzEgeUFwA17w2qjJkgXk3djTkKNNsq0vGkKQlk7a3B7JkJAdJ5zC4DvlttxbiUgoUT Y+7Lw2lHN71VsFESUF0fPl5gdm7KtoawNKU2zRBmPQgeGwDhlEfvVVKHHSbLXIXGlQpWt1ZpzBW o7Az80Fae/iCqS1BeOg== X-Proofpoint-ORIG-GUID: YI2MMq9qC0v_q_OQORAEu9mQJAdk7uDy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-02_01,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 suspectscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604020027 Hi Luca, On Mon, Mar 30, 2026 at 04:55:40PM +0200, Luca Weiss wrote: > Hi Mike, > > On Tue Mar 24, 2026 at 3:48 AM CET, Mike Tipton wrote: > > On Mon, Jan 19, 2026 at 11:28:07AM +0100, Konrad Dybcio wrote: > >> > >> > >> On 1/19/26 11:20 AM, Konrad Dybcio wrote: > >> > On 1/17/26 12:46 PM, Krzysztof Kozlowski wrote: > >> >> On Fri, Jan 16, 2026 at 02:17:21PM +0100, Luca Weiss wrote: > >> >>> Document an interconnect path for camcc that's required to enable > >> >>> the CAMSS_TOP_GDSC power domain. > >> >> > >> >> I find it confusing. Enabling GDSC power domains is done via power > >> >> domains, not via interconnects. Do not represent power domains as > >> >> interconnects, it's something completely different. > >> > > >> > The name of the power domains is CAMSS_TOP_GDSC (seems you misread) > >> > > >> > For the power domain to successfully turn on, the MNoC needs to be > >> > turned on (empirical evidence). The way to do it is to request a > >> > nonzero vote on this interconnect path > >> > > >> > (presumably because the GDSC or its invisible providers require > >> > something connected over that bus to carry out their enable sequences). > > > > The GDSC itself shouldn't depend on MMNOC in order to turn on properly. > > It should turn on just fine without it. There *is* a dependency between > > CAM_TOP_GDSC and MMNOC, but it's in the opposite direction. > > I can personally just write from practical experience, as Qualcomm > doesn't share any relevant documentation with OEMs. > > Without this patch the GDSC refuses to turn on. > > [ 291.055839] ------------[ cut here ]------------ > [ 291.055860] cam_cc_camss_top_gdsc status stuck at 'off' > [ 291.055878] WARNING: drivers/clk/qcom/gdsc.c:178 at gdsc_toggle_logic+0x138/0x144, CPU#4: hexdump/1995 > > With the patch it turns on just fine, no issues seen. I haven't observed that behavior, and I just reconfirmed on a more recent chip. I explicitly toggled this GDSC on/off while MMNOC is collapsed and it turns on fine. And if I disable MMNOC while the GDSC is still on, then MMNOC gets stuck entering collapse. But I haven't tried on Milos, specifically. It's possible there's some behavior unique to it that I'm not aware of. Regardless, the correct solution for both issues (MMNOC getting stuck turning off or the GDSC getting stuck turning on) is the same. Which is to vote for MMNOC on behalf of the GDSC as your patch does. And is also what we've done downstream. > > As Konrad has written, originally I didn't see any issue because that > interconnect was being kept alive by simple-framebuffer where I've added > 'interconnects' to keep the framebuffer alive. However when testing > without this, the GDSC would refuse to turn on, which led me to this > patch series. > > Additionally you can see in downstream devicetree you can also see an > interconnect defined for the "cam_cc_camss_top_gdsc" node: > > https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/qcom/proprietary/devicetree/+/refs/heads/odm/rc/target/15/fp6/fps_overlay/volcano.dtsi#2943 Right, this logic was originally added to prevent MMNOC from getting stuck in collapse, rather than to prevent the GDSC from getting stuck turning on. Mike > > Regards > Luca