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AJvYcCUPui0jE3fKPDncSW0tRSFrBpAVzurlukcnXlRDqvibvoFrUQIBwgSW/1yaVsIv7xBbsMiOCQAre8JJ@vger.kernel.org X-Gm-Message-State: AOJu0YxmNiC/CZD7ui3y8j8a5jI6ZkuXbuZ+NcMIaATGsu7nfDtvfTkw ewpiif+q3iWKQzxLNYKQv1Mhqk7McP6Jul0bqOog/pmugWL3uOOgDRGu/m440MM= X-Google-Smtp-Source: AGHT+IFvgo6qt2vB4D+5CxWmwBneFTMm7VvkmB3DADmGjcvJnOJUVQG58Cd4uUg0J+6QI23+xFjXxA== X-Received: by 2002:a05:600c:4595:b0:431:3b53:105e with SMTP id 5b1f17b1804b1-4316163bccfmr91296875e9.9.1729496943898; Mon, 21 Oct 2024 00:49:03 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4316f5cc921sm47137075e9.46.2024.10.21.00.49.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Oct 2024 00:49:02 -0700 (PDT) Message-ID: Date: Mon, 21 Oct 2024 10:49:01 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 03/12] dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB Content-Language: en-US To: Krzysztof Kozlowski Cc: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, p.zabel@pengutronix.de, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea References: <20241019084738.3370489-1-claudiu.beznea.uj@bp.renesas.com> <20241019084738.3370489-4-claudiu.beznea.uj@bp.renesas.com> <5fddjnvzu2e74rtmqw6o2w5upxn6dpih3hmdbgiky75qyuvyum@ilch2rahnmih> From: Claudiu Beznea In-Reply-To: <5fddjnvzu2e74rtmqw6o2w5upxn6dpih3hmdbgiky75qyuvyum@ilch2rahnmih> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 21.10.2024 10:34, Krzysztof Kozlowski wrote: > On Mon, Oct 21, 2024 at 09:32:37AM +0200, Krzysztof Kozlowski wrote: >>> +additionalProperties: false >>> + >>> +examples: >>> + - | >>> + #include >>> + #include >>> + #include >>> + #include >>> + >>> + clock-controller@1005c000 { >>> + compatible = "renesas,r9a08g045-vbattb"; >>> + reg = <0x1005c000 0x1000>; >>> + interrupts = ; >>> + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; >>> + clock-names = "bclk", "rtx"; >>> + assigned-clocks = <&vbattb VBATTB_MUX>; >>> + assigned-clock-parents = <&vbattb VBATTB_XC>; >> >> Why are you configuring internal clocks to internal parents? That's part >> internal to this device, not DTS... or at least some explanation would >> be useful. > > From DTS I see this belongs to the board, not SoC, so makes sense. That's true. This configuration depends on the type of the input clock connected to the RTXIN, RTXOUT pins which is board specific (see below diagram): +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ Thank you, Claudiu Beznea > > Best regards, > Krzysztof >