From: Drew Fustini <fustini@kernel.org>
To: Joel Stanley <joel@jms.id.au>, Joerg Roedel <joro@8bytes.org>
Cc: Nicholas Piggin <npiggin@gmail.com>,
devicetree@vger.kernel.org,
Tomasz Jeznach <tjeznach@rivosinc.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Michael Ellerman <mpe@oss.tenstorrent.com>
Subject: Re: [RFC PATCH 1/1] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU
Date: Thu, 2 Apr 2026 13:35:19 -0700 [thread overview]
Message-ID: <ac7TByN3oQGSUpyq@x1> (raw)
In-Reply-To: <CACPK8Xc=imZXXPp-CYY39=Ww4oVDdXPS5My_R1qODzGhOD2qnw@mail.gmail.com>
On Wed, Apr 01, 2026 at 11:57:57AM +1030, Joel Stanley wrote:
> On Tue, 10 Mar 2026 at 11:09, Nicholas Piggin <npiggin@gmail.com> wrote:
> >
> > Extend the binding to cover details specific to the Tenstorrent RISC-V
> > IOMMU. In particular, a second register range is added which contains
> > M-privileged registers, e.g., PMAs and PMPs.
> >
> > The RISC-V spec S-privileged registers remain in the first register
> > range and are compatible with "riscv,iommu" so the Linux driver does not
> > notice any difference, but the binding will be used by OpenSBI and
> > potentially other M-mode software.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
>
> Drew, will you take this through the the tt soc tree?
I think it would go through Joerg's iommu tree, but I could if Joerg can
an Ack.
Thanks,
Drew
prev parent reply other threads:[~2026-04-02 20:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-10 0:38 [RFC PATCH 1/1] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU Nicholas Piggin
2026-04-01 1:27 ` Joel Stanley
2026-04-02 20:35 ` Drew Fustini [this message]
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