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Fri, 21 Jun 2024 04:25:25 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45L4PEqI029596 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 21 Jun 2024 04:25:14 GMT Received: from [10.217.216.152] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Jun 2024 21:25:08 -0700 Message-ID: Date: Fri, 21 Jun 2024 09:54:59 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] dt-bindings: clock: qcom: Add SA8775P video clock controller To: Krzysztof Kozlowski , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Bartosz Golaszewski CC: , , , , , References: <20240612-sa8775p-mm-clock-controllers-v1-0-db295a846ee7@quicinc.com> <20240612-sa8775p-mm-clock-controllers-v1-1-db295a846ee7@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: O5ggWtnhqmUe8sBytdKaDIBBNI5oHEd0 X-Proofpoint-ORIG-GUID: O5ggWtnhqmUe8sBytdKaDIBBNI5oHEd0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-20_12,2024-06-20_04,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 spamscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 clxscore=1011 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406210030 On 6/13/2024 12:58 PM, Krzysztof Kozlowski wrote: > On 12/06/2024 12:47, Taniya Das wrote: >> Add device tree bindings for the video clock controller on Qualcomm >> SA8775P platform. > > You claim it is a v1, but I saw it and already commented on this. No > changelog, no versioning, so my comments were ignored? > > Please go back to previous comments, implement then, respond and then > send v3 with all comments addressed. > Krzysztof, I mentioned the below in the cover letter of this series. Did I still miss something? Add support for videocc, camcc, dispcc0 and dispcc1 on Qualcomm SA8775P platform. These multimedia clock controller and device tree patches are split from the below series. https://lore.kernel.org/all/20240531090249.10293-1-quic_tdas@quicinc.com/ Changes in this series compared to above series: [PATCH 1/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 3/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 5/8]: Updated bindings to reference qcom,gcc.yaml [PATCH 7/8]: Split updating sleep_clk frequency to separate patch [PATCH 8/8]: Newly added to update sleep_clk frequency to 32000 > > Best regards, > Krzysztof > -- Thanks & Regards, Taniya Das.