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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9c3cff17basm547511166b.50.2026.04.07.04.05.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Apr 2026 04:05:33 -0700 (PDT) Message-ID: Date: Tue, 7 Apr 2026 13:05:31 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions and port labels To: jsandom@axon.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com> <20260404-rb5gen2-dts-v1-1-895f8fc494fc@axon.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260404-rb5gen2-dts-v1-1-895f8fc494fc@axon.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=dO6WXuZb c=1 sm=1 tr=0 ts=69d4e4ff cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=h77gEMGJAAAA:8 a=Tbjyt6IBEl-nZ4hlP0IA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=PYyYjrCoJcZo81GydsRF:22 X-Proofpoint-GUID: ERV5QmMfGbRPTeGw7L9puvghIA_EzK_X X-Proofpoint-ORIG-GUID: ERV5QmMfGbRPTeGw7L9puvghIA_EzK_X X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA3MDEwNCBTYWx0ZWRfX1LcCHKC1AdsK fKsqEi6dIMV6Bom9BiFX+IAIRWrDXiZMVH3xdiBt5Vz3iBPWhnU/REGeikwA1okMInXULZb5j7g Bl9vuz/1htYspbbLr2eBEldRgWBnMupcSkpQEcNfnRuThfuU9z+/DZcuqn79Nje+5O/GUWU87r8 ZQgbGBI6vmFzvUPt3TvNZJZf3ZHaPuQWP1gbs2ay8FpIkr8szg2vo5V8zYIZ8QG2A1U0FzSwWhF /SfwFjpY6ElcWeYDJeAtdzY6boK4qmVQvmMg1KbUwxGKLgJg/ITA9vcT9/NDKZV9xoqNwJuYHqN eBNnJeSwIwxx/Us+AZ7l6PqSYL4QFFAM4Sla2pSofAD72JdGzw+hITLJDzbE7to41w4sAZ+Jt+K MBsMtbFo7EF/VZAnMIAE79TO5HO/3AhpL3M2zWRdurb5+GPJ5zV9zQ0IIFyDG34zjoUIl5VA59V eJ7v1HpLh6+lsl9FOyA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-07_02,2026-04-07_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070104 On 4/4/26 11:50 AM, Joe Sandom via B4 Relay wrote: > From: Joe Sandom > > Add the MHI register regions to the pcie0 and pcie1 controller nodes > so that the MHI bus layer can access controller registers directly. > > Also add labels to the root port nodes (pcie0_port0, pcie1_port0) to > allow board DTS files to reference them for adding endpoint devices > to each pcie root port. > > Signed-off-by: Joe Sandom > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..d4caf4d00832d7f1e8f65bf2bc873cddadc42168 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1964,8 +1964,9 @@ pcie0: pcie@1c00000 { > <0 0x60000000 0 0xf1d>, > <0 0x60000f20 0 0xa8>, > <0 0x60001000 0 0x1000>, > - <0 0x60100000 0 0x100000>; > - reg-names = "parf", "dbi", "elbi", "atu", "config"; > + <0 0x60100000 0 0x100000>, > + <0 0x01C03000 0 0x1000>; lowercase hex please, both places > + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; Since you're touching this part of the file anyway and others asked for more changes.. could you please break up the reg-names that you're editing such that there's one entry per line and they're aligned on the opening quote, i.e. reg-names = "foo", "bar", ... ? FWIW the reg ranges you added are OK Konrad