* [PATCH 1/6] dt-bindings: i2c: qcom-cci: Document Kaanapali compatible
2025-09-25 0:02 [PATCH 0/6] media: qcom: camss: Add Kaanapali support Jingyi Wang
@ 2025-09-25 0:02 ` Jingyi Wang
2025-09-25 19:32 ` Loic Poulain
2025-09-25 0:02 ` [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding Jingyi Wang
` (5 subsequent siblings)
6 siblings, 1 reply; 27+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
Jingyi Wang, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add Kaanapali compatible consistent with CAMSS CCI interfaces. The list
of clocks for Kaanapali requires its own compat string and definition.
This changes the minimum number of `clocks` and `clock-names`.
- const: cam_top_ahb
- const: cci
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 9bc99d736343..85a1c9738afe 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -25,6 +25,7 @@ properties:
- items:
- enum:
+ - qcom,kaanapali-cci
- qcom,qcm2290-cci
- qcom,sa8775p-cci
- qcom,sc7280-cci
@@ -257,6 +258,22 @@ allOf:
- const: cpas_ahb
- const: cci
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,kaanapali-cci
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: cam_top_ahb
+ - const: cci
+
additionalProperties: false
examples:
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 1/6] dt-bindings: i2c: qcom-cci: Document Kaanapali compatible
2025-09-25 0:02 ` [PATCH 1/6] dt-bindings: i2c: qcom-cci: Document Kaanapali compatible Jingyi Wang
@ 2025-09-25 19:32 ` Loic Poulain
2025-10-15 3:15 ` Hangxiang Ma
0 siblings, 1 reply; 27+ messages in thread
From: Loic Poulain @ 2025-09-25 19:32 UTC (permalink / raw)
To: Jingyi Wang
Cc: Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Hangxiang Ma,
Bryan O'Donoghue, linux-i2c, linux-arm-msm, devicetree,
linux-kernel, linux-media, aiqun.yu, tingwei.zhang, trilok.soni,
yijie.yang
On Thu, Sep 25, 2025 at 2:02 AM Jingyi Wang
<jingyi.wang@oss.qualcomm.com> wrote:
>
> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>
> Add Kaanapali compatible consistent with CAMSS CCI interfaces. The list
> of clocks for Kaanapali requires its own compat string and definition.
> This changes the minimum number of `clocks` and `clock-names`.
>
> - const: cam_top_ahb
> - const: cci
The recently introduced qcom,qcm2290-cci has the same definition with
two clocks, ahb, and cci.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/6] dt-bindings: i2c: qcom-cci: Document Kaanapali compatible
2025-09-25 19:32 ` Loic Poulain
@ 2025-10-15 3:15 ` Hangxiang Ma
0 siblings, 0 replies; 27+ messages in thread
From: Hangxiang Ma @ 2025-10-15 3:15 UTC (permalink / raw)
To: Loic Poulain, Jingyi Wang
Cc: Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
Ack
On 9/26/2025 3:32 AM, Loic Poulain wrote:
> On Thu, Sep 25, 2025 at 2:02 AM Jingyi Wang
> <jingyi.wang@oss.qualcomm.com> wrote:
>> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>>
>> Add Kaanapali compatible consistent with CAMSS CCI interfaces. The list
>> of clocks for Kaanapali requires its own compat string and definition.
>> This changes the minimum number of `clocks` and `clock-names`.
>>
>> - const: cam_top_ahb
>> - const: cci
> The recently introduced qcom,qcm2290-cci has the same definition with
> two clocks, ahb, and cci.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-09-25 0:02 [PATCH 0/6] media: qcom: camss: Add Kaanapali support Jingyi Wang
2025-09-25 0:02 ` [PATCH 1/6] dt-bindings: i2c: qcom-cci: Document Kaanapali compatible Jingyi Wang
@ 2025-09-25 0:02 ` Jingyi Wang
2025-09-25 3:12 ` Dmitry Baryshkov
2025-10-06 20:04 ` Loic Poulain
2025-09-25 0:02 ` [PATCH 3/6] media: qcom: camss: Add Kaanapali compatible camss driver Jingyi Wang
` (4 subsequent siblings)
6 siblings, 2 replies; 27+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
Jingyi Wang, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add bindings for qcom,kaanapali-camss in order to support the camera
subsystem for Kaanapali.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
.../bindings/media/qcom,kaanapali-camss.yaml | 494 +++++++++++++++++++++
1 file changed, 494 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
new file mode 100644
index 000000000000..ed0fe6774700
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
@@ -0,0 +1,494 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Kaanapali Camera Subsystem (CAMSS)
+
+maintainers:
+ - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,kaanapali-camss
+
+ reg:
+ maxItems: 16
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ clocks:
+ maxItems: 34
+
+ clock-names:
+ items:
+ - const: camnoc_nrt_axi
+ - const: camnoc_rt_axi
+ - const: camnoc_rt_vfe0
+ - const: camnoc_rt_vfe1
+ - const: camnoc_rt_vfe2
+ - const: camnoc_rt_vfe_lite
+ - const: cam_top_ahb
+ - const: cam_top_fast_ahb
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: csiphy5
+ - const: csiphy5_timer
+ - const: gcc_hf_axi
+ - const: qdss_debug_xo
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 16
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0_mnoc
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description:
+ TFE0 GDSC - Thin Front End, Global Distributed Switch Controller.
+ - description:
+ TFE1 GDSC - Thin Front End, Global Distributed Switch Controller.
+ - description:
+ TFE2 GDSC - Thin Front End, Global Distributed Switch Controller.
+ - description:
+ Titan GDSC - Titan ISP Block Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: tfe0
+ - const: tfe1
+ - const: tfe2
+ - const: top
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.2V regulator supply to PHY refclk pll block.
+
+ vdda-phy0-supply:
+ description:
+ Phandle to 0.8V regulator supply to PHY core block.
+
+ vdda-phy1-supply:
+ description:
+ Phandle to 0.8V regulator supply to PHY core block.
+
+ vdda-phy2-supply:
+ description:
+ Phandle to 0.8V regulator supply to PHY core block.
+
+ vdda-phy3-supply:
+ description:
+ Phandle to 0.8V regulator supply to PHY core block.
+
+ vdda-phy4-supply:
+ description:
+ Phandle to 0.8V regulator supply to PHY core block.
+
+ vdda-phy5-supply:
+ description:
+ Phandle to 0.8V regulator supply to PHY core block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSI0.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSI1.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSI2.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSI3.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - vdda-pll-supply
+ - vdda-phy0-supply
+ - vdda-phy1-supply
+ - vdda-phy2-supply
+ - vdda-phy3-supply
+ - vdda-phy4-supply
+ - vdda-phy5-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,kaanapali-camcc.h>
+ #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: isp@9253000 {
+ compatible = "qcom,kaanapali-camss";
+
+ reg = <0x0 0x09253000 0x0 0x5e80>,
+ <0x0 0x09263000 0x0 0x5e80>,
+ <0x0 0x09273000 0x0 0x5e80>,
+ <0x0 0x092d3000 0x0 0x3880>,
+ <0x0 0x092e7000 0x0 0x3880>,
+ <0x0 0x09523000 0x0 0x2000>,
+ <0x0 0x09525000 0x0 0x2000>,
+ <0x0 0x09527000 0x0 0x2000>,
+ <0x0 0x09529000 0x0 0x2000>,
+ <0x0 0x0952b000 0x0 0x2000>,
+ <0x0 0x0952d000 0x0 0x2000>,
+ <0x0 0x09151000 0x0 0x20000>,
+ <0x0 0x09171000 0x0 0x20000>,
+ <0x0 0x09191000 0x0 0x20000>,
+ <0x0 0x092dc000 0x0 0x1300>,
+ <0x0 0x092f0000 0x0 0x1300>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_rt_vfe0",
+ "camnoc_rt_vfe1",
+ "camnoc_rt_vfe2",
+ "camnoc_rt_vfe_lite",
+ "cam_top_ahb",
+ "cam_top_fast_ahb",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "gcc_hf_axi",
+ "qdss_debug_xo",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "tfe0",
+ "tfe1",
+ "tfe2",
+ "top";
+
+ vdda-pll-supply = <&vreg_l1d_1p2>;
+ vdda-phy0-supply = <&vreg_l3i_0p8>;
+ vdda-phy1-supply = <&vreg_l3i_0p8>;
+ vdda-phy2-supply = <&vreg_l3d_0p8>;
+ vdda-phy3-supply = <&vreg_l3i_0p8>;
+ vdda-phy4-supply = <&vreg_l3d_0p8>;
+ vdda-phy5-supply = <&vreg_l3i_0p8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy_ep0: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-09-25 0:02 ` [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding Jingyi Wang
@ 2025-09-25 3:12 ` Dmitry Baryshkov
2025-10-06 20:04 ` Loic Poulain
1 sibling, 0 replies; 27+ messages in thread
From: Dmitry Baryshkov @ 2025-09-25 3:12 UTC (permalink / raw)
To: Jingyi Wang
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma, Bryan O'Donoghue, linux-i2c, linux-arm-msm,
devicetree, linux-kernel, linux-media, aiqun.yu, tingwei.zhang,
trilok.soni, yijie.yang
On Wed, Sep 24, 2025 at 05:02:49PM -0700, Jingyi Wang wrote:
> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>
> Add bindings for qcom,kaanapali-camss in order to support the camera
> subsystem for Kaanapali.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-camss.yaml | 494 +++++++++++++++++++++
> 1 file changed, 494 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
> new file mode 100644
> index 000000000000..ed0fe6774700
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
> @@ -0,0 +1,494 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Kaanapali Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,kaanapali-camss
> +
> + reg:
> + maxItems: 16
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + clocks:
> + maxItems: 34
> +
> + clock-names:
> + items:
> + - const: camnoc_nrt_axi
> + - const: camnoc_rt_axi
> + - const: camnoc_rt_vfe0
> + - const: camnoc_rt_vfe1
> + - const: camnoc_rt_vfe2
> + - const: camnoc_rt_vfe_lite
> + - const: cam_top_ahb
> + - const: cam_top_fast_ahb
> + - const: csid
> + - const: csid_csiphy_rx
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: csiphy5
> + - const: csiphy5_timer
> + - const: gcc_hf_axi
> + - const: qdss_debug_xo
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe2
> + - const: vfe2_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 16
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_0_mnoc
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + items:
> + - description:
> + TFE0 GDSC - Thin Front End, Global Distributed Switch Controller.
> + - description:
> + TFE1 GDSC - Thin Front End, Global Distributed Switch Controller.
> + - description:
> + TFE2 GDSC - Thin Front End, Global Distributed Switch Controller.
> + - description:
> + Titan GDSC - Titan ISP Block Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: tfe0
> + - const: tfe1
> + - const: tfe2
> + - const: top
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.2V regulator supply to PHY refclk pll block.
> +
> + vdda-phy0-supply:
> + description:
> + Phandle to 0.8V regulator supply to PHY core block.
> +
> + vdda-phy1-supply:
> + description:
> + Phandle to 0.8V regulator supply to PHY core block.
> +
> + vdda-phy2-supply:
> + description:
> + Phandle to 0.8V regulator supply to PHY core block.
> +
> + vdda-phy3-supply:
> + description:
> + Phandle to 0.8V regulator supply to PHY core block.
> +
> + vdda-phy4-supply:
> + description:
> + Phandle to 0.8V regulator supply to PHY core block.
> +
> + vdda-phy5-supply:
> + description:
> + Phandle to 0.8V regulator supply to PHY core block.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data on CSI0.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data on CSI1.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data on CSI2.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data on CSI3.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + bus-type:
> + enum:
> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - vdda-pll-supply
> + - vdda-phy0-supply
> + - vdda-phy1-supply
> + - vdda-phy2-supply
> + - vdda-phy3-supply
> + - vdda-phy4-supply
> + - vdda-phy5-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/clock/qcom,kaanapali-camcc.h>
> + #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
This will break if corresponding patches are not merged (and they were
not even declared as dependencies). Please drop platform-specific
includes and use ephemeral DT nodes instead (you don't need any of
indices, just the nodes).
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: isp@9253000 {
> + compatible = "qcom,kaanapali-camss";
> +
> + reg = <0x0 0x09253000 0x0 0x5e80>,
> + <0x0 0x09263000 0x0 0x5e80>,
> + <0x0 0x09273000 0x0 0x5e80>,
> + <0x0 0x092d3000 0x0 0x3880>,
> + <0x0 0x092e7000 0x0 0x3880>,
> + <0x0 0x09523000 0x0 0x2000>,
> + <0x0 0x09525000 0x0 0x2000>,
> + <0x0 0x09527000 0x0 0x2000>,
> + <0x0 0x09529000 0x0 0x2000>,
> + <0x0 0x0952b000 0x0 0x2000>,
> + <0x0 0x0952d000 0x0 0x2000>,
> + <0x0 0x09151000 0x0 0x20000>,
> + <0x0 0x09171000 0x0 0x20000>,
> + <0x0 0x09191000 0x0 0x20000>,
> + <0x0 0x092dc000 0x0 0x1300>,
> + <0x0 0x092f0000 0x0 0x1300>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY5_CLK>,
> + <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
> + <&camcc CAM_CC_TFE_0_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_1_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_2_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> + clock-names = "camnoc_nrt_axi",
> + "camnoc_rt_axi",
> + "camnoc_rt_vfe0",
> + "camnoc_rt_vfe1",
> + "camnoc_rt_vfe2",
> + "camnoc_rt_vfe_lite",
> + "cam_top_ahb",
> + "cam_top_fast_ahb",
> + "csid",
> + "csid_csiphy_rx",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "csiphy5",
> + "csiphy5_timer",
> + "gcc_hf_axi",
> + "qdss_debug_xo",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe2",
> + "vfe2_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> +
> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_0_mnoc";
> +
> + iommus = <&apps_smmu 0x1c00 0x00>;
> +
> + power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
> + <&camcc CAM_CC_TFE_1_GDSC>,
> + <&camcc CAM_CC_TFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "tfe0",
> + "tfe1",
> + "tfe2",
> + "top";
> +
> + vdda-pll-supply = <&vreg_l1d_1p2>;
> + vdda-phy0-supply = <&vreg_l3i_0p8>;
> + vdda-phy1-supply = <&vreg_l3i_0p8>;
> + vdda-phy2-supply = <&vreg_l3d_0p8>;
> + vdda-phy3-supply = <&vreg_l3i_0p8>;
> + vdda-phy4-supply = <&vreg_l3d_0p8>;
> + vdda-phy5-supply = <&vreg_l3i_0p8>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + csiphy_ep0: endpoint {
> + clock-lanes = <7>;
> + data-lanes = <0 1>;
> + remote-endpoint = <&sensor_ep>;
> + };
> + };
> + };
> + };
> + };
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-09-25 0:02 ` [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding Jingyi Wang
2025-09-25 3:12 ` Dmitry Baryshkov
@ 2025-10-06 20:04 ` Loic Poulain
2025-10-15 3:21 ` Hangxiang Ma
1 sibling, 1 reply; 27+ messages in thread
From: Loic Poulain @ 2025-10-06 20:04 UTC (permalink / raw)
To: Jingyi Wang, Bryan O'Donoghue
Cc: Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Hangxiang Ma,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
Hi folks,
On Thu, Sep 25, 2025 at 2:03 AM Jingyi Wang
<jingyi.wang@oss.qualcomm.com> wrote:
>
> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>
> Add bindings for qcom,kaanapali-camss in order to support the camera
> subsystem for Kaanapali.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,kaanapali-camss.yaml | 494 +++++++++++++++++++++
> 1 file changed, 494 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
> new file mode 100644
> index 000000000000..ed0fe6774700
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
> @@ -0,0 +1,494 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Kaanapali Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,kaanapali-camss
> +
> + reg:
> + maxItems: 16
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
Wouldn't it make sense to simplify this and have different camss nodes
for the 'main' and 'lite' paths?
[...]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-06 20:04 ` Loic Poulain
@ 2025-10-15 3:21 ` Hangxiang Ma
2025-10-16 5:52 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Hangxiang Ma @ 2025-10-15 3:21 UTC (permalink / raw)
To: Loic Poulain, Jingyi Wang, Bryan O'Donoghue
Cc: Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 10/7/2025 4:04 AM, Loic Poulain wrote:
> Hi folks,
>
> On Thu, Sep 25, 2025 at 2:03 AM Jingyi Wang
> <jingyi.wang@oss.qualcomm.com> wrote:
>> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>>
>> Add bindings for qcom,kaanapali-camss in order to support the camera
>> subsystem for Kaanapali.
>>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> .../bindings/media/qcom,kaanapali-camss.yaml | 494 +++++++++++++++++++++
>> 1 file changed, 494 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
>> new file mode 100644
>> index 000000000000..ed0fe6774700
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
>> @@ -0,0 +1,494 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Kaanapali Camera Subsystem (CAMSS)
>> +
>> +maintainers:
>> + - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> +
>> +description:
>> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,kaanapali-camss
>> +
>> + reg:
>> + maxItems: 16
>> +
>> + reg-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid2
>> + - const: csid_lite0
>> + - const: csid_lite1
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: csiphy3
>> + - const: csiphy4
>> + - const: csiphy5
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe2
>> + - const: vfe_lite0
>> + - const: vfe_lite1
> Wouldn't it make sense to simplify this and have different camss nodes
> for the 'main' and 'lite' paths?
>
> [...]
No such plan till now. Other series may take this into consideration.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-15 3:21 ` Hangxiang Ma
@ 2025-10-16 5:52 ` Krzysztof Kozlowski
2025-10-16 8:47 ` Loic Poulain
0 siblings, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-16 5:52 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Jingyi Wang, Bryan O'Donoghue
Cc: Robert Foss, Andi Shyti, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 15/10/2025 05:21, Hangxiang Ma wrote:
>>> + - const: csiphy4
>>> + - const: csiphy5
>>> + - const: vfe0
>>> + - const: vfe1
>>> + - const: vfe2
>>> + - const: vfe_lite0
>>> + - const: vfe_lite1
>> Wouldn't it make sense to simplify this and have different camss nodes
>> for the 'main' and 'lite' paths?
>>
>> [...]
> No such plan till now. Other series may take this into consideration.
We don't care much about your plan. You are expected to send correct
hardware description.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-16 5:52 ` Krzysztof Kozlowski
@ 2025-10-16 8:47 ` Loic Poulain
2025-10-16 10:43 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Loic Poulain @ 2025-10-16 8:47 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Hangxiang Ma, Jingyi Wang, Bryan O'Donoghue, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bryan O'Donoghue, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, linux-i2c, linux-arm-msm, devicetree,
linux-kernel, linux-media, aiqun.yu, tingwei.zhang, trilok.soni,
yijie.yang
On Thu, Oct 16, 2025 at 7:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 15/10/2025 05:21, Hangxiang Ma wrote:
> >>> + - const: csiphy4
> >>> + - const: csiphy5
> >>> + - const: vfe0
> >>> + - const: vfe1
> >>> + - const: vfe2
> >>> + - const: vfe_lite0
> >>> + - const: vfe_lite1
> >> Wouldn't it make sense to simplify this and have different camss nodes
> >> for the 'main' and 'lite' paths?
> >>
> >> [...]
> > No such plan till now. Other series may take this into consideration.
>
> We don't care much about your plan. You are expected to send correct
> hardware description.
To be fair, other platforms like sc8280xp-camss already have the
all-in big camss node.
Point is that if Lite and Main blocks are distinct enough we could
have two simpler nodes.
Would it make things any better from a dts and camss perspective?
camss: isp@9253000 {
compatible = "qcom,kaanapali-camss";
[...]
}
camss-lite:ips@9273000 {
compatible = "qcom,kaanapali-lite-camss";
[...]
}
That approach would create two distinct CAMSS instances and separate
media pipelines.
However, it may not work with the current implementation, as the CSI
PHYs would need to be shared between them.
I guess this should be part of the broader discussion around
splitting/busifying CAMSS.
Regards,
Loic
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-16 8:47 ` Loic Poulain
@ 2025-10-16 10:43 ` Krzysztof Kozlowski
2025-10-20 10:16 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-16 10:43 UTC (permalink / raw)
To: Loic Poulain
Cc: Hangxiang Ma, Jingyi Wang, Bryan O'Donoghue, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bryan O'Donoghue, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, linux-i2c, linux-arm-msm, devicetree,
linux-kernel, linux-media, aiqun.yu, tingwei.zhang, trilok.soni,
yijie.yang
On 16/10/2025 10:47, Loic Poulain wrote:
> On Thu, Oct 16, 2025 at 7:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 15/10/2025 05:21, Hangxiang Ma wrote:
>>>>> + - const: csiphy4
>>>>> + - const: csiphy5
>>>>> + - const: vfe0
>>>>> + - const: vfe1
>>>>> + - const: vfe2
>>>>> + - const: vfe_lite0
>>>>> + - const: vfe_lite1
>>>> Wouldn't it make sense to simplify this and have different camss nodes
>>>> for the 'main' and 'lite' paths?
>>>>
>>>> [...]
>>> No such plan till now. Other series may take this into consideration.
>>
>> We don't care much about your plan. You are expected to send correct
>> hardware description.
>
> To be fair, other platforms like sc8280xp-camss already have the
> all-in big camss node.
> Point is that if Lite and Main blocks are distinct enough we could
> have two simpler nodes.
> Would it make things any better from a dts and camss perspective?
>
> camss: isp@9253000 {
> compatible = "qcom,kaanapali-camss";
> [...]
> }
>
> camss-lite:ips@9273000 {
> compatible = "qcom,kaanapali-lite-camss";
> [...]
> }
>
> That approach would create two distinct CAMSS instances and separate
> media pipelines.
> However, it may not work with the current implementation, as the CSI
> PHYs would need to be shared between them.
>
> I guess this should be part of the broader discussion around
> splitting/busifying CAMSS.
And this discussion CAN happen now, stopping this camss and any future
camss till we conclude the discussion. Whatever internal plans of that
teams are, rejecting technical discussion based on "no plans for that"
is a really bad argument, only stalling this patchset and raising eyebrows.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-16 10:43 ` Krzysztof Kozlowski
@ 2025-10-20 10:16 ` Krzysztof Kozlowski
2025-10-20 10:56 ` Bryan O'Donoghue
0 siblings, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2025-10-20 10:16 UTC (permalink / raw)
To: Loic Poulain
Cc: Hangxiang Ma, Jingyi Wang, Bryan O'Donoghue, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bryan O'Donoghue, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, linux-i2c, linux-arm-msm, devicetree,
linux-kernel, linux-media, aiqun.yu, tingwei.zhang, trilok.soni,
yijie.yang
On 16/10/2025 12:43, Krzysztof Kozlowski wrote:
> On 16/10/2025 10:47, Loic Poulain wrote:
>> On Thu, Oct 16, 2025 at 7:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>
>>> On 15/10/2025 05:21, Hangxiang Ma wrote:
>>>>>> + - const: csiphy4
>>>>>> + - const: csiphy5
>>>>>> + - const: vfe0
>>>>>> + - const: vfe1
>>>>>> + - const: vfe2
>>>>>> + - const: vfe_lite0
>>>>>> + - const: vfe_lite1
>>>>> Wouldn't it make sense to simplify this and have different camss nodes
>>>>> for the 'main' and 'lite' paths?
>>>>>
>>>>> [...]
>>>> No such plan till now. Other series may take this into consideration.
>>>
>>> We don't care much about your plan. You are expected to send correct
>>> hardware description.
>>
>> To be fair, other platforms like sc8280xp-camss already have the
>> all-in big camss node.
>> Point is that if Lite and Main blocks are distinct enough we could
>> have two simpler nodes.
>> Would it make things any better from a dts and camss perspective?
>>
>> camss: isp@9253000 {
>> compatible = "qcom,kaanapali-camss";
>> [...]
>> }
>>
>> camss-lite:ips@9273000 {
>> compatible = "qcom,kaanapali-lite-camss";
>> [...]
>> }
>>
>> That approach would create two distinct CAMSS instances and separate
>> media pipelines.
>> However, it may not work with the current implementation, as the CSI
>> PHYs would need to be shared between them.
>>
>> I guess this should be part of the broader discussion around
>> splitting/busifying CAMSS.
>
> And this discussion CAN happen now, stopping this camss and any future
> camss till we conclude the discussion. Whatever internal plans of that
> teams are, rejecting technical discussion based on "no plans for that"
> is a really bad argument, only stalling this patchset and raising eyebrows.
To be clear, I expect Loic's comment to be fully and technically
addressed, not with "no plan for that".
This blocks this patchset and any new versions.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-20 10:16 ` Krzysztof Kozlowski
@ 2025-10-20 10:56 ` Bryan O'Donoghue
2025-10-20 17:42 ` Vijay Kumar Tumati
[not found] ` <4fb3c83a-2bef-4b15-b676-73e8e8957452@oss.qualcomm.com>
0 siblings, 2 replies; 27+ messages in thread
From: Bryan O'Donoghue @ 2025-10-20 10:56 UTC (permalink / raw)
To: Krzysztof Kozlowski, Loic Poulain
Cc: Hangxiang Ma, Jingyi Wang, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 20/10/2025 11:16, Krzysztof Kozlowski wrote:
> On 16/10/2025 12:43, Krzysztof Kozlowski wrote:
>> On 16/10/2025 10:47, Loic Poulain wrote:
>>> On Thu, Oct 16, 2025 at 7:52 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>
>>>> On 15/10/2025 05:21, Hangxiang Ma wrote:
>>>>>>> + - const: csiphy4
>>>>>>> + - const: csiphy5
>>>>>>> + - const: vfe0
>>>>>>> + - const: vfe1
>>>>>>> + - const: vfe2
>>>>>>> + - const: vfe_lite0
>>>>>>> + - const: vfe_lite1
>>>>>> Wouldn't it make sense to simplify this and have different camss nodes
>>>>>> for the 'main' and 'lite' paths?
>>>>>>
>>>>>> [...]
>>>>> No such plan till now. Other series may take this into consideration.
>>>>
>>>> We don't care much about your plan. You are expected to send correct
>>>> hardware description.
>>>
>>> To be fair, other platforms like sc8280xp-camss already have the
>>> all-in big camss node.
>>> Point is that if Lite and Main blocks are distinct enough we could
>>> have two simpler nodes.
>>> Would it make things any better from a dts and camss perspective?
>>>
>>> camss: isp@9253000 {
>>> compatible = "qcom,kaanapali-camss";
>>> [...]
>>> }
>>>
>>> camss-lite:ips@9273000 {
>>> compatible = "qcom,kaanapali-lite-camss";
>>> [...]
>>> }
>>>
>>> That approach would create two distinct CAMSS instances and separate
>>> media pipelines.
>>> However, it may not work with the current implementation, as the CSI
>>> PHYs would need to be shared between them.
>>>
>>> I guess this should be part of the broader discussion around
>>> splitting/busifying CAMSS.
>>
>> And this discussion CAN happen now, stopping this camss and any future
>> camss till we conclude the discussion. Whatever internal plans of that
>> teams are, rejecting technical discussion based on "no plans for that"
>> is a really bad argument, only stalling this patchset and raising eyebrows.
>
>
> To be clear, I expect Loic's comment to be fully and technically
> addressed, not with "no plan for that".
>
> This blocks this patchset and any new versions.
>
> Best regards,
> Krzysztof
I think we should stick with the existing bindings.
There is no "lite" ISP there are so-called lite blocks within the CAMSS
block.
It makes sense to split out the PHYs from this block as they have their
own power-rails but, if you look at the block diagrams for this IP there
is no specific ISP lite, there are merely blocks within the camera
called lite.
It might be nice to structure things like this
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi with each component
separated out into its own node with its own compat string but, I'd have
a hard time justifying changing up the bindings we already have for that
reason - aside from anything else - all of those components in CAMSS
live inside of the TITAN_TOP_GDSC which is the power-domain for the
whole camera system.
So not meaning to answer for Hangxiang but, I think the compelling logic
here is to stick to and extend the existing bindings.
So in fact I have no problem with the bindings as submitted - not
including the regular fixups these types of submissions entail.
---
bod
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-20 10:56 ` Bryan O'Donoghue
@ 2025-10-20 17:42 ` Vijay Kumar Tumati
[not found] ` <4fb3c83a-2bef-4b15-b676-73e8e8957452@oss.qualcomm.com>
1 sibling, 0 replies; 27+ messages in thread
From: Vijay Kumar Tumati @ 2025-10-20 17:42 UTC (permalink / raw)
To: Bryan O'Donoghue, Krzysztof Kozlowski, Loic Poulain
Cc: Hangxiang Ma, Jingyi Wang, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 10/20/2025 3:56 AM, Bryan O'Donoghue wrote:
> On 20/10/2025 11:16, Krzysztof Kozlowski wrote:
>> On 16/10/2025 12:43, Krzysztof Kozlowski wrote:
>>> On 16/10/2025 10:47, Loic Poulain wrote:
>>>> On Thu, Oct 16, 2025 at 7:52 AM Krzysztof Kozlowski
>>>> <krzk@kernel.org> wrote:
>>>>>
>>>>> On 15/10/2025 05:21, Hangxiang Ma wrote:
>>>>>>>> + - const: csiphy4
>>>>>>>> + - const: csiphy5
>>>>>>>> + - const: vfe0
>>>>>>>> + - const: vfe1
>>>>>>>> + - const: vfe2
>>>>>>>> + - const: vfe_lite0
>>>>>>>> + - const: vfe_lite1
>>>>>>> Wouldn't it make sense to simplify this and have different camss
>>>>>>> nodes
>>>>>>> for the 'main' and 'lite' paths?
>>>>>>>
>>>>>>> [...]
>>>>>> No such plan till now. Other series may take this into
>>>>>> consideration.
>>>>>
>>>>> We don't care much about your plan. You are expected to send correct
>>>>> hardware description.
>>>>
>>>> To be fair, other platforms like sc8280xp-camss already have the
>>>> all-in big camss node.
>>>> Point is that if Lite and Main blocks are distinct enough we could
>>>> have two simpler nodes.
>>>> Would it make things any better from a dts and camss perspective?
>>>>
>>>> camss: isp@9253000 {
>>>> compatible = "qcom,kaanapali-camss";
>>>> [...]
>>>> }
>>>>
>>>> camss-lite:ips@9273000 {
>>>> compatible = "qcom,kaanapali-lite-camss";
>>>> [...]
>>>> }
>>>>
>>>> That approach would create two distinct CAMSS instances and separate
>>>> media pipelines.
>>>> However, it may not work with the current implementation, as the CSI
>>>> PHYs would need to be shared between them.
>>>>
>>>> I guess this should be part of the broader discussion around
>>>> splitting/busifying CAMSS.
>>>
>>> And this discussion CAN happen now, stopping this camss and any future
>>> camss till we conclude the discussion. Whatever internal plans of that
>>> teams are, rejecting technical discussion based on "no plans for that"
>>> is a really bad argument, only stalling this patchset and raising
>>> eyebrows.
>>
>>
>> To be clear, I expect Loic's comment to be fully and technically
>> addressed, not with "no plan for that".
>>
>> This blocks this patchset and any new versions.
>>
>> Best regards,
>> Krzysztof
>
> I think we should stick with the existing bindings.
>
> There is no "lite" ISP there are so-called lite blocks within the
> CAMSS block.
>
> It makes sense to split out the PHYs from this block as they have
> their own power-rails but, if you look at the block diagrams for this
> IP there is no specific ISP lite, there are merely blocks within the
> camera called lite.
>
> It might be nice to structure things like this
> arch/arm64/boot/dts/rockchip/rk356x-base.dtsi with each component
> separated out into its own node with its own compat string but, I'd
> have a hard time justifying changing up the bindings we already have
> for that reason - aside from anything else - all of those components
> in CAMSS live inside of the TITAN_TOP_GDSC which is the power-domain
> for the whole camera system.
>
> So not meaning to answer for Hangxiang but, I think the compelling
> logic here is to stick to and extend the existing bindings.
>
> So in fact I have no problem with the bindings as submitted - not
> including the regular fixups these types of submissions entail.
>
> ---
> bod
>
Hi @Bryan, @Krzysztof, just my two cents. I think we should consider
separating CSIPHY, CSID, IFE and IFE Lite into distinct DT nodes. Having
a modular DT structure brings in several advantages,
1. Simple to manage with much better readability.
2. Better control to disable certain HW modules from DT.
3. Less error prone as we don't need to maintain long lists of
clocks or other resources against their names. Accordingly, easy to review.
4. No need to maintain resource lists within the CAMSS driver to
identify the resources specific to the HW block. Offers centralized
control for the HW resources.
5. Allows re use between the platforms when a same version of a
subset of HW modules is carried over to future chip sets.
6. Is more scalable when we add more functionality to the CAMSS driver.
7. Finally, it brings in parallel development ability with
engineers (within the local teams) working on different HW modules
within camera subsystem.
If not for the current patches in the pipeline, if you are comfortable
with this approach, we will try to push the changes for the future chip
sets with the modular bindings, leaving the existing SOC drivers and
bindings untouched (if that's recommended). Please let us know your
thoughts. Thanks.
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread[parent not found: <4fb3c83a-2bef-4b15-b676-73e8e8957452@oss.qualcomm.com>]
* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
[not found] ` <4fb3c83a-2bef-4b15-b676-73e8e8957452@oss.qualcomm.com>
@ 2025-10-20 18:09 ` Bryan O'Donoghue
2025-10-20 18:12 ` Bryan O'Donoghue
0 siblings, 1 reply; 27+ messages in thread
From: Bryan O'Donoghue @ 2025-10-20 18:09 UTC (permalink / raw)
To: Vijay Kumar Tumati, Krzysztof Kozlowski, Loic Poulain
Cc: Hangxiang Ma, Jingyi Wang, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 20/10/2025 18:37, Vijay Kumar Tumati wrote:
> Hi @Bryan, @Krzyszto, just my two cents. I think we should consider
> separating CSIPHY, CSID, IFE and IFE Lite into distinct DT nodes. Having
> a modular DT structure brings in several advantages,
>
> 1. Simple to manage with much better readability.
> 2. Better control to disable certain HW modules from DT.
> 3. Less error prone as we don't need to maintain long lists of clocks
> or other resources against their names. Accordingly, easy to review.
> 4. No need to maintain resource lists within the CAMSS driver to
> identify the resources specific to the HW block. Offers centralized
> control for the HW resources.
> 5. Allows re use between the platforms when a same version of a subset
> of HW modules is carried over to future chip sets.
> 6. Is more scalable when we add more functionality to the CAMSS driver.
> 7. Finally, it brings in parallel development ability with engineers
> (within the local teams) working on different HW modules within
> camera subsystem.
>
> If not for the current patches in the pipeline, if you are comfortable
> with this approach, we will try to push the changes for the future chip
> sets with the modular bindings, leaving the existing SOC drivers and
> bindings untouched (if that's recommended). Please let us know your
> thoughts. Thanks.
I think the Rockchip breaking up of blocks is structurally nice and how
you would do things if you were adding stuff in from scratch.
Old Irish Joke:
Man in car stops asks local: "How do I get to Tralee"
Local scratches head under cap: "Well; I wouldn't start from here"
We have existing bindings and one message that has been repeated is that
new bindings should follow old bindings of a similar class.
There's a good argument to separate out the CSIPHY - because it has
distinct power-rails and has a real-world effect for users - in that
their PCB.
It would really be up to yourselves to justify why it is a whole new
binding is required i.e. what benefit does it actually bring, and to
show, prove, that existing users of this driver either benefit or don't
suffer i.e. doing work for old silicon too, not just the new stuff.
If the only objective you have is to facilitate co-existence of a
downstream driver with upstream bindings.
Anyway there's absolutely no reason to hold up this series or any
subsequent series on a hypothetical rewrite unless/until that rewrite
gets proposed, reviewed and applied.
---
bod
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding
2025-10-20 18:09 ` Bryan O'Donoghue
@ 2025-10-20 18:12 ` Bryan O'Donoghue
0 siblings, 0 replies; 27+ messages in thread
From: Bryan O'Donoghue @ 2025-10-20 18:12 UTC (permalink / raw)
To: Bryan O'Donoghue, Vijay Kumar Tumati, Krzysztof Kozlowski,
Loic Poulain
Cc: Hangxiang Ma, Jingyi Wang, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media, aiqun.yu,
tingwei.zhang, trilok.soni, yijie.yang
On 20/10/2025 19:09, Bryan O'Donoghue wrote:
> If the only objective you have is to facilitate co-existence of a
> downstream driver with upstream bindings.
[sic] Then that's a no. The beneficiary has to be upstream.
---
bod
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 3/6] media: qcom: camss: Add Kaanapali compatible camss driver
2025-09-25 0:02 [PATCH 0/6] media: qcom: camss: Add Kaanapali support Jingyi Wang
2025-09-25 0:02 ` [PATCH 1/6] dt-bindings: i2c: qcom-cci: Document Kaanapali compatible Jingyi Wang
2025-09-25 0:02 ` [PATCH 2/6] dt-bindings: media: camss: Add qcom,kaanapali-camss binding Jingyi Wang
@ 2025-09-25 0:02 ` Jingyi Wang
2025-09-25 0:02 ` [PATCH 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Jingyi Wang
` (3 subsequent siblings)
6 siblings, 0 replies; 27+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
Jingyi Wang, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add support for kaanapali in the camss driver. Add high level resource
information along with the bus bandwidth votes. Module level detailed
resource information will be enumerated in the following patches of the
series.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 2fbcd0e343aa..4a5caf54c116 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -34,6 +34,20 @@
static const struct parent_dev_ops vfe_parent_dev_ops;
+static const struct resources_icc icc_res_kaanapali[] = {
+ /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 925857,
+ .icc_bw_tbl.peak = 925857,
+ },
+ {
+ .name = "hf_0_mnoc",
+ .icc_bw_tbl.avg = 925857,
+ .icc_bw_tbl.peak = 925857,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8x16[] = {
/* CSIPHY0 */
{
@@ -4291,6 +4305,13 @@ static void camss_remove(struct platform_device *pdev)
camss_genpd_cleanup(camss);
}
+static const struct camss_resources kaanapali_resources = {
+ .version = CAMSS_KAANAPALI,
+ .pd_name = "top",
+ .icc_res = icc_res_kaanapali,
+ .icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
+};
+
static const struct camss_resources msm8916_resources = {
.version = CAMSS_8x16,
.csiphy_res = csiphy_res_8x16,
@@ -4467,6 +4488,7 @@ static const struct camss_resources x1e80100_resources = {
};
static const struct of_device_id camss_dt_match[] = {
+ { .compatible = "qcom,kaanapali-camss", .data = &kaanapali_resources },
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index a70fbc78ccc3..9fc9e04b9dab 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -89,6 +89,7 @@ enum camss_version {
CAMSS_845,
CAMSS_8550,
CAMSS_8775P,
+ CAMSS_KAANAPALI,
CAMSS_X1E80100,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY
2025-09-25 0:02 [PATCH 0/6] media: qcom: camss: Add Kaanapali support Jingyi Wang
` (2 preceding siblings ...)
2025-09-25 0:02 ` [PATCH 3/6] media: qcom: camss: Add Kaanapali compatible camss driver Jingyi Wang
@ 2025-09-25 0:02 ` Jingyi Wang
2025-09-25 12:57 ` Bryan O'Donoghue
2025-09-25 0:02 ` [PATCH 5/6] media: qcom: camss: csid: Add support for CSID 1080 Jingyi Wang
` (2 subsequent siblings)
6 siblings, 1 reply; 27+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
Jingyi Wang, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add more detailed resource information for CSIPHY devices in the camss
driver along with the support for v2.4.0 in the 2 phase CSIPHY driver
that is responsible for the PHY lane register configuration, module
reset and interrupt handling.
This change adds 'cmn_status_offset' variable in 'csidphy_device_regs'
structure. It helps adapt the offset to the common status registers that
is different in v2.4.0 from others.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 138 ++++++++++++++++++++-
drivers/media/platform/qcom/camss/camss-csiphy.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 107 ++++++++++++++++
3 files changed, 240 insertions(+), 6 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index a229ba04b158..ecb91d3688ca 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -46,7 +46,7 @@
#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
-#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n))
+#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, bias, n) ((offset) + (bias) + 0x4 * (n))
#define CSIPHY_DEFAULT_PARAMS 0
#define CSIPHY_LANE_ENABLE 1
@@ -587,6 +587,123 @@ csiphy_lane_regs lane_regs_sm8550[] = {
{0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
};
+/* GEN2 2.4.0 2PH DPHY mode */
+static const struct
+csiphy_lane_regs lane_regs_kaanapali[] = {
+ /* LN 0 */
+ {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN 2 */
+ {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN 4 */
+ {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN 6 */
+ {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+ {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL},
+ {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL},
+ {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+
+ /* LN CLK */
+ {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
+ {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
/* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
static const struct
csiphy_lane_regs lane_regs_x1e80100[] = {
@@ -714,13 +831,13 @@ static void csiphy_hw_version_read(struct csiphy_device *csiphy,
CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
hw_version = readl_relaxed(csiphy->base +
- CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12));
+ CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 12));
hw_version |= readl_relaxed(csiphy->base +
- CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8;
+ CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 13)) << 8;
hw_version |= readl_relaxed(csiphy->base +
- CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16;
+ CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 14)) << 16;
hw_version |= readl_relaxed(csiphy->base +
- CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24;
+ CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 15)) << 24;
dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
}
@@ -749,7 +866,8 @@ static irqreturn_t csiphy_isr(int irq, void *dev)
for (i = 0; i < 11; i++) {
int c = i + 22;
u8 val = readl_relaxed(csiphy->base +
- CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i));
+ CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset,
+ regs->cmn_status_offset, i));
writel_relaxed(val, csiphy->base +
CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c));
@@ -915,6 +1033,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8775P:
+ case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = true;
break;
@@ -989,6 +1108,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
csiphy->regs = regs;
regs->offset = 0x800;
+ regs->cmn_status_offset = 0xb0;
switch (csiphy->camss->res->version) {
case CAMSS_845:
@@ -1023,6 +1143,12 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_regs = &lane_regs_sa8775p[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
break;
+ case CAMSS_KAANAPALI:
+ regs->lane_regs = &lane_regs_kaanapali[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali);
+ regs->offset = 0x1000;
+ regs->cmn_status_offset = 0x138;
+ break;
default:
break;
}
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
index 895f80003c44..f5bf02cd32d5 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.h
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
@@ -90,6 +90,7 @@ struct csiphy_device_regs {
const struct csiphy_lane_regs *lane_regs;
int lane_array_size;
u32 offset;
+ u32 cmn_status_offset;
};
struct csiphy_device {
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 4a5caf54c116..542122fba825 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -34,6 +34,111 @@
static const struct parent_dev_ops vfe_parent_dev_ops;
+static const struct camss_subdev_resources csiphy_res_kaanapali[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdda-phy0", "vdda-pll" },
+ .clock = { "csiphy0", "csiphy0_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdda-phy1", "vdda-pll" },
+ .clock = { "csiphy1", "csiphy1_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdda-phy2", "vdda-pll" },
+ .clock = { "csiphy2", "csiphy2_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = { "vdda-phy3", "vdda-pll" },
+ .clock = { "csiphy3", "csiphy3_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY4 */
+ {
+ .regulators = { "vdda-phy4", "vdda-pll" },
+ .clock = { "csiphy4", "csiphy4_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy4" },
+ .interrupt = { "csiphy4" },
+ .csiphy = {
+ .id = 4,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY5 */
+ {
+ .regulators = { "vdda-phy5", "vdda-pll" },
+ .clock = { "csiphy5", "csiphy5_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy5" },
+ .interrupt = { "csiphy5" },
+ .csiphy = {
+ .id = 5,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
/* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
{
@@ -4308,8 +4413,10 @@ static void camss_remove(struct platform_device *pdev)
static const struct camss_resources kaanapali_resources = {
.version = CAMSS_KAANAPALI,
.pd_name = "top",
+ .csiphy_res = csiphy_res_kaanapali,
.icc_res = icc_res_kaanapali,
.icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
};
static const struct camss_resources msm8916_resources = {
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY
2025-09-25 0:02 ` [PATCH 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Jingyi Wang
@ 2025-09-25 12:57 ` Bryan O'Donoghue
2025-10-15 3:41 ` Hangxiang Ma
0 siblings, 1 reply; 27+ messages in thread
From: Bryan O'Donoghue @ 2025-09-25 12:57 UTC (permalink / raw)
To: Jingyi Wang, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Hangxiang Ma,
Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
On 25/09/2025 01:02, Jingyi Wang wrote:
> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>
> Add more detailed resource information for CSIPHY devices in the camss
> driver along with the support for v2.4.0 in the 2 phase CSIPHY driver
> that is responsible for the PHY lane register configuration, module
> reset and interrupt handling.
>
> This change adds 'cmn_status_offset' variable in 'csidphy_device_regs'
> structure. It helps adapt the offset to the common status registers that
> is different in v2.4.0 from others.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 138 ++++++++++++++++++++-
> drivers/media/platform/qcom/camss/camss-csiphy.h | 1 +
> drivers/media/platform/qcom/camss/camss.c | 107 ++++++++++++++++
> 3 files changed, 240 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index a229ba04b158..ecb91d3688ca 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -46,7 +46,7 @@
> #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
> #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
> #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
> -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n))
> +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, bias, n) ((offset) + (bias) + 0x4 * (n))
You need to explain this bias parameter in the commit log.
>
> #define CSIPHY_DEFAULT_PARAMS 0
> #define CSIPHY_LANE_ENABLE 1
> @@ -587,6 +587,123 @@ csiphy_lane_regs lane_regs_sm8550[] = {
> {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> };
>
> +/* GEN2 2.4.0 2PH DPHY mode */
You need to call out the process node in this comment, per the other
recent additions.
> +static const struct
> +csiphy_lane_regs lane_regs_kaanapali[] = {
> + /* LN 0 */
> + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN 2 */
> + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN 4 */
> + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN 6 */
> + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
> + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL},
> + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL},
> + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
> +
> + /* LN CLK */
> + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
> + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> +};
> +
> /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
> static const struct
> csiphy_lane_regs lane_regs_x1e80100[] = {
> @@ -714,13 +831,13 @@ static void csiphy_hw_version_read(struct csiphy_device *csiphy,
> CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
>
> hw_version = readl_relaxed(csiphy->base +
> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12));
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 12));
> hw_version |= readl_relaxed(csiphy->base +
> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8;
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 13)) << 8;
> hw_version |= readl_relaxed(csiphy->base +
> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16;
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 14)) << 16;
> hw_version |= readl_relaxed(csiphy->base +
> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24;
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, regs->cmn_status_offset, 15)) << 24;
>
> dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
> }
> @@ -749,7 +866,8 @@ static irqreturn_t csiphy_isr(int irq, void *dev)
> for (i = 0; i < 11; i++) {
> int c = i + 22;
> u8 val = readl_relaxed(csiphy->base +
> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i));
> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset,
> + regs->cmn_status_offset, i));
>
> writel_relaxed(val, csiphy->base +
> CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c));
> @@ -915,6 +1033,7 @@ static bool csiphy_is_gen2(u32 version)
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8775P:
> + case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> ret = true;
> break;
> @@ -989,6 +1108,7 @@ static int csiphy_init(struct csiphy_device *csiphy)
>
> csiphy->regs = regs;
> regs->offset = 0x800;
> + regs->cmn_status_offset = 0xb0;
>
> switch (csiphy->camss->res->version) {
> case CAMSS_845:
> @@ -1023,6 +1143,12 @@ static int csiphy_init(struct csiphy_device *csiphy)
> regs->lane_regs = &lane_regs_sa8775p[0];
> regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> break;
> + case CAMSS_KAANAPALI:
> + regs->lane_regs = &lane_regs_kaanapali[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali);
> + regs->offset = 0x1000;
> + regs->cmn_status_offset = 0x138;
I don't think a second offset is warranted
You could acheive the required offset with offset = 0x1138; and a comment.
Perhaps I'm not seeing it but seems like an additional - fixed - fluff
variable.
> + break;
> default:
> break;
> }
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
> index 895f80003c44..f5bf02cd32d5 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.h
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
> @@ -90,6 +90,7 @@ struct csiphy_device_regs {
> const struct csiphy_lane_regs *lane_regs;
> int lane_array_size;
> u32 offset;
> + u32 cmn_status_offset;
> };
>
> struct csiphy_device {
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 4a5caf54c116..542122fba825 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -34,6 +34,111 @@
>
> static const struct parent_dev_ops vfe_parent_dev_ops;
>
> +static const struct camss_subdev_resources csiphy_res_kaanapali[] = {
> + /* CSIPHY0 */
> + {
> + .regulators = { "vdda-phy0", "vdda-pll" },
> + .clock = { "csiphy0", "csiphy0_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy0" },
> + .interrupt = { "csiphy0" },
> + .csiphy = {
> + .id = 0,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY1 */
> + {
> + .regulators = { "vdda-phy1", "vdda-pll" },
> + .clock = { "csiphy1", "csiphy1_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy1" },
> + .interrupt = { "csiphy1" },
> + .csiphy = {
> + .id = 1,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY2 */
> + {
> + .regulators = { "vdda-phy2", "vdda-pll" },
> + .clock = { "csiphy2", "csiphy2_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy2" },
> + .interrupt = { "csiphy2" },
> + .csiphy = {
> + .id = 2,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY3 */
> + {
> + .regulators = { "vdda-phy3", "vdda-pll" },
> + .clock = { "csiphy3", "csiphy3_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy3" },
> + .interrupt = { "csiphy3" },
> + .csiphy = {
> + .id = 3,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY4 */
> + {
> + .regulators = { "vdda-phy4", "vdda-pll" },
> + .clock = { "csiphy4", "csiphy4_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy4" },
> + .interrupt = { "csiphy4" },
> + .csiphy = {
> + .id = 4,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> + /* CSIPHY5 */
> + {
> + .regulators = { "vdda-phy5", "vdda-pll" },
> + .clock = { "csiphy5", "csiphy5_timer",
> + "cam_top_ahb", "cam_top_fast_ahb" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "csiphy5" },
> + .interrupt = { "csiphy5" },
> + .csiphy = {
> + .id = 5,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sdm845
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_kaanapali[] = {
> /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
> {
> @@ -4308,8 +4413,10 @@ static void camss_remove(struct platform_device *pdev)
> static const struct camss_resources kaanapali_resources = {
> .version = CAMSS_KAANAPALI,
> .pd_name = "top",
> + .csiphy_res = csiphy_res_kaanapali,
> .icc_res = icc_res_kaanapali,
> .icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
> + .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
> };
>
> static const struct camss_resources msm8916_resources = {
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY
2025-09-25 12:57 ` Bryan O'Donoghue
@ 2025-10-15 3:41 ` Hangxiang Ma
0 siblings, 0 replies; 27+ messages in thread
From: Hangxiang Ma @ 2025-10-15 3:41 UTC (permalink / raw)
To: Bryan O'Donoghue, Jingyi Wang, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang
On 9/25/2025 8:57 PM, Bryan O'Donoghue wrote:
> On 25/09/2025 01:02, Jingyi Wang wrote:
>> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>>
>> Add more detailed resource information for CSIPHY devices in the camss
>> driver along with the support for v2.4.0 in the 2 phase CSIPHY driver
>> that is responsible for the PHY lane register configuration, module
>> reset and interrupt handling.
>>
>> This change adds 'cmn_status_offset' variable in 'csidphy_device_regs'
>> structure. It helps adapt the offset to the common status registers that
>> is different in v2.4.0 from others.
>>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 138
>> ++++++++++++++++++++-
>> drivers/media/platform/qcom/camss/camss-csiphy.h | 1 +
>> drivers/media/platform/qcom/camss/camss.c | 107
>> ++++++++++++++++
>> 3 files changed, 240 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> index a229ba04b158..ecb91d3688ca 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> @@ -46,7 +46,7 @@
>> #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
>> #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
>> #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
>> -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) +
>> 0xb0 + 0x4 * (n))
>> +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, bias, n) ((offset)
>> + (bias) + 0x4 * (n))
>
> You need to explain this bias parameter in the commit log.
Ack. Now rename the 'bias' parameter the same as 'common_status_offset'
to remove ambiguity.
>>
>> #define CSIPHY_DEFAULT_PARAMS 0
>> #define CSIPHY_LANE_ENABLE 1
>> @@ -587,6 +587,123 @@ csiphy_lane_regs lane_regs_sm8550[] = {
>> {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> };
>>
>> +/* GEN2 2.4.0 2PH DPHY mode */
>
> You need to call out the process node in this comment, per the other
> recent additions.
Ack
>> +static const struct
>> +csiphy_lane_regs lane_regs_kaanapali[] = {
>> + /* LN 0 */
>> + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
>> + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
>> + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
>> +
>> + /* LN 2 */
>> + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
>> + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
>> + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
>> +
>> + /* LN 4 */
>> + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
>> + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
>> + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
>> +
>> + /* LN 6 */
>> + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL},
>> + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
>> +
>> + /* LN CLK */
>> + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +};
>> +
>> /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */
>> static const struct
>> csiphy_lane_regs lane_regs_x1e80100[] = {
>> @@ -714,13 +831,13 @@ static void csiphy_hw_version_read(struct
>> csiphy_device *csiphy,
>> CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
>>
>> hw_version = readl_relaxed(csiphy->base +
>> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12));
>> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset,
>> regs->cmn_status_offset, 12));
>> hw_version |= readl_relaxed(csiphy->base +
>> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8;
>> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset,
>> regs->cmn_status_offset, 13)) << 8;
>> hw_version |= readl_relaxed(csiphy->base +
>> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16;
>> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset,
>> regs->cmn_status_offset, 14)) << 16;
>> hw_version |= readl_relaxed(csiphy->base +
>> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24;
>> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset,
>> regs->cmn_status_offset, 15)) << 24;
>>
>> dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
>> }
>> @@ -749,7 +866,8 @@ static irqreturn_t csiphy_isr(int irq, void *dev)
>> for (i = 0; i < 11; i++) {
>> int c = i + 22;
>> u8 val = readl_relaxed(csiphy->base +
>> - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i));
>> + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset,
>> + regs->cmn_status_offset, i));
>>
>> writel_relaxed(val, csiphy->base +
>> CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c));
>> @@ -915,6 +1033,7 @@ static bool csiphy_is_gen2(u32 version)
>> case CAMSS_845:
>> case CAMSS_8550:
>> case CAMSS_8775P:
>> + case CAMSS_KAANAPALI:
>> case CAMSS_X1E80100:
>> ret = true;
>> break;
>> @@ -989,6 +1108,7 @@ static int csiphy_init(struct csiphy_device
>> *csiphy)
>>
>> csiphy->regs = regs;
>> regs->offset = 0x800;
>> + regs->cmn_status_offset = 0xb0;
>>
>> switch (csiphy->camss->res->version) {
>> case CAMSS_845:
>> @@ -1023,6 +1143,12 @@ static int csiphy_init(struct csiphy_device
>> *csiphy)
>> regs->lane_regs = &lane_regs_sa8775p[0];
>> regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
>> break;
>> + case CAMSS_KAANAPALI:
>> + regs->lane_regs = &lane_regs_kaanapali[0];
>> + regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali);
>> + regs->offset = 0x1000;
>> + regs->cmn_status_offset = 0x138;
>
> I don't think a second offset is warranted
>
> You could acheive the required offset with offset = 0x1138; and a
> comment.
>
> Perhaps I'm not seeing it but seems like an additional - fixed - fluff
> variable.
Necessary to add another variable here. The 'offset' parameter denotes
the address offset between base and the common register. But the
'common_status_offset' denotes the offset between common registers and
status registers.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 5/6] media: qcom: camss: csid: Add support for CSID 1080
2025-09-25 0:02 [PATCH 0/6] media: qcom: camss: Add Kaanapali support Jingyi Wang
` (3 preceding siblings ...)
2025-09-25 0:02 ` [PATCH 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Jingyi Wang
@ 2025-09-25 0:02 ` Jingyi Wang
2025-09-25 23:30 ` Bryan O'Donoghue
2025-09-25 0:02 ` [PATCH 6/6] media: qcom: camss: vfe: Add support for VFE 1080 Jingyi Wang
2025-09-25 22:48 ` [PATCH 0/6] media: qcom: camss: Add Kaanapali support Bryan O'Donoghue
6 siblings, 1 reply; 27+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
Jingyi Wang, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Atiya Kailany
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add more detailed resource information for CSID devices along with the
driver for CSID 1080 that is responsible for CSID register
configuration, module reset and IRQ handling for BUF_DONE events.
In this CSID version, RUP and AUP update values are split into two
registers along with a SET register. Accordingly , enhance the CSID
interface to accommodate both the legacy combined reg_update and the
split RUP and AUP updates.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
.../media/platform/qcom/camss/camss-csid-1080.c | 379 +++++++++++++++++++++
.../media/platform/qcom/camss/camss-csid-1080.h | 25 ++
drivers/media/platform/qcom/camss/camss-csid.h | 9 +-
drivers/media/platform/qcom/camss/camss.c | 80 +++++
drivers/media/platform/qcom/camss/camss.h | 1 +
6 files changed, 494 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 23960d02877d..3a7ed4f5a004 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -8,6 +8,7 @@ qcom-camss-objs += \
camss-csid-4-7.o \
camss-csid-340.o \
camss-csid-680.o \
+ camss-csid-1080.o \
camss-csid-gen2.o \
camss-csid-gen3.o \
camss-csiphy-2ph-1-0.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c b/drivers/media/platform/qcom/camss/camss-csid-1080.c
new file mode 100644
index 000000000000..ab5944d4ff34
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-csid-1080.c
+ *
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/types.h>
+#include <linux/v4l2-controls.h>
+#include "camss.h"
+#include "camss-csid.h"
+#include "camss-csid-1080.h"
+
+/* Reset and Command Registers */
+#define CSID_RST_CFG 0x108
+#define RST_MODE BIT(0)
+#define RST_LOCATION BIT(4)
+
+/* Reset and Command Registers */
+#define CSID_RST_CMD 0x10C
+#define SELECT_HW_RST BIT(0)
+#define SELECT_IRQ_RST BIT(2)
+#define CSID_IRQ_CMD 0x110
+#define IRQ_CMD_CLEAR BIT(0)
+
+/* Register Update Commands, RUP/AUP */
+#define CSID_RUP_CMD 0x114
+#define RUP_RDIN BIT(8)
+#define CSID_AUP_CMD 0x118
+#define AUP_RDIN BIT(8)
+#define CSID_RUP_AUP_CMD 0x11C
+#define RUP_SET BIT(0)
+#define MUP BIT(4)
+
+/* Top level interrupt registers */
+#define CSID_TOP_IRQ_STATUS 0x180
+#define CSID_TOP_IRQ_MASK 0x184
+#define CSID_TOP_IRQ_CLEAR 0x188
+#define CSID_TOP_IRQ_SET 0x18C
+#define INFO_RST_DONE BIT(0)
+#define CSI2_RX_IRQ_STATUS BIT(2)
+#define BUF_DONE_IRQ_STATUS BIT(3)
+#define RDIn_IRQ_STATUS_OFFSET 16
+#define TOP_IRQ_STATUS_2 BIT(31)
+
+/* Buffer done interrupt registers */
+#define CSID_BUF_DONE_IRQ_STATUS 0x1A0
+#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16
+#define CSID_BUF_DONE_IRQ_MASK 0x1A4
+#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8
+#define CSID_BUF_DONE_IRQ_SET 0x1AC
+
+/* CSI2 RX interrupt registers */
+#define CSID_CSI2_RX_IRQ_STATUS 0x1B0
+#define CSID_CSI2_RX_IRQ_MASK 0x1B4
+#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8
+#define CSID_CSI2_RX_IRQ_SET 0x1BC
+
+/* CSI2 RX Configuration */
+#define CSID_CSI2_RX_CFG0 0x880
+#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
+#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
+#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSID_CSI2_RX_CFG1 0x884
+#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
+#define CSI2_RX_CFG1_VC_MODE BIT(2)
+
+/* CSIPHY to hardware PHY selector mapping */
+#define CSID_CSIPHY_ID_BASE_OFFSET 1
+
+#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4 : 5)
+
+/* RDI Configuration */
+#define CSID_RDI_CFG0(rdi) \
+ ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi))
+#define RDI_CFG0_RETIME_BS BIT(5)
+#define RDI_CFG0_TIMESTAMP_EN BIT(6)
+#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
+#define RDI_CFG0_DECODE_FORMAT 12
+#define RDI_CFG0_DT 16
+#define RDI_CFG0_VC 22
+#define RDI_CFG0_EN BIT(31)
+
+/* RDI Control and Configuration */
+#define CSID_RDI_CTRL(rdi) \
+ ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi))
+#define RDI_CTRL_START_CMD BIT(0)
+
+#define CSID_RDI_CFG1(rdi) \
+ ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi))
+#define RDI_CFG1_DROP_H_EN BIT(5)
+#define RDI_CFG1_DROP_V_EN BIT(6)
+#define RDI_CFG1_CROP_H_EN BIT(7)
+#define RDI_CFG1_CROP_V_EN BIT(8)
+#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
+
+/* RDI Pixel Store Configuration */
+#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi))
+#define RDI_PIX_STORE_CFG0_EN BIT(0)
+#define RDI_PIX_STORE_CFG0_MIN_HBI 1
+
+/* RDI IRQ Status in wrapper */
+#define CSID_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi)))
+#define CSID_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi)))
+#define CSID_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi)))
+#define INFO_RUP_DONE BIT(23)
+
+static void __csid_aup_rup_trigger(struct csid_device *csid)
+{
+ /* trigger SET in combined register */
+ writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
+}
+
+static void __csid_aup_update(struct csid_device *csid, int port_id)
+{
+ csid->aup_update |= AUP_RDIN << port_id;
+ writel(csid->aup_update, csid->base + CSID_AUP_CMD);
+
+ __csid_aup_rup_trigger(csid);
+}
+
+static void __csid_reg_update(struct csid_device *csid, int port_id)
+{
+ csid->rup_update |= RUP_RDIN << port_id;
+ writel(csid->rup_update, csid->base + CSID_RUP_CMD);
+
+ __csid_aup_rup_trigger(csid);
+}
+
+static void __csid_configure_rx(struct csid_device *csid,
+ struct csid_phy_config *phy)
+{
+ int val;
+
+ val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
+ val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
+ val |= (phy->csiphy_id + CSID_CSIPHY_ID_BASE_OFFSET)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ writel(val, csid->base + CSID_CSI2_RX_CFG0);
+
+ val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+}
+
+static void __csid_configure_rx_vc(struct csid_device *csid,
+ struct csid_phy_config *phy, int vc)
+{
+ int val;
+
+ if (vc > 3) {
+ val = readl(csid->base + CSID_CSI2_RX_CFG1);
+ val |= CSI2_RX_CFG1_VC_MODE;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+ }
+}
+
+static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
+{
+ int val = 0;
+
+ if (enable)
+ val = RDI_CTRL_START_CMD;
+
+ writel(val, csid->base + CSID_RDI_CTRL(rdi));
+}
+
+static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
+{
+ u32 val;
+
+ /* Configure pixel store to allow absorption of hblanking or idle time.
+ * This helps with horizontal crop and prevents line buffer conflicts.
+ * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
+ * and just enable the pixel store functionality.
+ */
+ val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
+ writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
+}
+
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
+{
+ u32 val;
+ u8 lane_cnt = csid->phy.lane_cnt;
+
+ /* Source pads matching RDI channels on hardware.
+ * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
+ */
+ struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
+ const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
+ csid->res->formats->nformats,
+ input_format->code);
+
+ if (!lane_cnt)
+ lane_cnt = 4;
+
+ val = RDI_CFG0_TIMESTAMP_EN;
+ val |= RDI_CFG0_TIMESTAMP_STB_SEL;
+ val |= RDI_CFG0_RETIME_BS;
+
+ /* note: for non-RDI path, this should be format->decode_format */
+ val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
+ val |= vc << RDI_CFG0_VC;
+ val |= format->data_type << RDI_CFG0_DT;
+ writel(val, csid->base + CSID_RDI_CFG0(vc));
+
+ val = RDI_CFG1_PACKING_FORMAT_MIPI;
+ writel(val, csid->base + CSID_RDI_CFG1(vc));
+
+ /* Configure pixel store using dedicated register in 1080 */
+ if (!csid_is_lite(csid))
+ __csid_configure_rdi_pix_store(csid, vc);
+
+ val = 0;
+ writel(val, csid->base + CSID_RDI_CTRL(vc));
+
+ val = readl(csid->base + CSID_RDI_CFG0(vc));
+
+ if (enable)
+ val |= RDI_CFG0_EN;
+
+ writel(val, csid->base + CSID_RDI_CFG0(vc));
+}
+
+static void csid_configure_stream_1080(struct csid_device *csid, u8 enable)
+{
+ u8 i;
+ u8 vc;
+
+ __csid_configure_rx(csid, &csid->phy);
+
+ for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_1080; vc++) {
+ if (csid->phy.en_vc & BIT(vc)) {
+ __csid_configure_rdi_stream(csid, enable, vc);
+ __csid_configure_rx_vc(csid, &csid->phy, vc);
+
+ for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++)
+ __csid_aup_update(csid, vc);
+
+ __csid_reg_update(csid, vc);
+
+ __csid_ctrl_rdi(csid, enable, vc);
+ }
+ }
+}
+
+static int csid_configure_testgen_pattern_1080(struct csid_device *csid,
+ s32 val)
+{
+ return 0;
+}
+
+static void csid_subdev_reg_update_1080(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ /* No explicit clear required */
+ if (!clear)
+ __csid_aup_update(csid, port_id);
+}
+
+/**
+ * csid_isr - CSID module interrupt service routine
+ * @irq: Interrupt line
+ * @dev: CSID device
+ *
+ * Return IRQ_HANDLED on success
+ */
+static irqreturn_t csid_isr_1080(int irq, void *dev)
+{
+ struct csid_device *csid = dev;
+ u32 val, buf_done_val;
+ u8 reset_done;
+ int i;
+
+ val = readl(csid->base + CSID_TOP_IRQ_STATUS);
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+
+ reset_done = val & INFO_RST_DONE;
+
+ buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
+ writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++)
+ if (csid->phy.en_vc & BIT(i)) {
+ val = readl(csid->base + CSID_RDIN_IRQ_STATUS(i));
+ writel(val, csid->base + CSID_RDIN_IRQ_CLEAR(i));
+
+ if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) {
+ /*
+ * buf done and RUP IRQ have been moved to CSID from VFE.
+ * Once CSID received buf done, need notify VFE of this
+ * event and trigger VFE to handle buf done process.
+ */
+ camss_buf_done(csid->camss, csid->id, i);
+ }
+ }
+
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ if (reset_done)
+ complete(&csid->reset_complete);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * csid_reset - Trigger reset on CSID module and wait to complete
+ * @csid: CSID device
+ *
+ * Return 0 on success or a negative error code otherwise
+ */
+static int csid_reset_1080(struct csid_device *csid)
+{
+ unsigned long time;
+ u32 val;
+ int i;
+
+ reinit_completion(&csid->reset_complete);
+
+ val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+ writel(val, csid->base + CSID_TOP_IRQ_MASK);
+
+ val = 0;
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ /* only need to clear Buffer Done IRQ Status here,
+ * RUP Done IRQ Status will be cleared once isr
+ * strobe generated by CSID_RST_CMD
+ */
+ val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
+ }
+ }
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
+
+ /* Clear all IRQ status with CLEAR bits set */
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ val = RST_LOCATION | RST_MODE;
+ writel(val, csid->base + CSID_RST_CFG);
+
+ val = SELECT_HW_RST | SELECT_IRQ_RST;
+ writel(val, csid->base + CSID_RST_CMD);
+
+ time = wait_for_completion_timeout(&csid->reset_complete,
+ msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
+
+ if (!time) {
+ dev_err(csid->camss->dev, "CSID reset timeout\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void csid_subdev_init_1080(struct csid_device *csid)
+{
+ csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
+}
+
+const struct csid_hw_ops csid_ops_1080 = {
+ .configure_stream = csid_configure_stream_1080,
+ .configure_testgen_pattern = csid_configure_testgen_pattern_1080,
+ .hw_version = csid_hw_version,
+ .isr = csid_isr_1080,
+ .reset = csid_reset_1080,
+ .src_pad_code = csid_src_pad_code,
+ .subdev_init = csid_subdev_init_1080,
+ .reg_update = csid_subdev_reg_update_1080,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.h b/drivers/media/platform/qcom/camss/camss-csid-1080.h
new file mode 100644
index 000000000000..f526f3168e33
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-1080.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * camss-csid-1080.h
+ *
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module Generation 3
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#ifndef __QC_MSM_CAMSS_CSID_1080_H__
+#define __QC_MSM_CAMSS_CSID_1080_H__
+
+#define DECODE_FORMAT_UNCOMPRESSED_8_BIT 0x1
+#define DECODE_FORMAT_UNCOMPRESSED_10_BIT 0x2
+#define DECODE_FORMAT_UNCOMPRESSED_12_BIT 0x3
+#define DECODE_FORMAT_UNCOMPRESSED_14_BIT 0x4
+#define DECODE_FORMAT_UNCOMPRESSED_16_BIT 0x5
+#define DECODE_FORMAT_UNCOMPRESSED_20_BIT 0x6
+#define DECODE_FORMAT_UNCOMPRESSED_24_BIT 0x7
+#define DECODE_FORMAT_PAYLOAD_ONLY 0xf
+
+#define PLAIN_FORMAT_PLAIN8 0x0 /* supports DPCM, UNCOMPRESSED_6/8_BIT */
+#define PLAIN_FORMAT_PLAIN16 0x1 /* supports DPCM, UNCOMPRESSED_10/16_BIT */
+#define PLAIN_FORMAT_PLAIN32 0x2 /* supports UNCOMPRESSED_20_BIT */
+
+#endif /* __QC_MSM_CAMSS_CSID_1080_H__ */
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index aedc96ed84b2..465f05590679 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -154,7 +154,13 @@ struct csid_device {
void __iomem *base;
u32 irq;
char irq_name[30];
- u32 reg_update;
+ union {
+ u32 reg_update;
+ struct {
+ u32 rup_update;
+ u32 aup_update;
+ };
+ };
struct camss_clock *clock;
int nclocks;
struct regulator_bulk_data *supplies;
@@ -215,6 +221,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
extern const struct csid_hw_ops csid_ops_340;
extern const struct csid_hw_ops csid_ops_680;
+extern const struct csid_hw_ops csid_ops_1080;
extern const struct csid_hw_ops csid_ops_gen2;
extern const struct csid_hw_ops csid_ops_gen3;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 542122fba825..74a8ad3cb728 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -139,6 +139,84 @@ static const struct camss_subdev_resources csiphy_res_kaanapali[] = {
},
};
+static const struct camss_subdev_resources csid_res_kaanapali[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_1080,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
/* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
{
@@ -4414,9 +4492,11 @@ static const struct camss_resources kaanapali_resources = {
.version = CAMSS_KAANAPALI,
.pd_name = "top",
.csiphy_res = csiphy_res_kaanapali,
+ .csid_res = csid_res_kaanapali,
.icc_res = icc_res_kaanapali,
.icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
.csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
+ .csid_num = ARRAY_SIZE(csid_res_kaanapali),
};
static const struct camss_resources msm8916_resources = {
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 9fc9e04b9dab..876cd2a64cbe 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -41,6 +41,7 @@
(to_camss_index(ptr_module, index)->dev)
#define CAMSS_RES_MAX 17
+#define CAMSS_INIT_BUF_COUNT 2
struct camss_subdev_resources {
char *regulators[CAMSS_RES_MAX];
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 5/6] media: qcom: camss: csid: Add support for CSID 1080
2025-09-25 0:02 ` [PATCH 5/6] media: qcom: camss: csid: Add support for CSID 1080 Jingyi Wang
@ 2025-09-25 23:30 ` Bryan O'Donoghue
2025-10-15 3:44 ` Hangxiang Ma
0 siblings, 1 reply; 27+ messages in thread
From: Bryan O'Donoghue @ 2025-09-25 23:30 UTC (permalink / raw)
To: Jingyi Wang, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Hangxiang Ma,
Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, Atiya Kailany
On 25/09/2025 01:02, Jingyi Wang wrote:
> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>
> Add more detailed resource information for CSID devices along with the
> driver for CSID 1080 that is responsible for CSID register
> configuration, module reset and IRQ handling for BUF_DONE events.
>
> In this CSID version, RUP and AUP update values are split into two
> registers along with a SET register. Accordingly , enhance the CSID
> interface to accommodate both the legacy combined reg_update and the
> split RUP and AUP updates.
>
> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 1 +
> .../media/platform/qcom/camss/camss-csid-1080.c | 379 +++++++++++++++++++++
> .../media/platform/qcom/camss/camss-csid-1080.h | 25 ++
> drivers/media/platform/qcom/camss/camss-csid.h | 9 +-
> drivers/media/platform/qcom/camss/camss.c | 80 +++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 6 files changed, 494 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index 23960d02877d..3a7ed4f5a004 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -8,6 +8,7 @@ qcom-camss-objs += \
> camss-csid-4-7.o \
> camss-csid-340.o \
> camss-csid-680.o \
> + camss-csid-1080.o \
> camss-csid-gen2.o \
> camss-csid-gen3.o \
> camss-csiphy-2ph-1-0.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c b/drivers/media/platform/qcom/camss/camss-csid-1080.c
> new file mode 100644
> index 000000000000..ab5944d4ff34
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c
> @@ -0,0 +1,379 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * camss-csid-1080.c
> + *
> + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
> + *
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/types.h>
> +#include <linux/v4l2-controls.h>
> +#include "camss.h"
> +#include "camss-csid.h"
> +#include "camss-csid-1080.h"
> +
> +/* Reset and Command Registers */
> +#define CSID_RST_CFG 0x108
> +#define RST_MODE BIT(0)
> +#define RST_LOCATION BIT(4)
> +
> +/* Reset and Command Registers */
> +#define CSID_RST_CMD 0x10C
> +#define SELECT_HW_RST BIT(0)
> +#define SELECT_IRQ_RST BIT(2)
> +#define CSID_IRQ_CMD 0x110
> +#define IRQ_CMD_CLEAR BIT(0)
> +
> +/* Register Update Commands, RUP/AUP */
> +#define CSID_RUP_CMD 0x114
> +#define RUP_RDIN BIT(8)
> +#define CSID_AUP_CMD 0x118
> +#define AUP_RDIN BIT(8)
> +#define CSID_RUP_AUP_CMD 0x11C
> +#define RUP_SET BIT(0)
> +#define MUP BIT(4)
> +
> +/* Top level interrupt registers */
> +#define CSID_TOP_IRQ_STATUS 0x180
> +#define CSID_TOP_IRQ_MASK 0x184
> +#define CSID_TOP_IRQ_CLEAR 0x188
> +#define CSID_TOP_IRQ_SET 0x18C
> +#define INFO_RST_DONE BIT(0)
> +#define CSI2_RX_IRQ_STATUS BIT(2)
> +#define BUF_DONE_IRQ_STATUS BIT(3)
> +#define RDIn_IRQ_STATUS_OFFSET 16
> +#define TOP_IRQ_STATUS_2 BIT(31)
> +
> +/* Buffer done interrupt registers */
> +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0
> +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16
> +#define CSID_BUF_DONE_IRQ_MASK 0x1A4
> +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8
> +#define CSID_BUF_DONE_IRQ_SET 0x1AC
> +
> +/* CSI2 RX interrupt registers */
> +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0
> +#define CSID_CSI2_RX_IRQ_MASK 0x1B4
> +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8
> +#define CSID_CSI2_RX_IRQ_SET 0x1BC
> +
> +/* CSI2 RX Configuration */
> +#define CSID_CSI2_RX_CFG0 0x880
> +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
> +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
> +#define CSI2_RX_CFG0_PHY_NUM_SEL 20
> +#define CSID_CSI2_RX_CFG1 0x884
> +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
> +#define CSI2_RX_CFG1_VC_MODE BIT(2)
> +
> +/* CSIPHY to hardware PHY selector mapping */
> +#define CSID_CSIPHY_ID_BASE_OFFSET 1
Please align to the existing namespace and now that I look at it, try to
aggregate some of these defines into one place.
Its a bit mindless repeating defines/code in silos within the same driver.
e.g.
grep -r -e CSID_CSIPHY_ID_BASE_OFFSET -e CSI2_RX_CFG0_PHY_SEL_BASE_IDX
drivers/media/platform/qcom/camss/*
drivers/media/platform/qcom/camss/camss-csid-1080.c:#define
CSID_CSIPHY_ID_BASE_OFFSET 1
drivers/media/platform/qcom/camss/camss-csid-1080.c: val |=
(phy->csiphy_id + CSID_CSIPHY_ID_BASE_OFFSET)
drivers/media/platform/qcom/camss/camss-csid-680.c:#define
CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
drivers/media/platform/qcom/camss/camss-csid-680.c: val |=
(phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) <<
CSI2_RX_CFG0_PHY_NUM_SEL;
drivers/media/platform/qcom/camss/camss-csid-gen3.c:#define
CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
drivers/media/platform/qcom/camss/camss-csid-gen3.c: val |=
(phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) <<
CSI2_RX_CFG0_PHY_NUM_SEL;
Expectation for v2 here is to review defines ensure the names are
consistent with what's upstream and where possible moving common defines
into one header.
> +
> +#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4 : 5)
> +
> +/* RDI Configuration */
> +#define CSID_RDI_CFG0(rdi) \
> + ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi))
> +#define RDI_CFG0_RETIME_BS BIT(5)
> +#define RDI_CFG0_TIMESTAMP_EN BIT(6)
> +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
> +#define RDI_CFG0_DECODE_FORMAT 12
> +#define RDI_CFG0_DT 16
> +#define RDI_CFG0_VC 22
> +#define RDI_CFG0_EN BIT(31)
> +
> +/* RDI Control and Configuration */
> +#define CSID_RDI_CTRL(rdi) \
> + ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi))
> +#define RDI_CTRL_START_CMD BIT(0)
> +
> +#define CSID_RDI_CFG1(rdi) \
> + ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi))
> +#define RDI_CFG1_DROP_H_EN BIT(5)
> +#define RDI_CFG1_DROP_V_EN BIT(6)
> +#define RDI_CFG1_CROP_H_EN BIT(7)
> +#define RDI_CFG1_CROP_V_EN BIT(8)
> +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
> +
> +/* RDI Pixel Store Configuration */
> +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi))
> +#define RDI_PIX_STORE_CFG0_EN BIT(0)
> +#define RDI_PIX_STORE_CFG0_MIN_HBI 1
> +
> +/* RDI IRQ Status in wrapper */
> +#define CSID_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi)))
> +#define CSID_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi)))
> +#define CSID_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi)))
> +#define INFO_RUP_DONE BIT(23)
> +
> +static void __csid_aup_rup_trigger(struct csid_device *csid)
> +{
> + /* trigger SET in combined register */
> + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
> +}
> +
> +static void __csid_aup_update(struct csid_device *csid, int port_id)
> +{
> + csid->aup_update |= AUP_RDIN << port_id;
> + writel(csid->aup_update, csid->base + CSID_AUP_CMD);
> +
> + __csid_aup_rup_trigger(csid);
> +}
> +
> +static void __csid_reg_update(struct csid_device *csid, int port_id)
> +{
> + csid->rup_update |= RUP_RDIN << port_id;
> + writel(csid->rup_update, csid->base + CSID_RUP_CMD);
> +
> + __csid_aup_rup_trigger(csid);
> +}
> +
> +static void __csid_configure_rx(struct csid_device *csid,
> + struct csid_phy_config *phy)
> +{
> + int val;
> +
> + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
> + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
> + val |= (phy->csiphy_id + CSID_CSIPHY_ID_BASE_OFFSET)
> + << CSI2_RX_CFG0_PHY_NUM_SEL;
> + writel(val, csid->base + CSID_CSI2_RX_CFG0);
> +
> + val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
> +}
> +
> +static void __csid_configure_rx_vc(struct csid_device *csid,
> + struct csid_phy_config *phy, int vc)
> +{
> + int val;
> +
> + if (vc > 3) {
> + val = readl(csid->base + CSID_CSI2_RX_CFG1);
> + val |= CSI2_RX_CFG1_VC_MODE;
> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
> + }
> +}
> +
> +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
> +{
> + int val = 0;
> +
> + if (enable)
> + val = RDI_CTRL_START_CMD;
> +
> + writel(val, csid->base + CSID_RDI_CTRL(rdi));
> +}
> +
> +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
> +{
> + u32 val;
> +
> + /* Configure pixel store to allow absorption of hblanking or idle time.
> + * This helps with horizontal crop and prevents line buffer conflicts.
> + * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
> + * and just enable the pixel store functionality.
> + */
> + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
> + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
> +}
> +
> +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
> +{
> + u32 val;
> + u8 lane_cnt = csid->phy.lane_cnt;
> +
> + /* Source pads matching RDI channels on hardware.
> + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
> + */
> + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
> + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
> + csid->res->formats->nformats,
> + input_format->code);
> +
> + if (!lane_cnt)
> + lane_cnt = 4;
> +
> + val = RDI_CFG0_TIMESTAMP_EN;
> + val |= RDI_CFG0_TIMESTAMP_STB_SEL;
> + val |= RDI_CFG0_RETIME_BS;
> +
> + /* note: for non-RDI path, this should be format->decode_format */
> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
> + val |= vc << RDI_CFG0_VC;
> + val |= format->data_type << RDI_CFG0_DT;
> + writel(val, csid->base + CSID_RDI_CFG0(vc));
> +
> + val = RDI_CFG1_PACKING_FORMAT_MIPI;
> + writel(val, csid->base + CSID_RDI_CFG1(vc));
> +
> + /* Configure pixel store using dedicated register in 1080 */
> + if (!csid_is_lite(csid))
> + __csid_configure_rdi_pix_store(csid, vc);
> +
> + val = 0;
> + writel(val, csid->base + CSID_RDI_CTRL(vc));
> +
> + val = readl(csid->base + CSID_RDI_CFG0(vc));
> +
> + if (enable)
> + val |= RDI_CFG0_EN;
> +
> + writel(val, csid->base + CSID_RDI_CFG0(vc));
> +}
> +
> +static void csid_configure_stream_1080(struct csid_device *csid, u8 enable)
> +{
> + u8 i;
> + u8 vc;
> +
> + __csid_configure_rx(csid, &csid->phy);
> +
> + for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_1080; vc++) {
> + if (csid->phy.en_vc & BIT(vc)) {
> + __csid_configure_rdi_stream(csid, enable, vc);
> + __csid_configure_rx_vc(csid, &csid->phy, vc);
> +
> + for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++)
> + __csid_aup_update(csid, vc);
> +
> + __csid_reg_update(csid, vc);
> +
> + __csid_ctrl_rdi(csid, enable, vc);
> + }
> + }
> +}
> +
> +static int csid_configure_testgen_pattern_1080(struct csid_device *csid,
> + s32 val)
> +{
> + return 0;
> +}
> +
> +static void csid_subdev_reg_update_1080(struct csid_device *csid, int port_id,
> + bool clear)
> +{
> + /* No explicit clear required */
> + if (!clear)
> + __csid_aup_update(csid, port_id);
> +}
> +
> +/**
> + * csid_isr - CSID module interrupt service routine
> + * @irq: Interrupt line
> + * @dev: CSID device
> + *
> + * Return IRQ_HANDLED on success
> + */
> +static irqreturn_t csid_isr_1080(int irq, void *dev)
> +{
> + struct csid_device *csid = dev;
> + u32 val, buf_done_val;
> + u8 reset_done;
> + int i;
> +
> + val = readl(csid->base + CSID_TOP_IRQ_STATUS);
> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
> +
> + reset_done = val & INFO_RST_DONE;
> +
> + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
> + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
> +
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++)
> + if (csid->phy.en_vc & BIT(i)) {
> + val = readl(csid->base + CSID_RDIN_IRQ_STATUS(i));
> + writel(val, csid->base + CSID_RDIN_IRQ_CLEAR(i));
> +
> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) {
> + /*
> + * buf done and RUP IRQ have been moved to CSID from VFE.
> + * Once CSID received buf done, need notify VFE of this
> + * event and trigger VFE to handle buf done process.
> + */
> + camss_buf_done(csid->camss, csid->id, i);
> + }
> + }
> +
> + val = IRQ_CMD_CLEAR;
> + writel(val, csid->base + CSID_IRQ_CMD);
> +
> + if (reset_done)
> + complete(&csid->reset_complete);
> +
> + return IRQ_HANDLED;
> +}
> +
> +/**
> + * csid_reset - Trigger reset on CSID module and wait to complete
> + * @csid: CSID device
> + *
> + * Return 0 on success or a negative error code otherwise
> + */
> +static int csid_reset_1080(struct csid_device *csid)
> +{
> + unsigned long time;
> + u32 val;
> + int i;
> +
> + reinit_completion(&csid->reset_complete);
> +
> + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
> + writel(val, csid->base + CSID_TOP_IRQ_MASK);
> +
> + val = 0;
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) {
> + if (csid->phy.en_vc & BIT(i)) {
> + /* only need to clear Buffer Done IRQ Status here,
> + * RUP Done IRQ Status will be cleared once isr
> + * strobe generated by CSID_RST_CMD
> + */
I like this self-documenting code BTW, thanks for the commentary effort.
> + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
> + }
> + }
> + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
> + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
> +
> + /* Clear all IRQ status with CLEAR bits set */
> + val = IRQ_CMD_CLEAR;
> + writel(val, csid->base + CSID_IRQ_CMD);
> +
> + val = RST_LOCATION | RST_MODE;
> + writel(val, csid->base + CSID_RST_CFG);
> +
> + val = SELECT_HW_RST | SELECT_IRQ_RST;
> + writel(val, csid->base + CSID_RST_CMD);
> +
> + time = wait_for_completion_timeout(&csid->reset_complete,
> + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
> +
> + if (!time) {
> + dev_err(csid->camss->dev, "CSID reset timeout\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static void csid_subdev_init_1080(struct csid_device *csid)
> +{
> + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
> +}
> +
> +const struct csid_hw_ops csid_ops_1080 = {
> + .configure_stream = csid_configure_stream_1080,
> + .configure_testgen_pattern = csid_configure_testgen_pattern_1080,
> + .hw_version = csid_hw_version,
> + .isr = csid_isr_1080,
> + .reset = csid_reset_1080,
> + .src_pad_code = csid_src_pad_code,
> + .subdev_init = csid_subdev_init_1080,
> + .reg_update = csid_subdev_reg_update_1080,
> +};
Awaiting access to the register list for this part however, where is
__csid_configure_wrapper(struct csid_device *csid){}
Is this mux not required on your hardware ?
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.h b/drivers/media/platform/qcom/camss/camss-csid-1080.h
> new file mode 100644
> index 000000000000..f526f3168e33
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * camss-csid-1080.h
> + *
> + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module Generation 3
> + *
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +#ifndef __QC_MSM_CAMSS_CSID_1080_H__
> +#define __QC_MSM_CAMSS_CSID_1080_H__
> +
> +#define DECODE_FORMAT_UNCOMPRESSED_8_BIT 0x1
> +#define DECODE_FORMAT_UNCOMPRESSED_10_BIT 0x2
> +#define DECODE_FORMAT_UNCOMPRESSED_12_BIT 0x3
> +#define DECODE_FORMAT_UNCOMPRESSED_14_BIT 0x4
> +#define DECODE_FORMAT_UNCOMPRESSED_16_BIT 0x5
> +#define DECODE_FORMAT_UNCOMPRESSED_20_BIT 0x6
> +#define DECODE_FORMAT_UNCOMPRESSED_24_BIT 0x7
> +#define DECODE_FORMAT_PAYLOAD_ONLY 0xf
> +
> +#define PLAIN_FORMAT_PLAIN8 0x0 /* supports DPCM, UNCOMPRESSED_6/8_BIT */
> +#define PLAIN_FORMAT_PLAIN16 0x1 /* supports DPCM, UNCOMPRESSED_10/16_BIT */
> +#define PLAIN_FORMAT_PLAIN32 0x2 /* supports UNCOMPRESSED_20_BIT */
> +
> +#endif /* __QC_MSM_CAMSS_CSID_1080_H__ */
This header is a 1:1 drivers/media/platform/qcom/camss/camss-csid-gen3.h
of its completely redundant.
Please go through your submission and rationalise the copy/pasting.
---
bod
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 5/6] media: qcom: camss: csid: Add support for CSID 1080
2025-09-25 23:30 ` Bryan O'Donoghue
@ 2025-10-15 3:44 ` Hangxiang Ma
0 siblings, 0 replies; 27+ messages in thread
From: Hangxiang Ma @ 2025-10-15 3:44 UTC (permalink / raw)
To: Bryan O'Donoghue, Jingyi Wang, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, Atiya Kailany
On 9/26/2025 7:30 AM, Bryan O'Donoghue wrote:
> On 25/09/2025 01:02, Jingyi Wang wrote:
>> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>>
>> Add more detailed resource information for CSID devices along with the
>> driver for CSID 1080 that is responsible for CSID register
>> configuration, module reset and IRQ handling for BUF_DONE events.
>>
>> In this CSID version, RUP and AUP update values are split into two
>> registers along with a SET register. Accordingly , enhance the CSID
>> interface to accommodate both the legacy combined reg_update and the
>> split RUP and AUP updates.
>>
>> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/camss/Makefile | 1 +
>> .../media/platform/qcom/camss/camss-csid-1080.c | 379
>> +++++++++++++++++++++
>> .../media/platform/qcom/camss/camss-csid-1080.h | 25 ++
>> drivers/media/platform/qcom/camss/camss-csid.h | 9 +-
>> drivers/media/platform/qcom/camss/camss.c | 80 +++++
>> drivers/media/platform/qcom/camss/camss.h | 1 +
>> 6 files changed, 494 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/Makefile
>> b/drivers/media/platform/qcom/camss/Makefile
>> index 23960d02877d..3a7ed4f5a004 100644
>> --- a/drivers/media/platform/qcom/camss/Makefile
>> +++ b/drivers/media/platform/qcom/camss/Makefile
>> @@ -8,6 +8,7 @@ qcom-camss-objs += \
>> camss-csid-4-7.o \
>> camss-csid-340.o \
>> camss-csid-680.o \
>> + camss-csid-1080.o \
>> camss-csid-gen2.o \
>> camss-csid-gen3.o \
>> camss-csiphy-2ph-1-0.o \
>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c
>> b/drivers/media/platform/qcom/camss/camss-csid-1080.c
>> new file mode 100644
>> index 000000000000..ab5944d4ff34
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c
>> @@ -0,0 +1,379 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * camss-csid-1080.c
>> + *
>> + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
>> + *
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of.h>
>> +#include <linux/types.h>
>> +#include <linux/v4l2-controls.h>
>> +#include "camss.h"
>> +#include "camss-csid.h"
>> +#include "camss-csid-1080.h"
>> +
>> +/* Reset and Command Registers */
>> +#define CSID_RST_CFG 0x108
>> +#define RST_MODE BIT(0)
>> +#define RST_LOCATION BIT(4)
>> +
>> +/* Reset and Command Registers */
>> +#define CSID_RST_CMD 0x10C
>> +#define SELECT_HW_RST BIT(0)
>> +#define SELECT_IRQ_RST BIT(2)
>> +#define CSID_IRQ_CMD 0x110
>> +#define IRQ_CMD_CLEAR BIT(0)
>> +
>> +/* Register Update Commands, RUP/AUP */
>> +#define CSID_RUP_CMD 0x114
>> +#define RUP_RDIN BIT(8)
>> +#define CSID_AUP_CMD 0x118
>> +#define AUP_RDIN BIT(8)
>> +#define CSID_RUP_AUP_CMD 0x11C
>> +#define RUP_SET BIT(0)
>> +#define MUP BIT(4)
>> +
>> +/* Top level interrupt registers */
>> +#define CSID_TOP_IRQ_STATUS 0x180
>> +#define CSID_TOP_IRQ_MASK 0x184
>> +#define CSID_TOP_IRQ_CLEAR 0x188
>> +#define CSID_TOP_IRQ_SET 0x18C
>> +#define INFO_RST_DONE BIT(0)
>> +#define CSI2_RX_IRQ_STATUS BIT(2)
>> +#define BUF_DONE_IRQ_STATUS BIT(3)
>> +#define RDIn_IRQ_STATUS_OFFSET 16
>> +#define TOP_IRQ_STATUS_2 BIT(31)
>> +
>> +/* Buffer done interrupt registers */
>> +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0
>> +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16
>> +#define CSID_BUF_DONE_IRQ_MASK 0x1A4
>> +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8
>> +#define CSID_BUF_DONE_IRQ_SET 0x1AC
>> +
>> +/* CSI2 RX interrupt registers */
>> +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0
>> +#define CSID_CSI2_RX_IRQ_MASK 0x1B4
>> +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8
>> +#define CSID_CSI2_RX_IRQ_SET 0x1BC
>> +
>> +/* CSI2 RX Configuration */
>> +#define CSID_CSI2_RX_CFG0 0x880
>> +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
>> +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
>> +#define CSI2_RX_CFG0_PHY_NUM_SEL 20
>> +#define CSID_CSI2_RX_CFG1 0x884
>> +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
>> +#define CSI2_RX_CFG1_VC_MODE BIT(2)
>> +
>> +/* CSIPHY to hardware PHY selector mapping */
>> +#define CSID_CSIPHY_ID_BASE_OFFSET 1
>
> Please align to the existing namespace and now that I look at it, try
> to aggregate some of these defines into one place.
>
> Its a bit mindless repeating defines/code in silos within the same
> driver.
>
> e.g.
>
> grep -r -e CSID_CSIPHY_ID_BASE_OFFSET -e CSI2_RX_CFG0_PHY_SEL_BASE_IDX
> drivers/media/platform/qcom/camss/*
> drivers/media/platform/qcom/camss/camss-csid-1080.c:#define
> CSID_CSIPHY_ID_BASE_OFFSET 1
> drivers/media/platform/qcom/camss/camss-csid-1080.c: val |=
> (phy->csiphy_id + CSID_CSIPHY_ID_BASE_OFFSET)
> drivers/media/platform/qcom/camss/camss-csid-680.c:#define
> CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
> drivers/media/platform/qcom/camss/camss-csid-680.c: val |=
> (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) <<
> CSI2_RX_CFG0_PHY_NUM_SEL;
> drivers/media/platform/qcom/camss/camss-csid-gen3.c:#define
> CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
> drivers/media/platform/qcom/camss/camss-csid-gen3.c: val |=
> (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) <<
> CSI2_RX_CFG0_PHY_NUM_SEL;
>
> Expectation for v2 here is to review defines ensure the names are
> consistent with what's upstream and where possible moving common
> defines into one header.
> > +
Ack
>> +#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4
>> : 5)
>> +
>> +/* RDI Configuration */
>> +#define CSID_RDI_CFG0(rdi) \
>> + ((csid_is_lite(csid) ? 0x3080 : 0x5480) + 0x200 * (rdi))
>> +#define RDI_CFG0_RETIME_BS BIT(5)
>> +#define RDI_CFG0_TIMESTAMP_EN BIT(6)
>> +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
>> +#define RDI_CFG0_DECODE_FORMAT 12
>> +#define RDI_CFG0_DT 16
>> +#define RDI_CFG0_VC 22
>> +#define RDI_CFG0_EN BIT(31)
>> +
>> +/* RDI Control and Configuration */
>> +#define CSID_RDI_CTRL(rdi) \
>> + ((csid_is_lite(csid) ? 0x3088 : 0x5488) + 0x200 * (rdi))
>> +#define RDI_CTRL_START_CMD BIT(0)
>> +
>> +#define CSID_RDI_CFG1(rdi) \
>> + ((csid_is_lite(csid) ? 0x3094 : 0x5494) + 0x200 * (rdi))
>> +#define RDI_CFG1_DROP_H_EN BIT(5)
>> +#define RDI_CFG1_DROP_V_EN BIT(6)
>> +#define RDI_CFG1_CROP_H_EN BIT(7)
>> +#define RDI_CFG1_CROP_V_EN BIT(8)
>> +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
>> +
>> +/* RDI Pixel Store Configuration */
>> +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi))
>> +#define RDI_PIX_STORE_CFG0_EN BIT(0)
>> +#define RDI_PIX_STORE_CFG0_MIN_HBI 1
>> +
>> +/* RDI IRQ Status in wrapper */
>> +#define CSID_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi)))
>> +#define CSID_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi)))
>> +#define CSID_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi)))
>> +#define INFO_RUP_DONE BIT(23)
>> +
>> +static void __csid_aup_rup_trigger(struct csid_device *csid)
>> +{
>> + /* trigger SET in combined register */
>> + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
>> +}
>> +
>> +static void __csid_aup_update(struct csid_device *csid, int port_id)
>> +{
>> + csid->aup_update |= AUP_RDIN << port_id;
>> + writel(csid->aup_update, csid->base + CSID_AUP_CMD);
>> +
>> + __csid_aup_rup_trigger(csid);
>> +}
>> +
>> +static void __csid_reg_update(struct csid_device *csid, int port_id)
>> +{
>> + csid->rup_update |= RUP_RDIN << port_id;
>> + writel(csid->rup_update, csid->base + CSID_RUP_CMD);
>> +
>> + __csid_aup_rup_trigger(csid);
>> +}
>> +
>> +static void __csid_configure_rx(struct csid_device *csid,
>> + struct csid_phy_config *phy)
>> +{
>> + int val;
>> +
>> + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
>> + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
>> + val |= (phy->csiphy_id + CSID_CSIPHY_ID_BASE_OFFSET)
>> + << CSI2_RX_CFG0_PHY_NUM_SEL;
>> + writel(val, csid->base + CSID_CSI2_RX_CFG0);
>> +
>> + val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
>> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
>> +}
>> +
>> +static void __csid_configure_rx_vc(struct csid_device *csid,
>> + struct csid_phy_config *phy, int vc)
>> +{
>> + int val;
>> +
>> + if (vc > 3) {
>> + val = readl(csid->base + CSID_CSI2_RX_CFG1);
>> + val |= CSI2_RX_CFG1_VC_MODE;
>> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
>> + }
>> +}
>> +
>> +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8
>> rdi)
>> +{
>> + int val = 0;
>> +
>> + if (enable)
>> + val = RDI_CTRL_START_CMD;
>> +
>> + writel(val, csid->base + CSID_RDI_CTRL(rdi));
>> +}
>> +
>> +static void __csid_configure_rdi_pix_store(struct csid_device *csid,
>> u8 rdi)
>> +{
>> + u32 val;
>> +
>> + /* Configure pixel store to allow absorption of hblanking or
>> idle time.
>> + * This helps with horizontal crop and prevents line buffer
>> conflicts.
>> + * Reset state is 0x8 which has MIN_HBI=4, we keep the default
>> MIN_HBI
>> + * and just enable the pixel store functionality.
>> + */
>> + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
>> + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
>> +}
>> +
>> +static void __csid_configure_rdi_stream(struct csid_device *csid, u8
>> enable, u8 vc)
>> +{
>> + u32 val;
>> + u8 lane_cnt = csid->phy.lane_cnt;
>> +
>> + /* Source pads matching RDI channels on hardware.
>> + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
>> + */
>> + struct v4l2_mbus_framefmt *input_format =
>> &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
>> + const struct csid_format_info *format =
>> csid_get_fmt_entry(csid->res->formats->formats,
>> + csid->res->formats->nformats,
>> + input_format->code);
>> +
>> + if (!lane_cnt)
>> + lane_cnt = 4;
>> +
>> + val = RDI_CFG0_TIMESTAMP_EN;
>> + val |= RDI_CFG0_TIMESTAMP_STB_SEL;
>> + val |= RDI_CFG0_RETIME_BS;
>> +
>> + /* note: for non-RDI path, this should be format->decode_format */
>> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
>> + val |= vc << RDI_CFG0_VC;
>> + val |= format->data_type << RDI_CFG0_DT;
>> + writel(val, csid->base + CSID_RDI_CFG0(vc));
>> +
>> + val = RDI_CFG1_PACKING_FORMAT_MIPI;
>> + writel(val, csid->base + CSID_RDI_CFG1(vc));
>> +
>> + /* Configure pixel store using dedicated register in 1080 */
>> + if (!csid_is_lite(csid))
>> + __csid_configure_rdi_pix_store(csid, vc);
>> +
>> + val = 0;
>> + writel(val, csid->base + CSID_RDI_CTRL(vc));
>> +
>> + val = readl(csid->base + CSID_RDI_CFG0(vc));
>> +
>> + if (enable)
>> + val |= RDI_CFG0_EN;
>> +
>> + writel(val, csid->base + CSID_RDI_CFG0(vc));
>> +}
>> +
>> +static void csid_configure_stream_1080(struct csid_device *csid, u8
>> enable)
>> +{
>> + u8 i;
>> + u8 vc;
>> +
>> + __csid_configure_rx(csid, &csid->phy);
>> +
>> + for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_1080; vc++) {
>> + if (csid->phy.en_vc & BIT(vc)) {
>> + __csid_configure_rdi_stream(csid, enable, vc);
>> + __csid_configure_rx_vc(csid, &csid->phy, vc);
>> +
>> + for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++)
>> + __csid_aup_update(csid, vc);
>> +
>> + __csid_reg_update(csid, vc);
>> +
>> + __csid_ctrl_rdi(csid, enable, vc);
>> + }
>> + }
>> +}
>> +
>> +static int csid_configure_testgen_pattern_1080(struct csid_device
>> *csid,
>> + s32 val)
>> +{
>> + return 0;
>> +}
>> +
>> +static void csid_subdev_reg_update_1080(struct csid_device *csid,
>> int port_id,
>> + bool clear)
>> +{
>> + /* No explicit clear required */
>> + if (!clear)
>> + __csid_aup_update(csid, port_id);
>> +}
>> +
>> +/**
>> + * csid_isr - CSID module interrupt service routine
>> + * @irq: Interrupt line
>> + * @dev: CSID device
>> + *
>> + * Return IRQ_HANDLED on success
>> + */
>> +static irqreturn_t csid_isr_1080(int irq, void *dev)
>> +{
>> + struct csid_device *csid = dev;
>> + u32 val, buf_done_val;
>> + u8 reset_done;
>> + int i;
>> +
>> + val = readl(csid->base + CSID_TOP_IRQ_STATUS);
>> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
>> +
>> + reset_done = val & INFO_RST_DONE;
>> +
>> + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
>> + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
>> +
>> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++)
>> + if (csid->phy.en_vc & BIT(i)) {
>> + val = readl(csid->base + CSID_RDIN_IRQ_STATUS(i));
>> + writel(val, csid->base + CSID_RDIN_IRQ_CLEAR(i));
>> +
>> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET +
>> i)) {
>> + /*
>> + * buf done and RUP IRQ have been moved to CSID from
>> VFE.
>> + * Once CSID received buf done, need notify VFE of this
>> + * event and trigger VFE to handle buf done process.
>> + */
>> + camss_buf_done(csid->camss, csid->id, i);
>> + }
>> + }
>> +
>> + val = IRQ_CMD_CLEAR;
>> + writel(val, csid->base + CSID_IRQ_CMD);
>> +
>> + if (reset_done)
>> + complete(&csid->reset_complete);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +/**
>> + * csid_reset - Trigger reset on CSID module and wait to complete
>> + * @csid: CSID device
>> + *
>> + * Return 0 on success or a negative error code otherwise
>> + */
>> +static int csid_reset_1080(struct csid_device *csid)
>> +{
>> + unsigned long time;
>> + u32 val;
>> + int i;
>> +
>> + reinit_completion(&csid->reset_complete);
>> +
>> + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
>> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
>> + writel(val, csid->base + CSID_TOP_IRQ_MASK);
>> +
>> + val = 0;
>> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) {
>> + if (csid->phy.en_vc & BIT(i)) {
>> + /* only need to clear Buffer Done IRQ Status here,
>> + * RUP Done IRQ Status will be cleared once isr
>> + * strobe generated by CSID_RST_CMD
>> + */
>
> I like this self-documenting code BTW, thanks for the commentary effort.
Thanks. Will keep it.
>> + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
>> + }
>> + }
>> + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
>> + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
>> +
>> + /* Clear all IRQ status with CLEAR bits set */
>> + val = IRQ_CMD_CLEAR;
>> + writel(val, csid->base + CSID_IRQ_CMD);
>> +
>> + val = RST_LOCATION | RST_MODE;
>> + writel(val, csid->base + CSID_RST_CFG);
>> +
>> + val = SELECT_HW_RST | SELECT_IRQ_RST;
>> + writel(val, csid->base + CSID_RST_CMD);
>> +
>> + time = wait_for_completion_timeout(&csid->reset_complete,
>> + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
>> +
>> + if (!time) {
>> + dev_err(csid->camss->dev, "CSID reset timeout\n");
>> + return -EIO;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void csid_subdev_init_1080(struct csid_device *csid)
>> +{
>> + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
>> +}
>> +
>> +const struct csid_hw_ops csid_ops_1080 = {
>> + .configure_stream = csid_configure_stream_1080,
>> + .configure_testgen_pattern = csid_configure_testgen_pattern_1080,
>> + .hw_version = csid_hw_version,
>> + .isr = csid_isr_1080,
>> + .reset = csid_reset_1080,
>> + .src_pad_code = csid_src_pad_code,
>> + .subdev_init = csid_subdev_init_1080,
>> + .reg_update = csid_subdev_reg_update_1080,
>> +};
>
> Awaiting access to the register list for this part however, where is
>
> __csid_configure_wrapper(struct csid_device *csid){}
>
> Is this mux not required on your hardware ?
This is not required for Apollo architecture and that there is no
CSID_SWAPPER_TOP register space.
>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.h
>> b/drivers/media/platform/qcom/camss/camss-csid-1080.h
>> new file mode 100644
>> index 000000000000..f526f3168e33
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * camss-csid-1080.h
>> + *
>> + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
>> Generation 3
>> + *
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +#ifndef __QC_MSM_CAMSS_CSID_1080_H__
>> +#define __QC_MSM_CAMSS_CSID_1080_H__
>> +
>> +#define DECODE_FORMAT_UNCOMPRESSED_8_BIT 0x1
>> +#define DECODE_FORMAT_UNCOMPRESSED_10_BIT 0x2
>> +#define DECODE_FORMAT_UNCOMPRESSED_12_BIT 0x3
>> +#define DECODE_FORMAT_UNCOMPRESSED_14_BIT 0x4
>> +#define DECODE_FORMAT_UNCOMPRESSED_16_BIT 0x5
>> +#define DECODE_FORMAT_UNCOMPRESSED_20_BIT 0x6
>> +#define DECODE_FORMAT_UNCOMPRESSED_24_BIT 0x7
>> +#define DECODE_FORMAT_PAYLOAD_ONLY 0xf
>> +
>> +#define PLAIN_FORMAT_PLAIN8 0x0 /* supports DPCM,
>> UNCOMPRESSED_6/8_BIT */
>> +#define PLAIN_FORMAT_PLAIN16 0x1 /* supports DPCM,
>> UNCOMPRESSED_10/16_BIT */
>> +#define PLAIN_FORMAT_PLAIN32 0x2 /* supports UNCOMPRESSED_20_BIT */
>> +
>> +#endif /* __QC_MSM_CAMSS_CSID_1080_H__ */
>
> This header is a 1:1
> drivers/media/platform/qcom/camss/camss-csid-gen3.h of its completely
> redundant.
>
> Please go through your submission and rationalise the copy/pasting.
Ack
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 6/6] media: qcom: camss: vfe: Add support for VFE 1080
2025-09-25 0:02 [PATCH 0/6] media: qcom: camss: Add Kaanapali support Jingyi Wang
` (4 preceding siblings ...)
2025-09-25 0:02 ` [PATCH 5/6] media: qcom: camss: csid: Add support for CSID 1080 Jingyi Wang
@ 2025-09-25 0:02 ` Jingyi Wang
2025-09-25 22:59 ` Bryan O'Donoghue
2025-09-25 22:48 ` [PATCH 0/6] media: qcom: camss: Add Kaanapali support Bryan O'Donoghue
6 siblings, 1 reply; 27+ messages in thread
From: Jingyi Wang @ 2025-09-25 0:02 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
Jingyi Wang, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
Atiya Kailany
From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Add more detailed resource information for VFE and VFE Lite devices
along with a driver for the 1080 version of those that is responsible
for bus write master configuration and buffer address update.
The FULL front end modules in Kaanapali camera subsystem are called TFEs
(Thin Front End), however, retaining the name VFE at places to maintain
consistency and avoid unnecessary code changes.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-vfe-1080.c | 156 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 15 +-
drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 138 ++++++++++++++++++
5 files changed, 307 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 3a7ed4f5a004..dc41b0d6dc21 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -22,6 +22,7 @@ qcom-camss-objs += \
camss-vfe-340.o \
camss-vfe-480.o \
camss-vfe-680.o \
+ camss-vfe-1080.o \
camss-vfe-gen3.o \
camss-vfe-gen1.o \
camss-vfe.o \
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
new file mode 100644
index 000000000000..f1852a3bf97f
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-vfe-1080.c
+ *
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include "camss.h"
+#include "camss-vfe.h"
+
+/* VFE-1080 Bus Register Base Addresses */
+#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+
+#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
+#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
+
+#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
+
+#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
+#define WM_CFG_EN BIT(0)
+#define WM_VIR_FRM_EN BIT(1)
+#define WM_CFG_MODE BIT(16)
+#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
+#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
+#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50c + (n) * 0x100)
+#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
+#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
+#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
+#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
+
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
+#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
+
+/* VFE lite has no such registers */
+#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
+#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53c + (n) * 0x100)
+
+#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
+#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
+
+/*
+ * Bus client mapping:
+ *
+ * Full VFE:
+ * 23 = RDI0, 24 = RDI1, 25 = RDI2, 26 = RDI3, 27 = RDI4
+ *
+ * VFE LITE:
+ * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3
+ */
+#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
+
+static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
+{
+ struct v4l2_pix_format_mplane *pix =
+ &line->video_out.active_fmt.fmt.pix_mp;
+
+ wm = RDI_WM(wm);
+
+ /* no clock gating at bus input */
+ writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
+
+ writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
+
+ writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
+ vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
+ writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
+ writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
+ vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
+ writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
+
+ /* no dropped frames, one irq per frame */
+ if (!vfe_is_lite(vfe)) {
+ writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
+ }
+
+ writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
+ writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
+
+ writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
+ writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
+
+ writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
+{
+ wm = RDI_WM(wm);
+ writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
+}
+
+static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
+ struct vfe_line *line)
+{
+ wm = RDI_WM(wm);
+ writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
+
+ dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
+}
+
+static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ int port_id = line_id;
+
+ camss_reg_update(vfe->camss, vfe->id, port_id, false);
+}
+
+static const struct camss_video_ops vfe_video_ops_1080 = {
+ .queue_buffer = vfe_queue_buffer_v2,
+ .flush_buffers = vfe_flush_buffers,
+};
+
+static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vfe)
+{
+ vfe->video_ops = vfe_video_ops_1080;
+}
+
+static void vfe_global_reset_1080(struct vfe_device *vfe)
+{
+ vfe_isr_reset_ack(vfe);
+}
+
+static irqreturn_t vfe_isr_1080(int irq, void *dev)
+{
+ /* nop */
+ return IRQ_HANDLED;
+}
+
+static int vfe_halt_1080(struct vfe_device *vfe)
+{
+ /* rely on vfe_disable_output() to stop the VFE */
+ return 0;
+}
+
+const struct vfe_hw_ops vfe_ops_1080 = {
+ .global_reset = vfe_global_reset_1080,
+ .hw_version = vfe_hw_version,
+ .isr = vfe_isr_1080,
+ .pm_domain_off = vfe_pm_domain_off,
+ .pm_domain_on = vfe_pm_domain_on,
+ .reg_update = vfe_reg_update_1080,
+ .subdev_init = vfe_subdev_init_1080,
+ .vfe_disable = vfe_disable,
+ .vfe_enable = vfe_enable_v2,
+ .vfe_halt = vfe_halt_1080,
+ .vfe_wm_start = vfe_wm_start_1080,
+ .vfe_wm_stop = vfe_wm_stop_1080,
+ .vfe_buf_done = vfe_buf_done,
+ .vfe_wm_update = vfe_wm_update_1080,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index ee08dbbddf88..90e7fbd2428b 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8775P:
+ case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
@@ -521,7 +522,8 @@ int vfe_enable_output_v2(struct vfe_line *line)
spin_lock_irqsave(&vfe->output_lock, flags);
- ops->reg_update_clear(vfe, line->id);
+ if (ops->reg_update_clear)
+ ops->reg_update_clear(vfe, line->id);
if (output->state > VFE_OUTPUT_RESERVED) {
dev_err(vfe->camss->dev,
@@ -541,14 +543,17 @@ int vfe_enable_output_v2(struct vfe_line *line)
ops->vfe_wm_start(vfe, output->wm_idx[0], line);
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) {
output->buf[i] = vfe_buf_get_pending(output);
if (!output->buf[i])
break;
output->gen2.active_num++;
ops->vfe_wm_update(vfe, output->wm_idx[0],
output->buf[i]->addr[0], line);
- ops->reg_update(vfe, line->id);
+
+ /* Deferring the reg update until after CSID config */
+ if (vfe->camss->res->version != CAMSS_KAANAPALI)
+ ops->reg_update(vfe, line->id);
}
spin_unlock_irqrestore(&vfe->output_lock, flags);
@@ -914,7 +919,8 @@ static int vfe_match_clock_names(struct vfe_device *vfe,
return (!strcmp(clock->name, vfe_name) ||
!strcmp(clock->name, vfe_lite_name) ||
!strcmp(clock->name, "vfe_lite") ||
- !strcmp(clock->name, "camnoc_axi"));
+ !strcmp(clock->name, "camnoc_axi") ||
+ !strcmp(clock->name, "camnoc_rt_axi"));
}
/*
@@ -1997,6 +2003,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8775P:
+ case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
ret = 16;
break;
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index 0300efdb1c46..444924ddf724 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -245,6 +245,7 @@ extern const struct vfe_hw_ops vfe_ops_170;
extern const struct vfe_hw_ops vfe_ops_340;
extern const struct vfe_hw_ops vfe_ops_480;
extern const struct vfe_hw_ops vfe_ops_680;
+extern const struct vfe_hw_ops vfe_ops_1080;
extern const struct vfe_hw_ops vfe_ops_gen3;
int vfe_get(struct vfe_device *vfe);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 74a8ad3cb728..2239abfef26e 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -217,6 +217,142 @@ static const struct camss_subdev_resources csid_res_kaanapali[] = {
}
};
+/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks
+ * to operate on any TFE Full.
+ */
+static const struct camss_subdev_resources vfe_res_kaanapali[] = {
+ /* VFE0 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "tfe0",
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "tfe1",
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = true,
+ .pd_name = "tfe2",
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 - IFE Lite */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
+ "camnoc_rt_vfe_lite", "camnoc_rt_axi",
+ "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 - IFE Lite */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
+ "camnoc_rt_vfe_lite", "camnoc_rt_axi",
+ "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_1080,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
static const struct resources_icc icc_res_kaanapali[] = {
/* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
{
@@ -4493,10 +4629,12 @@ static const struct camss_resources kaanapali_resources = {
.pd_name = "top",
.csiphy_res = csiphy_res_kaanapali,
.csid_res = csid_res_kaanapali,
+ .vfe_res = vfe_res_kaanapali,
.icc_res = icc_res_kaanapali,
.icc_path_num = ARRAY_SIZE(icc_res_kaanapali),
.csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali),
.csid_num = ARRAY_SIZE(csid_res_kaanapali),
+ .vfe_num = ARRAY_SIZE(vfe_res_kaanapali),
};
static const struct camss_resources msm8916_resources = {
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 6/6] media: qcom: camss: vfe: Add support for VFE 1080
2025-09-25 0:02 ` [PATCH 6/6] media: qcom: camss: vfe: Add support for VFE 1080 Jingyi Wang
@ 2025-09-25 22:59 ` Bryan O'Donoghue
0 siblings, 0 replies; 27+ messages in thread
From: Bryan O'Donoghue @ 2025-09-25 22:59 UTC (permalink / raw)
To: Jingyi Wang, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Hangxiang Ma,
Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, Atiya Kailany
On 25/09/2025 01:02, Jingyi Wang wrote:
> From: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>
> Add more detailed resource information for VFE and VFE Lite devices
> along with a driver for the 1080 version of those that is responsible
> for bus write master configuration and buffer address update.
"Add Video Front End (VFE) version 1080 as found on the Kaanapali SoC"
> The FULL front end modules in Kaanapali camera subsystem are called TFEs
> (Thin Front End), however, retaining the name VFE at places to maintain
> consistency and avoid unnecessary code changes.
Good
>
> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 1 +
> drivers/media/platform/qcom/camss/camss-vfe-1080.c | 156 +++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss-vfe.c | 15 +-
> drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
> drivers/media/platform/qcom/camss/camss.c | 138 ++++++++++++++++++
> 5 files changed, 307 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index 3a7ed4f5a004..dc41b0d6dc21 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -22,6 +22,7 @@ qcom-camss-objs += \
> camss-vfe-340.o \
> camss-vfe-480.o \
> camss-vfe-680.o \
> + camss-vfe-1080.o \
> camss-vfe-gen3.o \
> camss-vfe-gen1.o \
> camss-vfe.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
> new file mode 100644
> index 000000000000..f1852a3bf97f
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-1080.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * camss-vfe-1080.c
> + *
> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
> + *
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +
> +#include "camss.h"
> +#include "camss-vfe.h"
> +
> +/* VFE-1080 Bus Register Base Addresses */
> +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
> +
> +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
> +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
> +
> +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128)
> +
> +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100)
> +#define WM_CFG_EN BIT(0)
> +#define WM_VIR_FRM_EN BIT(1)
> +#define WM_CFG_MODE BIT(16)
> +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100)
> +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100)
> +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50c + (n) * 0x100)
> +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
> +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100)
> +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
> +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100)
> +
> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0x100)
> +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * 0x100)
> +
> +/* VFE lite has no such registers */
> +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x100)
> +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53c + (n) * 0x100)
> +
> +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x100)
> +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) * 0x100)
> +
> +/*
> + * Bus client mapping:
> + *
> + * Full VFE:
> + * 23 = RDI0, 24 = RDI1, 25 = RDI2, 26 = RDI3, 27 = RDI4
> + *
> + * VFE LITE:
> + * 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3
> + */
Give the full bus client mapping, no the partial.
> +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
> +
> +static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
> +{
> + struct v4l2_pix_format_mplane *pix =
> + &line->video_out.active_fmt.fmt.pix_mp;
> +
> + wm = RDI_WM(wm);
> +
> + /* no clock gating at bus input */
> + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
> +
> + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
> +
> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
> + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
> + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
> + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
> + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
> + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
> +
> + /* no dropped frames, one irq per frame */
> + if (!vfe_is_lite(vfe)) {
> + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
> + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
> + }
> +
> + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
> + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
> +
> + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
> + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
> +
> + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
> +}
> +
> +static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
> +{
> + wm = RDI_WM(wm);
> + writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
> +}
> +
> +static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
> + struct vfe_line *line)
> +{
> + wm = RDI_WM(wm);
> + writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
> +
> + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
> +}
> +
> +static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id line_id)
> +{
> + int port_id = line_id;
> +
> + camss_reg_update(vfe->camss, vfe->id, port_id, false);
> +}
> +
> +static const struct camss_video_ops vfe_video_ops_1080 = {
> + .queue_buffer = vfe_queue_buffer_v2,
> + .flush_buffers = vfe_flush_buffers,
> +};
> +
> +static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vfe)
> +{
> + vfe->video_ops = vfe_video_ops_1080;
> +}
> +
> +static void vfe_global_reset_1080(struct vfe_device *vfe)
> +{
> + vfe_isr_reset_ack(vfe);
> +}
> +
> +static irqreturn_t vfe_isr_1080(int irq, void *dev)
> +{
> + /* nop */
> + return IRQ_HANDLED;
> +}
> +
> +static int vfe_halt_1080(struct vfe_device *vfe)
> +{
> + /* rely on vfe_disable_output() to stop the VFE */
> + return 0;
> +}
> +
> +const struct vfe_hw_ops vfe_ops_1080 = {
> + .global_reset = vfe_global_reset_1080,
> + .hw_version = vfe_hw_version,
> + .isr = vfe_isr_1080,
> + .pm_domain_off = vfe_pm_domain_off,
> + .pm_domain_on = vfe_pm_domain_on,
> + .reg_update = vfe_reg_update_1080,
> + .subdev_init = vfe_subdev_init_1080,
> + .vfe_disable = vfe_disable,
> + .vfe_enable = vfe_enable_v2,
> + .vfe_halt = vfe_halt_1080,
> + .vfe_wm_start = vfe_wm_start_1080,
> + .vfe_wm_stop = vfe_wm_stop_1080,
> + .vfe_buf_done = vfe_buf_done,
> + .vfe_wm_update = vfe_wm_update_1080,
> +};
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index ee08dbbddf88..90e7fbd2428b 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -349,6 +349,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8775P:
> + case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> switch (sink_code) {
> case MEDIA_BUS_FMT_YUYV8_1X16:
> @@ -521,7 +522,8 @@ int vfe_enable_output_v2(struct vfe_line *line)
>
> spin_lock_irqsave(&vfe->output_lock, flags);
>
> - ops->reg_update_clear(vfe, line->id);
> + if (ops->reg_update_clear)
> + ops->reg_update_clear(vfe, line->id);
What's going on here, why don't you have to clear the reg_update for
your hardware ?
>
> if (output->state > VFE_OUTPUT_RESERVED) {
> dev_err(vfe->camss->dev,
> @@ -541,14 +543,17 @@ int vfe_enable_output_v2(struct vfe_line *line)
>
> ops->vfe_wm_start(vfe, output->wm_idx[0], line);
>
> - for (i = 0; i < 2; i++) {
> + for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) {
This I like but it's not specific to VFE 1080.
It can/should be introduced as its own patch to remove this hard-coded
value.
> output->buf[i] = vfe_buf_get_pending(output);
> if (!output->buf[i])
> break;
> output->gen2.active_num++;
> ops->vfe_wm_update(vfe, output->wm_idx[0],
> output->buf[i]->addr[0], line);
> - ops->reg_update(vfe, line->id);
> +
> + /* Deferring the reg update until after CSID config */
> + if (vfe->camss->res->version != CAMSS_KAANAPALI)
> + ops->reg_update(vfe, line->id);
Needs more justification - here in the email thread will do.
OK you don't have to do reg_update but, your logic is not consistent for
this.
In one case you check for ops->reg_update_clear() in this case you check
for !KANNAPALI
Definitely don't want to have SoC specific logic in the core files
unless absolutely necessary, which in this case it is not.
> }
>
> spin_unlock_irqrestore(&vfe->output_lock, flags);
> @@ -914,7 +919,8 @@ static int vfe_match_clock_names(struct vfe_device *vfe,
> return (!strcmp(clock->name, vfe_name) ||
> !strcmp(clock->name, vfe_lite_name) ||
> !strcmp(clock->name, "vfe_lite") ||
> - !strcmp(clock->name, "camnoc_axi"));
> + !strcmp(clock->name, "camnoc_axi") ||
> + !strcmp(clock->name, "camnoc_rt_axi"));
I'd prefer to see a small patch adding camnoc_rt_axi and explaining what
it is inside of CAMSS and why we should clock it.
> }
>
> /*
> @@ -1997,6 +2003,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8775P:
> + case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> ret = 16;
> break;
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
> index 0300efdb1c46..444924ddf724 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.h
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h
> @@ -245,6 +245,7 @@ extern const struct vfe_hw_ops vfe_ops_170;
> extern const struct vfe_hw_ops vfe_ops_340;
> extern const struct vfe_hw_ops vfe_ops_480;
> extern const struct vfe_hw_ops vfe_ops_680;
> +extern const struct vfe_hw_ops vfe_ops_1080;
> extern const struct vfe_hw_ops vfe_ops_gen3;
>
> int vfe_get(struct vfe_device *vfe);
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 74a8ad3cb728..2239abfef26e 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -217,6 +217,142 @@ static const struct camss_subdev_resources csid_res_kaanapali[] = {
> }
> };
>
> +/* In Kaanapali, CAMNOC requires all CAMNOC_RT_TFEX clocks
> + * to operate on any TFE Full.
> + */
> +static const struct camss_subdev_resources vfe_res_kaanapali[] = {
> + /* VFE0 - TFE Full */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
XO debug ?
Really ? Why ?
Whats that clock for and why is it needed for the runtime TFE to function ?
---
bod
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 0/6] media: qcom: camss: Add Kaanapali support
2025-09-25 0:02 [PATCH 0/6] media: qcom: camss: Add Kaanapali support Jingyi Wang
` (5 preceding siblings ...)
2025-09-25 0:02 ` [PATCH 6/6] media: qcom: camss: vfe: Add support for VFE 1080 Jingyi Wang
@ 2025-09-25 22:48 ` Bryan O'Donoghue
2025-10-15 3:17 ` Hangxiang Ma
6 siblings, 1 reply; 27+ messages in thread
From: Bryan O'Donoghue @ 2025-09-25 22:48 UTC (permalink / raw)
To: Jingyi Wang, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab,
Hangxiang Ma
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, Atiya Kailany
On 25/09/2025 01:02, Jingyi Wang wrote:
> Add support for the RDI only CAMSS camera driver on Kaanapali. Enabling
> RDI path involves adding the support for a set of CSIPHY, CSID and TFE
> modules, with each TFE having multiple RDI ports.
>
> Kaanapali camera sub system provides
>
> - 3 x VFE, 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE Lite
> - 3 x CSID
> - 2 x CSID Lite
> - 6 x CSI PHY
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
How has this series been tested ?
---
bod
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 0/6] media: qcom: camss: Add Kaanapali support
2025-09-25 22:48 ` [PATCH 0/6] media: qcom: camss: Add Kaanapali support Bryan O'Donoghue
@ 2025-10-15 3:17 ` Hangxiang Ma
0 siblings, 0 replies; 27+ messages in thread
From: Hangxiang Ma @ 2025-10-15 3:17 UTC (permalink / raw)
To: Bryan O'Donoghue, Jingyi Wang, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bryan O'Donoghue, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang, Atiya Kailany
On 9/26/2025 6:48 AM, Bryan O'Donoghue wrote:
> On 25/09/2025 01:02, Jingyi Wang wrote:
>> Add support for the RDI only CAMSS camera driver on Kaanapali. Enabling
>> RDI path involves adding the support for a set of CSIPHY, CSID and TFE
>> modules, with each TFE having multiple RDI ports.
>>
>> Kaanapali camera sub system provides
>>
>> - 3 x VFE, 5 RDI per VFE
>> - 2 x VFE Lite, 4 RDI per VFE Lite
>> - 3 x CSID
>> - 2 x CSID Lite
>> - 6 x CSI PHY
>>
>> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> How has this series been tested ?
>
> ---
> bod
Will update in next revision
^ permalink raw reply [flat|nested] 27+ messages in thread