[PATCH v4 0/6] Add support for LS7A LPC IRQ for MIPS Loongson systems

[PATCH v4 0/6] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Icenowy Zheng]

From: Icenowy Zheng <uwu@icenowy.me>

This patchset tries to add support for Loongson 7A1000 PCH's LPC
interrupt controller to MIPS-based Loongson systems.

LPC, from software's perspective of view, is just ISA, so the interrupts
should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
machines handled it, the setup is fragile and depends on its specific
setup sequence (allocating the LPC IRQs first, and then allocate the
parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
breaks this fragile sequence, so the first two commits is created to
address this issue (by reserving ISA interrupts from the dynamic
allocation space).

Then the remaining commits are just adding OF(DT) based initialization
of PCH LPC interrupt controller, like what happened on PCH PIC.

Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
integrated ones, with some additional patches adding the PCH LPC device
node to the ls7a-pch.dtsi file.

Changes in v4:
- Removed "IRQ" acronym from detailed commit messages (but still kept
  in summary phrases for the length constraint).
- Re-format some patch to utilize 100 columns instead of 80.
- Temporarily removed the DT patches for fitting the whole patchset into
  the irqchip tree.

Changes in v3:
- Override arch_dynirq_lower_bound() in MIPS Loongson64 / LoongArch
  instead of modifying the global version of function.
- Added Rob's R-b to the binding patch.

Changes in v2:
- Rebased on top of `irq-drivers-2026-02-09` tag.
- Compatible changed to `loongson,ls7a-lpc` .
- Merged the patch for conditionally build of ACPI code to the patch
  introducing OF code.
- Sorted function variable definitions.
- Reworded some commit messages as Thomas Glexiner suggests.
- Added __init to the LPC irqchip OF initialization code to prevent
  section mismatch.

Icenowy Zheng (6):
  MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs
  LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs
  dt-bindings: interrupt-controller: add LS7A PCH LPC
  irqchip/loongson-pch-lpc: Extract non-ACPI-related code from ACPI init
  irqchip/loongson-pch-lpc: Add OF init code
  irqchip/loongson-pch-lpc: Enable building on MIPS Loongson64

 .../loongson,pch-lpc.yaml                     | 52 +++++++++++
 arch/loongarch/kernel/irq.c                   |  6 ++
 arch/mips/loongson64/init.c                   |  6 ++
 drivers/irqchip/Kconfig                       |  1 -
 drivers/irqchip/irq-loongson-pch-lpc.c        | 92 +++++++++++++++----
 5 files changed, 136 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

-- 
2.52.0

[PATCH v4 1/6] MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs

[Icenowy Zheng]

On some Loongson 3A devices, a LPC bus is present and some legacy
devices (e.g. 8259) on it expect hardcoded low interrupt numbers. However
currently the expected low range interrupt numbers are not exempted from
the dynamic allocation, which leads to confliction when registering LPC
interrupts in the fixed range.

Override arch_dynirq_lower_bound() to reserve these low range interrupt
numbers and prevent them from being dynamically allocated.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/mips/loongson64/init.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index 5f73f8663ab2d..c7cc5a3d7817f 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -7,6 +7,7 @@
 #include <linux/irqchip.h>
 #include <linux/logic_pio.h>
 #include <linux/memblock.h>
+#include <linux/minmax.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <asm/bootinfo.h>
@@ -227,3 +228,8 @@ void __init arch_init_irq(void)
 	reserve_pio_range();
 	irqchip_init();
 }
+
+unsigned int arch_dynirq_lower_bound(unsigned int from)
+{
+	return MAX(from, NR_IRQS_LEGACY);
+}
-- 
2.52.0

[PATCH v4 2/6] LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs

[Icenowy Zheng]

Loongson 7A PCH chips all contain a LPC controller, which is used in
some devices to connect legacy ISA devices (e.g. 8259 PS/2 controller).

The LPC irqchip driver will register LPC interrupts at the fixed range
0~15, and the PCH PIC irqchip driver uses dynamic allocation. However the
LPC interrupt numbers are currently not exempted from dynamic allocation.

The currently setup work by accident because the LPC interrupt controller
is the first consumer of PIC interrupt controller, and the PIC interrupt
number is allocated after LPC interrupts are registered. Such setup is
fragile and will stop to work when the LPC irqchip driver is reworked.

Override arch_dynirq_lower_bound() to reserve LPC interrupts from dynamic
allocation, to prevent interrupt number collision and allow rework of the
LPC irqchip driver.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 arch/loongarch/kernel/irq.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 80946cafaec1b..7bf68a7a5f4b3 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -11,6 +11,7 @@
 #include <linux/irqchip.h>
 #include <linux/kernel_stat.h>
 #include <linux/proc_fs.h>
+#include <linux/minmax.h>
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/seq_file.h>
@@ -99,6 +100,11 @@ int __init arch_probe_nr_irqs(void)
 	return NR_IRQS_LEGACY;
 }
 
+unsigned int arch_dynirq_lower_bound(unsigned int from)
+{
+	return MAX(from, NR_IRQS_LEGACY);
+}
+
 void __init init_IRQ(void)
 {
 	int i;
-- 
2.52.0

[PATCH v4 3/6] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Icenowy Zheng]

Loongson 7A series PCH contains an LPC controller with an interrupt
controller.

Add the device tree binding for the interrupt controller.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 .../loongson,pch-lpc.yaml                     | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
new file mode 100644
index 0000000000000..ff2a425b6f0b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCH LPC Controller
+
+maintainers:
+  - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description:
+  This interrupt controller is found in the Loongson LS7A family of PCH for
+  accepting interrupts sent by LPC-connected peripherals and signalling PIC
+  via a single interrupt line when interrupts are available.
+
+properties:
+  compatible:
+    const: loongson,ls7a-lpc
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  '#interrupt-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - interrupts
+  - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    lpc: interrupt-controller@10002000 {
+      compatible = "loongson,ls7a-lpc";
+      reg = <0x10002000 0x400>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      interrupt-parent = <&pic>;
+      interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...
-- 
2.52.0

[PATCH v4 4/6] irqchip/loongson-pch-lpc: Extract non-ACPI-related code from ACPI init

[Icenowy Zheng]

A lot of code can be shared between the existing ACPI init flow with the
upcoming OF init flow.

Extract it into a dedicated function.

The re-ordering of parent interrupt acquisition requires the
architecture code to reserve legacy interrupts from the dynamic
allocation by overriding arch_dynirq_lower_bound(), otherwise the parent
of LPC irqchip will be allocated to the intended static range of LPC
interrupts, which leads to allocation failure of LPC interrupts.

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/irq-loongson-pch-lpc.c | 57 +++++++++++++++++---------
 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
index 3ad46ec94e3c0..2bb6659e9a93c 100644
--- a/drivers/irqchip/irq-loongson-pch-lpc.c
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -175,13 +175,10 @@ static struct syscore pch_lpc_syscore = {
 	.ops = &pch_lpc_syscore_ops,
 };
 
-int __init pch_lpc_acpi_init(struct irq_domain *parent,
-					struct acpi_madt_lpc_pic *acpi_pchlpc)
+static int __init pch_lpc_init(phys_addr_t addr, unsigned long size,
+			       struct fwnode_handle *irq_handle, int parent_irq)
 {
-	int parent_irq;
 	struct pch_lpc *priv;
-	struct irq_fwspec fwspec;
-	struct fwnode_handle *irq_handle;
 
 	priv = kzalloc_obj(*priv);
 	if (!priv)
@@ -189,7 +186,7 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	raw_spin_lock_init(&priv->lpc_lock);
 
-	priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
+	priv->base = ioremap(addr, size);
 	if (!priv->base)
 		goto free_priv;
 
@@ -198,12 +195,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 		goto iounmap_base;
 	}
 
-	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
-	if (!irq_handle) {
-		pr_err("Unable to allocate domain handle\n");
-		goto iounmap_base;
-	}
-
 	/*
 	 * The LPC interrupt controller is a legacy i8259-compatible device,
 	 * which requires a static 1:1 mapping for IRQs 0-15.
@@ -213,15 +204,10 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 						    &pch_lpc_domain_ops, priv);
 	if (!priv->lpc_domain) {
 		pr_err("Failed to create IRQ domain\n");
-		goto free_irq_handle;
+		goto iounmap_base;
 	}
 	pch_lpc_reset(priv);
 
-	fwspec.fwnode = parent->fwnode;
-	fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
-	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
-	fwspec.param_count = 2;
-	parent_irq = irq_create_fwspec_mapping(&fwspec);
 	irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
 
 	pch_lpc_priv = priv;
@@ -230,8 +216,6 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	return 0;
 
-free_irq_handle:
-	irq_domain_free_fwnode(irq_handle);
 iounmap_base:
 	iounmap(priv->base);
 free_priv:
@@ -239,3 +223,36 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent,
 
 	return -ENOMEM;
 }
+
+int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc)
+{
+	struct fwnode_handle *irq_handle;
+	struct irq_fwspec fwspec;
+	int parent_irq, ret;
+
+	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
+	if (!irq_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		return -ENOMEM;
+	}
+
+	fwspec.fwnode = parent->fwnode;
+	fwspec.param[0] = acpi_pchlpc->cascade + GSI_MIN_PCH_IRQ;
+	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+	fwspec.param_count = 2;
+	parent_irq = irq_create_fwspec_mapping(&fwspec);
+	if (parent_irq <= 0) {
+		pr_err("Unable to map LPC parent interrupt\n");
+		irq_domain_free_fwnode(irq_handle);
+		return -ENOMEM;
+	}
+
+	ret = pch_lpc_init(acpi_pchlpc->address, acpi_pchlpc->size, irq_handle, parent_irq);
+	if (ret) {
+		irq_dispose_mapping(parent_irq);
+		irq_domain_free_fwnode(irq_handle);
+		return ret;
+	}
+
+	return 0;
+}
-- 
2.52.0

[PATCH v4 5/6] irqchip/loongson-pch-lpc: Add OF init code

[Icenowy Zheng]

The OF-based MIPS Loongson-3 systems can also have a PCH LPC interrupt
controller.

Add OF-based initialization code for this driver.

Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/irq-loongson-pch-lpc.c | 35 ++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
index 2bb6659e9a93c..7117ca6fc2f05 100644
--- a/drivers/irqchip/irq-loongson-pch-lpc.c
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -13,6 +13,8 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/syscore_ops.h>
 
 #include "irq-loongson.h"
@@ -224,6 +226,7 @@ static int __init pch_lpc_init(phys_addr_t addr, unsigned long size,
 	return -ENOMEM;
 }
 
+#ifdef CONFIG_ACPI
 int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc)
 {
 	struct fwnode_handle *irq_handle;
@@ -256,3 +259,35 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic
 
 	return 0;
 }
+#endif /* CONFIG_ACPI */
+
+#ifdef CONFIG_OF
+static int __init pch_lpc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct fwnode_handle *irq_handle;
+	struct resource res;
+	int parent_irq, ret;
+
+	if (of_address_to_resource(node, 0, &res))
+		return -EINVAL;
+
+	parent_irq = irq_of_parse_and_map(node, 0);
+	if (!parent_irq) {
+		pr_err("Failed to get the parent IRQ for LPC IRQs\n");
+		return -EINVAL;
+	}
+
+	irq_handle = of_fwnode_handle(node);
+
+	ret = pch_lpc_init(res.start, resource_size(&res), irq_handle,
+			   parent_irq);
+	if (ret) {
+		irq_dispose_mapping(parent_irq);
+		return ret;
+	}
+
+	return 0;
+}
+
+IRQCHIP_DECLARE(pch_lpc, "loongson,ls7a-lpc", pch_lpc_of_init);
+#endif /* CONFIG_OF */
-- 
2.52.0

[PATCH v4 6/6] irqchip/loongson-pch-lpc: Enable building on MIPS Loongson64

[Icenowy Zheng]

As the driver can now support OF-based platforms, it's now possible to
use it on MIPS Loongson64 machines.

Drop the requirement of LOONGARCH for this driver, to allow build on
both MIPS-based and LoongArch-based Loongson systems.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
 drivers/irqchip/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f07b00d7fef90..f2eee2bd61dd0 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -761,7 +761,6 @@ config LOONGSON_PCH_MSI
 
 config LOONGSON_PCH_LPC
 	bool "Loongson PCH LPC Controller"
-	depends on LOONGARCH
 	depends on MACH_LOONGSON64 || LOONGARCH
 	default MACH_LOONGSON64
 	select IRQ_DOMAIN_HIERARCHY
-- 
2.52.0

Re: [PATCH v4 3/6] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Jiaxun Yang]

On Sat, 21 Mar 2026, at 9:20 AM, Icenowy Zheng wrote:
> Loongson 7A series PCH contains an LPC controller with an interrupt
> controller.
>
> Add the device tree binding for the interrupt controller.
>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

> ---
>  .../loongson,pch-lpc.yaml                     | 52 +++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
>
> diff --git 
> a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml 
> b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> new file mode 100644
> index 0000000000000..ff2a425b6f0b8
> --- /dev/null
> +++ 
> b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: 
> http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson PCH LPC Controller
> +
> +maintainers:
> +  - Jiaxun Yang <jiaxun.yang@flygoat.com>
> +
> +description:
> +  This interrupt controller is found in the Loongson LS7A family of 
> PCH for
> +  accepting interrupts sent by LPC-connected peripherals and 
> signalling PIC
> +  via a single interrupt line when interrupts are available.
> +
> +properties:
> +  compatible:
> +    const: loongson,ls7a-lpc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  '#interrupt-cells':
> +    const: 2
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +  - interrupts
> +  - '#interrupt-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    lpc: interrupt-controller@10002000 {
> +      compatible = "loongson,ls7a-lpc";
> +      reg = <0x10002000 0x400>;
> +      interrupt-controller;
> +      #interrupt-cells = <2>;
> +      interrupt-parent = <&pic>;
> +      interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> +    };
> +...
> -- 
> 2.52.0

-- 
- Jiaxun

Re: [PATCH v4 6/6] irqchip/loongson-pch-lpc: Enable building on MIPS Loongson64

[Jiaxun Yang]

On Sat, 21 Mar 2026, at 9:20 AM, Icenowy Zheng wrote:
> As the driver can now support OF-based platforms, it's now possible to
> use it on MIPS Loongson64 machines.
>
> Drop the requirement of LOONGARCH for this driver, to allow build on
> both MIPS-based and LoongArch-based Loongson systems.
>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

> ---
>  drivers/irqchip/Kconfig | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index f07b00d7fef90..f2eee2bd61dd0 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -761,7 +761,6 @@ config LOONGSON_PCH_MSI
> 
>  config LOONGSON_PCH_LPC
>  	bool "Loongson PCH LPC Controller"
> -	depends on LOONGARCH
>  	depends on MACH_LOONGSON64 || LOONGARCH
>  	default MACH_LOONGSON64
>  	select IRQ_DOMAIN_HIERARCHY
> -- 
> 2.52.0

-- 
- Jiaxun

Re: [PATCH v4 0/6] Add support for LS7A LPC IRQ for MIPS Loongson systems

[Huacai Chen]

For the whole series:

Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>


On Sat, Mar 21, 2026 at 5:20 PM Icenowy Zheng <zhengxingda@iscas.ac.cn> wrote:
>
> From: Icenowy Zheng <uwu@icenowy.me>
>
> This patchset tries to add support for Loongson 7A1000 PCH's LPC
> interrupt controller to MIPS-based Loongson systems.
>
> LPC, from software's perspective of view, is just ISA, so the interrupts
> should be handled as legacy ones occupying the lowest 0-15 IRQ numbers.
> Despite the current PCH LPC driver for ACPI-based LoongArch Loongson
> machines handled it, the setup is fragile and depends on its specific
> setup sequence (allocating the LPC IRQs first, and then allocate the
> parent IRQ at PCH PIC). The refactor of extracting parent IRQ allocation
> breaks this fragile sequence, so the first two commits is created to
> address this issue (by reserving ISA interrupts from the dynamic
> allocation space).
>
> Then the remaining commits are just adding OF(DT) based initialization
> of PCH LPC interrupt controller, like what happened on PCH PIC.
>
> Tested on a Haier Boyue G51 system with legacy i8042 keyboard/mouse as
> integrated ones, with some additional patches adding the PCH LPC device
> node to the ls7a-pch.dtsi file.
>
> Changes in v4:
> - Removed "IRQ" acronym from detailed commit messages (but still kept
>   in summary phrases for the length constraint).
> - Re-format some patch to utilize 100 columns instead of 80.
> - Temporarily removed the DT patches for fitting the whole patchset into
>   the irqchip tree.
>
> Changes in v3:
> - Override arch_dynirq_lower_bound() in MIPS Loongson64 / LoongArch
>   instead of modifying the global version of function.
> - Added Rob's R-b to the binding patch.
>
> Changes in v2:
> - Rebased on top of `irq-drivers-2026-02-09` tag.
> - Compatible changed to `loongson,ls7a-lpc` .
> - Merged the patch for conditionally build of ACPI code to the patch
>   introducing OF code.
> - Sorted function variable definitions.
> - Reworded some commit messages as Thomas Glexiner suggests.
> - Added __init to the LPC irqchip OF initialization code to prevent
>   section mismatch.
>
> Icenowy Zheng (6):
>   MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs
>   LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs
>   dt-bindings: interrupt-controller: add LS7A PCH LPC
>   irqchip/loongson-pch-lpc: Extract non-ACPI-related code from ACPI init
>   irqchip/loongson-pch-lpc: Add OF init code
>   irqchip/loongson-pch-lpc: Enable building on MIPS Loongson64
>
>  .../loongson,pch-lpc.yaml                     | 52 +++++++++++
>  arch/loongarch/kernel/irq.c                   |  6 ++
>  arch/mips/loongson64/init.c                   |  6 ++
>  drivers/irqchip/Kconfig                       |  1 -
>  drivers/irqchip/irq-loongson-pch-lpc.c        | 92 +++++++++++++++----
>  5 files changed, 136 insertions(+), 21 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
>
> --
> 2.52.0
>
>

Re: [PATCH v4 3/6] dt-bindings: interrupt-controller: add LS7A PCH LPC

[Rob Herring (Arm)]

On Sat, 21 Mar 2026 17:20:29 +0800, Icenowy Zheng wrote:
> Loongson 7A series PCH contains an LPC controller with an interrupt
> controller.
> 
> Add the device tree binding for the interrupt controller.
> 
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> ---
>  .../loongson,pch-lpc.yaml                     | 52 +++++++++++++++++++
>  1 file changed, 52 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v4 1/6] MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs

[Jiaxun Yang]

On Sat, 21 Mar 2026, at 9:20 AM, Icenowy Zheng wrote:
> On some Loongson 3A devices, a LPC bus is present and some legacy
> devices (e.g. 8259) on it expect hardcoded low interrupt numbers. However
> currently the expected low range interrupt numbers are not exempted from
> the dynamic allocation, which leads to confliction when registering LPC
> interrupts in the fixed range.
>
> Override arch_dynirq_lower_bound() to reserve these low range interrupt
> numbers and prevent them from being dynamically allocated.
>
> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>

Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

@Thomas Bogendoerfer, do you mind picking this over MIPS tree?

Thanks
Jiaxun

> ---
>  arch/mips/loongson64/init.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
> index 5f73f8663ab2d..c7cc5a3d7817f 100644
> --- a/arch/mips/loongson64/init.c
> +++ b/arch/mips/loongson64/init.c
> @@ -7,6 +7,7 @@
>  #include <linux/irqchip.h>
>  #include <linux/logic_pio.h>
>  #include <linux/memblock.h>
> +#include <linux/minmax.h>
>  #include <linux/of.h>
>  #include <linux/of_address.h>
>  #include <asm/bootinfo.h>
> @@ -227,3 +228,8 @@ void __init arch_init_irq(void)
>  	reserve_pio_range();
>  	irqchip_init();
>  }
> +
> +unsigned int arch_dynirq_lower_bound(unsigned int from)
> +{
> +	return MAX(from, NR_IRQS_LEGACY);
> +}
> -- 
> 2.52.0

-- 
- Jiaxun

Re: [PATCH v4 1/6] MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs

[Thomas Bogendoerfer]

On Thu, Mar 26, 2026 at 09:40:09PM +0000, Jiaxun Yang wrote:
> 
> 
> On Sat, 21 Mar 2026, at 9:20 AM, Icenowy Zheng wrote:
> > On some Loongson 3A devices, a LPC bus is present and some legacy
> > devices (e.g. 8259) on it expect hardcoded low interrupt numbers. However
> > currently the expected low range interrupt numbers are not exempted from
> > the dynamic allocation, which leads to confliction when registering LPC
> > interrupts in the fixed range.
> >
> > Override arch_dynirq_lower_bound() to reserve these low range interrupt
> > numbers and prevent them from being dynamically allocated.
> >
> > Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
> 
> Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> @Thomas Bogendoerfer, do you mind picking this over MIPS tree?

https://lore.kernel.org/all/177453852024.1647592.16054697624437632741.tip-bot2@tip-bot2/

IMHO this in tip tree already

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]