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Wed, 25 Sep 2024 14:18:14 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 25 Sep 2024 14:18:14 +0800 Message-ID: Date: Wed, 25 Sep 2024 14:18:12 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 2/6] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs Content-Language: en-US To: Conor Dooley , , Yong Wu CC: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Yong Wu , Joerg Roedel , Will Deacon , Robin Murphy , Matthias Brugger , AngeloGioacchino Del Regno , , , , , , , Alexandre Mergnat , Bear Wang , Pablo Sun , Macpaul Lin , Sen Chu , Chris-qj chen , "MediaTek Chromebook Upstream" , Chen-Yu Tsai References: <20240924103156.13119-1-macpaul.lin@mediatek.com> <20240924103156.13119-2-macpaul.lin@mediatek.com> <20240924-haiku-drudge-79e5824d4b6f@spud> From: Macpaul Lin In-Reply-To: <20240924-haiku-drudge-79e5824d4b6f@spud> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.588500-8.000000 X-TMASE-MatchedRID: QfHZjzml1E8OwH4pD14DsPHkpkyUphL9BGvINcfHqhdb6PBUqmq+UvQU BVrvaj2GVqzxHEDTg4yCIO7cu5PDkZShxRaS8Dn1EhGH3CRdKUUS12tj9Zvd8zRCaZSKE/Osl0B rH8BQUYUhXi7xgp14q38pRfXsZjabnEpyfsnNrVIzw5Ejs3g1lqIf1lfNT7ZiVxk27EKh25I+C9 E+fi6GeW7movz4+rjW78PdD37e4xy4aCSQ7hdJ78xmTzofEWOOazzS+36ix9ybKItl61J/ycnjL TA/UDoAA6QGdvwfwZZWRVlrjsKO8N0H8LFZNFG7CKFCmhdu5cXEsTcv4IYmcFuCpxJB4M3gJq70 pWlFtQWWbNCyNAdblyX6zonwXAPVNJ30o4E0TPxXF3PdlZlUCc0/jHJTVScj1iM9jSWVg5985c/ x1FQodgevtLgqnPLci7PEd0wIBlEj2EMHngcSkJ6oP1a0mRIj X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.588500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: BF41B72D588AEB07E4AC90B862252831A27D922EF92665FEF4C9BB815DD795142000:8 On 9/25/24 00:02, Conor Dooley wrote: > On Tue, Sep 24, 2024 at 06:31:52PM +0800, Macpaul Lin wrote: >> The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due >> to an excessively long 'interrupts' property. The error message was: >> >> infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0], >> [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] >> is too long >> >> To address this issue, add "minItems: 1" and "maxItems: 5" constraints to >> the 'interrupts' property in the DT binding schema. This change allows for >> flexibility in the number of interrupts for new SoCs >> >> Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema") >> > > This space should be removed. Thanks! Will fix it in the next version. >> Signed-off-by: Macpaul Lin >> --- >> Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml >> index ea6b0f5f24de..a00f1f0045b1 100644 >> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml >> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml >> @@ -96,7 +96,8 @@ properties: >> maxItems: 1 >> >> interrupts: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 5 > > You need to add an items list here, and probably some per compatible > constraints. What are each of the itnerrupts for? > According to Friday Yang's comment, The IOMMU of MT8195 has 5 banks: 0/1/2/3/4. Each bank has a set of APB registers corresponding to the normal world, protected world 1/2/3, and secure world, respectively. Therefore, 5 interrupt numbers are needed. >> >> clocks: >> items: >> -- >> 2.45.2 >> Will try to fix it and add some description for MT8195. I think this patch could be split as a separated patch from the origin patch set. It'll take some time to refine the patch. Thanks Macpaul Lin