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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5ad2e16fee3sm375352e87.31.2026.06.12.02.11.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Jun 2026 02:11:42 -0700 (PDT) Message-ID: Date: Fri, 12 Jun 2026 12:11:42 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: qcom: sm8550: add SDHC4 controller node To: William Bright Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Boukobza , Tendai Makumire References: <20260427-sm8550-sdhc4-support-v2-1-a4241f43ecd5@imd-tec.com> <5a5cbf8f-07ef-419a-8d30-c1b0b2786312@linaro.org> <00643a25-040a-4bec-8324-f52b30d84f9f@linaro.org> From: Vladimir Zapolskiy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/12/26 11:47, William Bright wrote: > On Thu, Jun 11, 2026 at 10:48:34AM +0300, Vladimir Zapolskiy wrote: >> Looks like the SDHC driver behaves expectedly then. For me it's hard to say >> what may be the rootcause, I believe the lower bus frequency should be fine, >> so it sounds like a hardware issue, but could it be PCB/board specific one? >> >> If you find a chance to copy the SDHC driver (and its small dependencies) >> from Android and test it on your board, and if it also fails, then it might >> be well concluded that something is wrong with hardware, still it won't be >> quite convincing that the SoC SDHC is to blame here. >> >> Hope it helps. >> > My colleague Tendai () had the same issue > with dll-tuning failing in SDR50 when working on the downstream 5.15 msm > kernel [1]. If Qualcomm supports their downstream Android kernel running on your board, it should be worth to contact them. > It does sound like a potential SI issue so I will try the following: > - Sweeping the drive-strength values for the sdhc_4 lines to see if I > can find a set of values that work > - Scoping the lines to check SI when performing dll-tuning, our board > is very dense so this is challenging. > I am guessing this patch is only acceptable to be upstreamed once we get > to the bottom of why dll-tuning is failing? Apparently if Qualcomm confirms that SM8550 SDHC4 actually has this discovered and unveiled defect, then this change will be accepted for all SM8550 platform like you propose it to be done. According to my experince SM8550 SDHC2 operates properly in UHS-I SDR50/SDR104 speed modes, this can be verified on the reference boards like HDK or QRD, and for me it sounds oddly that there is such a problem with SDHC4. If the proposed change as is does not enter upstream for SM8550 SoC, you may keep it as a necessary change in your particular board .dts file. > [1] https://github.com/imd-tec/meta-imdt-qcom/tree/kirkstone/patches/msm-kernel/files > -- Best wishes, Vladimir