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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: IeXcOFHXVF6DAjcENlIVMT3payo5Q7Is X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDExNyBTYWx0ZWRfXxBhCUD4n2oKx TaDQXDzo1ilUq+xP/Skm51uMU7XDCFJ16OfW+lTPLuy3Oka+/jPpN0qXZv3MM+XlyFRScArVCqA cXG0E9fT5+/Ybs8zBUMxUqmmPJRXZgQ9Evppd7sE2plpyJYrqaL87m/yBGKIXn/f5l7/9crycgl eqfd2bKCZeDIifC5oyoZVAJaPRF2TZRtzQ3a9JbZFk5PC7tVWWmhqvYLlpLBeM2/6XaQOWoTWI/ PyMhFOUVq1LLtSRWE01VSW5mfSr+29A6xqgLxhROsztrI/f0jhM+f38oKQuPMShOYQ4d4iZjmt7 9J8L+CetiuS2+W09O3hJAwVWkGi3QH3rEN1nK3LGhNcV9kSb3GtzRhVHvX8i7w392AWP1WsvLrT q5Qk1TVie6bnL9WpHupdTL3NdfLwpIqHNriyT3kaVBLamUgwC2dYidfwkCUjX5tbsWPHOt5czHR S0yZ6msSMUVGTljrjPg== X-Proofpoint-GUID: IeXcOFHXVF6DAjcENlIVMT3payo5Q7Is X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDExNyBTYWx0ZWRfX2b0kOM/IDi/R SDWRKabs+GABFvxC0esGX/VPVErgCEKOlsiLQtrM3dRro+0BKuqI6JR2lGGYVRCe7WgLGz/4tyn YvhkN9uK0NfkxZXR41K6mM7uzbi1x6E= X-Authority-Analysis: v=2.4 cv=b+uCJNGx c=1 sm=1 tr=0 ts=6a6cbfa5 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=wVA5pQU3D6HtJETKl3oCcQ==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=B7p1tibXOPgUgj-QF2sA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_05,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310117 On 27-07-2026 21:15, Rahul Samana wrote: > The reworked RB3 Gen 2 Industrial BT UART overlay needs to disable the > on-board WCN6750 PMU and add a graph endpoint to the M.2 PCI node. > > Label the exact WCN6750 PMU node and PCI child node connected to the M.2 > E-key slot so the overlay can patch them directly instead of using a full > path or reconstructing the nested PCI hierarchy. > > Signed-off-by: Rahul Samana > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 37a3b51323ce..b2b6fd29880f 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -325,7 +325,7 @@ vdd_ntn_1p8: regulator-vdd-ntn-1p8 { > regulator-enable-ramp-delay = <10000>; > }; > > - wcn6750-pmu { > + wcn6750_pmu: wcn6750-pmu { > compatible = "qcom,wcn6750-pmu"; > pinctrl-0 = <&bt_en>; > pinctrl-names = "default"; > @@ -901,7 +901,7 @@ pcie1_switch0_dsp1: pcie@1,0 { > bus-range = <0x3 0xff>; > }; > > - pcie@2,0 { > + pcie0_m2_e: pcie@2,0 { > reg = <0x21000 0x0 0x0 0x0 0x0>; > #address-cells = <3>; > #size-cells = <2>; > One correction for this patch: After re-checking the composed devicetree and the device enumeration, the QCC2072-facing PCIe path is behind the Industrial mezzanine PCIe0 switch: /soc@0/pcie@1c00000/pcie@0/pcie@0,0/pcie@2,0 The pcie@2,0 node labelled in qcs6490-rb3gen2.dts by this patch is under the base RB3 PCIe1 topology, so it is not the right endpoint for the BT UART variant. I will fix this in v3 once the endpoint modelling approach is clarified. Regards, Rahul