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[108.26.179.17]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-705cc925fe7sm3211617b3a.19.2024.06.14.07.28.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Jun 2024 07:28:34 -0700 (PDT) Message-ID: Date: Fri, 14 Jun 2024 10:28:17 -0400 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] RISC-V: Detect unaligned vector accesses supported. To: Conor Dooley Cc: linux-riscv@lists.infradead.org, Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Evan Green , Andrew Jones , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20240613191616.2101821-1-jesse@rivosinc.com> <20240613191616.2101821-5-jesse@rivosinc.com> <20240614-viral-dinghy-71d5f6585a55@wendy> <20240614-distaste-negligee-ba9216a8684e@wendy> Content-Language: en-US From: Jesse Taube In-Reply-To: <20240614-distaste-negligee-ba9216a8684e@wendy> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/14/24 04:40, Conor Dooley wrote: > On Fri, Jun 14, 2024 at 09:36:55AM +0100, Conor Dooley wrote: >> On Thu, Jun 13, 2024 at 03:16:13PM -0400, Jesse Taube wrote: >>> --- a/arch/riscv/kernel/unaligned_access_speed.c >>> +++ b/arch/riscv/kernel/unaligned_access_speed.c >>> @@ -19,7 +19,8 @@ >>> #define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE) >>> #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80) >>> >>> -DEFINE_PER_CPU(long, misaligned_access_speed); >>> +DEFINE_PER_CPU(long, misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_UNKNOWN; >>> +DEFINE_PER_CPU(long, vector_misaligned_access) = RISCV_HWPROBE_VEC_MISALIGNED_UNSUPPORTED; >>> >>> #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS >>> static cpumask_t fast_misaligned_access; >>> @@ -268,12 +269,18 @@ static int check_unaligned_access_all_cpus(void) >>> >>> if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICCLSM)) { >>> for_each_online_cpu(cpu) { >>> +#ifdef CONFIG_RISCV_VECTOR_MISALIGNED >>> + per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_VEC_MISALIGNED_FAST; >>> +#endif >>> +#ifdef CONFIG_RISCV_MISALIGNED >>> per_cpu(misaligned_access_speed, cpu) = RISCV_HWPROBE_MISALIGNED_FAST; >>> +#endif >> >> Can you IS_ENABLED()-ify these two as well please? > > Ah, you can't cos the variable doesn't exist in the other case. Yeah kinda just dealing with how it was originally written ideally we would use IS_ENABLED. I don't really want to have a 500+ diff patch IS_ENABLED()-ifying the original code as well. I can do that if necessary though. Thank, Jesse Taube