Re: [PATCH v3 5/5] arm64: dts: meson: a1: support USB controller in OTG mode

[neil.armstrong@linaro.org]

Hi,

On 26/04/2023 12:29, Dmitry Rokosov wrote:
> Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3
> heads. It supports otg/host/peripheral modes.
> 
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
> ---
>   arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 59 +++++++++++++++++++++++
>   1 file changed, 59 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index ae7d39cff07a..5588ee602161 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -8,6 +8,8 @@
>   #include <dt-bindings/gpio/meson-a1-gpio.h>
>   #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
>   #include <dt-bindings/clock/amlogic,a1-clkc.h>
> +#include <dt-bindings/power/meson-a1-power.h>
> +#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
>   
>   / {
>   	compatible = "amlogic,a1";
> @@ -169,6 +171,17 @@ gpio_intc: interrupt-controller@0440 {
>   				amlogic,channel-interrupts =
>   					<49 50 51 52 53 54 55 56>;
>   			};
> +
> +			usb2_phy1: phy@4000 {
> +				compatible = "amlogic,a1-usb2-phy";
> +				clocks = <&clkc CLKID_USB_PHY_IN>;
> +				clock-names = "xtal";
> +				reg = <0x0 0x4000 0x0 0x60>;
> +				resets = <&reset RESET_USBPHY>;
> +				reset-names = "phy";
> +				#phy-cells = <0>;
> +				power-domains = <&pwrc PWRC_USB_ID>;
> +			};
>   		};
>   
>   		gic: interrupt-controller@ff901000 {
> @@ -192,6 +205,52 @@ spifc: spi@fd000400 {
>   			#size-cells = <0>;
>   			status = "disabled";
>   		};
> +
> +		usb: usb@fe004400 {
> +			status = "disabled";
> +			compatible = "amlogic,meson-a1-usb-ctrl";
> +			reg = <0x0 0xfe004400 0x0 0xa0>;
> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +
> +			clocks = <&clkc CLKID_USB_CTRL>,
> +				 <&clkc CLKID_USB_BUS>,
> +				 <&clkc CLKID_USB_CTRL_IN>;
> +			clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
> +			resets = <&reset RESET_USBCTRL>;
> +			reset-name = "usb_ctrl";
> +
> +			dr_mode = "otg";
> +
> +			phys = <&usb2_phy1>;
> +			phy-names = "usb2-phy1";
> +
> +			dwc2: usb@ff500000 {
> +				compatible = "amlogic,meson-a1-usb", "snps,dwc2";
> +				reg = <0x0 0xff500000 0x0 0x40000>;
> +				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +				phys = <&usb2_phy1>;
> +				phy-names = "usb2-phy";
> +				clocks = <&clkc CLKID_USB_PHY>;
> +				clock-names = "otg";
> +				dr_mode = "peripheral";
> +				g-rx-fifo-size = <192>;
> +				g-np-tx-fifo-size = <128>;
> +				g-tx-fifo-size = <128 128 16 16 16>;
> +			};
> +
> +			dwc3: usb@ff400000 {
> +				compatible = "snps,dwc3";
> +				reg = <0x0 0xff400000 0x0 0x100000>;
> +				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +				dr_mode = "host";
> +				snps,dis_u2_susphy_quirk;
> +				snps,quirk-frame-length-adjustment = <0x20>;
> +				snps,parkmode-disable-ss-quirk;
> +			};
> +		};
>   	};
>   
>   	timer {

This patcj is fine, but depends on clock bindings & dt, so now Vinod took the PHY
patch, please resend this wiyhout patches 1 & 5, then resend the DT patch later when
the clock bindings is merged.

Thanks,
Neil