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Thu, 25 Sep 2025 03:34:23 -0700 (PDT) Message-ID: Date: Thu, 25 Sep 2025 13:34:22 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY To: Geert Uytterhoeven Cc: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Wolfram Sang References: <20250925100302.3508038-1-claudiu.beznea.uj@bp.renesas.com> <20250925100302.3508038-5-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi, Geert, On 9/25/25 13:15, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Thu, 25 Sept 2025 at 12:04, Claudiu wrote: >> From: Claudiu Beznea >> >> On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called >> PWRRDY. This signal is managed by the system controller and must be >> de-asserted after powering on the area where USB PHY resides and asserted >> before powering it off. >> >> On power-on the USB PWRRDY signal need to be de-asserted before enabling >> clock and switching the module to normal state (through MSTOP support). The >> power-on configuration sequence must be: >> >> 1/ PWRRDY=0 >> 2/ CLK_ON=1 >> 3/ MSTOP=0 >> >> On power-off the configuration sequence should be: >> >> 1/ MSTOP=1 >> 2/ CLK_ON=0 >> 3/ PWRRDY=1 >> >> The CLK_ON and MSTOP functionalities are controlled by clock drivers. >> >> After long discussions with the internal HW team, it has been confirmed >> that the HW connection b/w USB PHY block, the USB channels, the system >> controller, clock, MSTOP, PWRRDY signal is as follows: >> >> ┌──────────────────────────────┐ >> │ │◄── CPG_CLKON_USB.CLK0_ON >> │ USB CH0 │ >> ┌──────────────────────────┐ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK2_ON >> │ ┌────────┐ ││host controller registers │ │ >> │ │ │ ││function controller registers│ >> │ │ PHY0 │◄──┤└───────────────────────────┘ │ >> │ USB PHY │ │ └────────────▲─────────────────┘ >> │ └────────┘ │ >> │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON >> │┌──────────────┐ ┌────────┐ >> ││USHPHY control│ │ │ >> ││ registers │ │ PHY1 │ ┌──────────────────────────────┐ >> │└──────────────┘ │ │◄──┤ USB CH1 │ >> │ └────────┘ │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK1_ON >> └─▲───────▲─────────▲──────┘ ││ host controller registers │ │ >> │ │ │ │└───────────────────────────┘ │ >> │ │ │ └────────────▲─────────────────┘ >> │ │ │ │ >> │ │ │ CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON >> │PWRRDY │ │ >> │ │ CPG_CLK_ON_USB.CLK3_ON >> │ │ >> │ CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON >> │ >> ┌────┐ >> │SYSC│ >> └────┘ >> >> where: >> - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X >> of different USB blocks, X in {0, 1, 2, 3} >> - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the >> MSTOP of different USB blocks, X in {4, 5, 6, 7} >> - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used >> by the USB CH0, USB CH1 >> - SYSC is the system controller block controlling the PWRRDY signal >> - USB CHx are individual USB block with host and function capabilities >> (USB CH0 have both host and function capabilities, USB CH1 has only >> host capabilities) >> >> The USBPHY control registers are controlled though the >> reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by >> phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The >> USB PHY ports request resets from the reset-rzg2l-usbphy-ctrl driver. >> >> The connection b/w the system controller and the USB PHY CTRL driver is >> implemented through the renesas,sysc-pwrrdy device tree property >> proposed in this patch. This property specifies the register offset and the >> bitmask required to control the PWRRDY signal. >> >> Since the USB PHY CTRL driver needs to be probed before any other >> USB-specific driver on RZ/G3S, control of PWRRDY is passed exclusively >> to it. This guarantees the correct configuration sequence between clocks, >> MSTOP bits, and the PWRRDY bit. At the same time, changes are kept minimal >> by avoiding modifications to the USB PHY driver to also handle the PWRRDY >> itself. >> >> Tested-by: Wolfram Sang >> Signed-off-by: Claudiu Beznea >> --- >> >> Changes in v7: >> - used proper regmap update value on rzg2l_usbphy_ctrl_set_pwrrdy() > > Thanks for the update! > >> --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c >> +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c > >> @@ -110,6 +125,49 @@ static const struct regmap_config rzg2l_usb_regconf = { >> .max_register = 1, >> }; >> >> +static void rzg2l_usbphy_ctrl_set_pwrrdy(struct rzg2l_usbphy_ctrl_pwrrdy *pwrrdy, >> + bool power_on) >> +{ >> + u32 val = (!power_on << (ffs(pwrrdy->mask) - 1)) & pwrrdy->mask; > > ffs(x) - 1 == __ffs(x) OK, thank you! I'm going to wait for more feedback before updating it in a new version. Thank you for your review, Claudiu > >> + >> + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, val); >> +} > > Gr{oetje,eeting}s, > > Geert >