* [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling
@ 2026-02-20 4:07 Aaron Kling via B4 Relay
2026-02-20 4:07 ` [PATCH v3 1/2] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible Aaron Kling via B4 Relay
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-02-20 4:07 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pm, Aaron Kling,
Krzysztof Kozlowski, Neil Armstrong, Konrad Dybcio
Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Changes in v3:
- Squash the last two patches
- Link to v2: https://lore.kernel.org/r/20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com
Changes in v2:
- Squash first two patches
- Update opp tables in last patch to match how the downstream driver
parses those tables
- Link to v1: https://lore.kernel.org/r/20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com
---
Aaron Kling (2):
dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++
2 files changed, 368 insertions(+)
---
base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 1/2] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
2026-02-20 4:07 [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling via B4 Relay
@ 2026-02-20 4:07 ` Aaron Kling via B4 Relay
2026-02-20 4:07 ` [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
2026-03-10 20:05 ` [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling
2 siblings, 0 replies; 11+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-02-20 4:07 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pm, Aaron Kling,
Krzysztof Kozlowski
From: Aaron Kling <webgeek1234@gmail.com>
Document the OSM L3 found in the Qualcomm SM8550 platform.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 4b9b98fbe8f22258c209e8337bb4517e5f5888e8..3cbe2c3701f77d5d70082092043f2b2ccbd64905 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -34,6 +34,7 @@ properties:
- qcom,sm6375-cpucp-l3
- qcom,sm8250-epss-l3
- qcom,sm8350-epss-l3
+ - qcom,sm8550-epss-l3
- qcom,sm8650-epss-l3
- const: qcom,epss-l3
- items:
--
2.52.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
2026-02-20 4:07 [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling via B4 Relay
2026-02-20 4:07 ` [PATCH v3 1/2] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible Aaron Kling via B4 Relay
@ 2026-02-20 4:07 ` Aaron Kling via B4 Relay
2026-02-23 1:16 ` Dmitry Baryshkov
2026-03-30 14:33 ` Bjorn Andersson
2026-03-10 20:05 ` [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling
2 siblings, 2 replies; 11+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-02-20 4:07 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pm, Aaron Kling,
Neil Armstrong, Konrad Dybcio
From: Aaron Kling <webgeek1234@gmail.com>
Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
frequency by aggregating bandwidth requests of all CPU core with referenc
to the current OPP they are configured in by the LMH/EPSS hardware.
The effect is a proper caches & DDR frequency scaling when CPU cores
changes frequency.
The OPP tables were built using the downstream memlat ddr, llcc & l3
tables for each cluster types with the actual EPSS cpufreq LUT tables
from running a QCS8550 device.
Also add the OSC L3 Cache controller node.
Also add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
1 file changed, 367 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0fc36d25f3c2a6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -17,6 +17,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -78,6 +79,13 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@@ -104,6 +112,13 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_100: l2-cache {
compatible = "cache";
@@ -125,6 +140,13 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_200: l2-cache {
compatible = "cache";
@@ -146,6 +168,13 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_300: l2-cache {
compatible = "cache";
@@ -167,6 +196,13 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_400: l2-cache {
compatible = "cache";
@@ -188,6 +224,13 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_500: l2-cache {
compatible = "cache";
@@ -209,6 +252,13 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <270>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_600: l2-cache {
compatible = "cache";
@@ -230,6 +280,13 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
+ operating-points-v2 = <&cpu7_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_700: l2-cache {
compatible = "cache";
@@ -397,6 +454,306 @@ memory@a0000000 {
reg = <0 0xa0000000 0 0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
+ };
+
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-672000000 {
+ opp-hz = /bits/ 64 <672000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
+ };
+
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
+ };
+
+ opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-499200000 {
+ opp-hz = /bits/ 64 <499200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-614400000 {
+ opp-hz = /bits/ 64 <614400000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1171200000 {
+ opp-hz = /bits/ 64 <1171200000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
+ };
+
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2188800000 {
+ opp-hz = /bits/ 64 <2188800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2323200000 {
+ opp-hz = /bits/ 64 <2323200000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2457600000 {
+ opp-hz = /bits/ 64 <2457600000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2592000000 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2803200000 {
+ opp-hz = /bits/ 64 <2803200000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+ };
+
+ cpu7_opp_table: opp-table-cpu7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-595200000 {
+ opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
+ };
+
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
+ };
+
+ opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
+ };
+
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
+ };
+
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
+ };
+
+ opp-1977600000 {
+ opp-hz = /bits/ 64 <1977600000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
+ };
+
+ opp-2092800000 {
+ opp-hz = /bits/ 64 <2092800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2227200000 {
+ opp-hz = /bits/ 64 <2227200000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2476800000 {
+ opp-hz = /bits/ 64 <2476800000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2592000000 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2726400000 {
+ opp-hz = /bits/ 64 <2726400000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
+ };
+
+ opp-2841600000 {
+ opp-hz = /bits/ 64 <2841600000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+
+ opp-2956800000 {
+ opp-hz = /bits/ 64 <2956800000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+
+ opp-3187200000 {
+ opp-hz = /bits/ 64 <3187200000>;
+ opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
+ };
+ };
+
pmu-a510 {
compatible = "arm,cortex-a510-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ epss_l3: interconnect@17d90000 {
+ compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
+ reg = <0 0x17d90000 0 0x1000>;
+
+ clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@17d91000 {
compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x17d91000 0 0x1000>,
--
2.52.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
2026-02-20 4:07 ` [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
@ 2026-02-23 1:16 ` Dmitry Baryshkov
2026-03-30 14:33 ` Bjorn Andersson
1 sibling, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2026-02-23 1:16 UTC (permalink / raw)
To: webgeek1234
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar, linux-arm-msm,
devicetree, linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
On Thu, Feb 19, 2026 at 10:07:40PM -0600, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> frequency by aggregating bandwidth requests of all CPU core with referenc
> to the current OPP they are configured in by the LMH/EPSS hardware.
>
> The effect is a proper caches & DDR frequency scaling when CPU cores
> changes frequency.
>
> The OPP tables were built using the downstream memlat ddr, llcc & l3
> tables for each cluster types with the actual EPSS cpufreq LUT tables
> from running a QCS8550 device.
>
> Also add the OSC L3 Cache controller node.
>
> Also add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
>
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
> 1 file changed, 367 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling
2026-02-20 4:07 [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling via B4 Relay
2026-02-20 4:07 ` [PATCH v3 1/2] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible Aaron Kling via B4 Relay
2026-02-20 4:07 ` [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
@ 2026-03-10 20:05 ` Aaron Kling
2026-03-10 20:20 ` Krzysztof Kozlowski
2 siblings, 1 reply; 11+ messages in thread
From: Aaron Kling @ 2026-03-10 20:05 UTC (permalink / raw)
To: webgeek1234
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar, linux-arm-msm,
devicetree, linux-kernel, linux-pm, Krzysztof Kozlowski,
Neil Armstrong, Konrad Dybcio
On Thu, Feb 19, 2026 at 10:07 PM Aaron Kling via B4 Relay
<devnull+webgeek1234.gmail.com@kernel.org> wrote:
>
> Add the OSM L3 controller node then add the necessary interconnect
> properties with the appropriate OPP table for each CPU cluster to
> allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
> cluster operating point.
>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> Changes in v3:
> - Squash the last two patches
> - Link to v2: https://lore.kernel.org/r/20260218-sm8550-ddr-bw-scaling-v2-0-43a2b6d47e70@gmail.com
>
> Changes in v2:
> - Squash first two patches
> - Update opp tables in last patch to match how the downstream driver
> parses those tables
> - Link to v1: https://lore.kernel.org/r/20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com
>
> ---
> Aaron Kling (2):
> dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
> arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
>
> .../bindings/interconnect/qcom,osm-l3.yaml | 1 +
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++
> 2 files changed, 368 insertions(+)
> ---
> base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
> change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
>
> Best regards,
> --
> Aaron Kling <webgeek1234@gmail.com>
What is the normal merge sequence and window for linux-arm-msm? I see
several things that have been picked up for -next recently, but none
of my sm8550 patches that have been reviewed / approved have been
picked up yet.
Sincerely,
Aaron
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling
2026-03-10 20:05 ` [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling
@ 2026-03-10 20:20 ` Krzysztof Kozlowski
2026-03-10 20:31 ` Aaron Kling
0 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-10 20:20 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar, linux-arm-msm,
devicetree, linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
On 10/03/2026 21:05, Aaron Kling wrote:
>> ---
>> Aaron Kling (2):
>> dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
>> arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
>>
>> .../bindings/interconnect/qcom,osm-l3.yaml | 1 +
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++
>> 2 files changed, 368 insertions(+)
>> ---
>> base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
>> change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
>>
>> Best regards,
>> --
>> Aaron Kling <webgeek1234@gmail.com>
>
> What is the normal merge sequence and window for linux-arm-msm? I see
> several things that have been picked up for -next recently, but none
> of my sm8550 patches that have been reviewed / approved have been
> picked up yet.
This one is probably waiting on interconnect, no? Not saying that
merging here is easy, quite the opposite - it's frustrating, but you can
help by responding with actual data, e.g. bindings were merged and DTS
can go, instead of just content-less ping.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling
2026-03-10 20:20 ` Krzysztof Kozlowski
@ 2026-03-10 20:31 ` Aaron Kling
2026-03-10 20:48 ` Krzysztof Kozlowski
2026-03-11 13:45 ` Georgi Djakov
0 siblings, 2 replies; 11+ messages in thread
From: Aaron Kling @ 2026-03-10 20:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar, linux-arm-msm,
devicetree, linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
On Tue, Mar 10, 2026 at 3:20 PM Krzysztof Kozlowski
<krzysztof.kozlowski@oss.qualcomm.com> wrote:
>
> On 10/03/2026 21:05, Aaron Kling wrote:
> >> ---
> >> Aaron Kling (2):
> >> dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
> >> arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
> >>
> >> .../bindings/interconnect/qcom,osm-l3.yaml | 1 +
> >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++
> >> 2 files changed, 368 insertions(+)
> >> ---
> >> base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
> >> change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
> >>
> >> Best regards,
> >> --
> >> Aaron Kling <webgeek1234@gmail.com>
> >
> > What is the normal merge sequence and window for linux-arm-msm? I see
> > several things that have been picked up for -next recently, but none
> > of my sm8550 patches that have been reviewed / approved have been
> > picked up yet.
>
>
> This one is probably waiting on interconnect, no? Not saying that
> merging here is easy, quite the opposite - it's frustrating, but you can
> help by responding with actual data, e.g. bindings were merged and DTS
> can go, instead of just content-less ping.
So patch 1, the bindings, has to go via a different tree; then patch 2
goes via linux-arm-msm? Or does the first patch need an ack from other
people? I was assuming both of these could be handled by the
linux-arm-msm maintainers.
Part of this was a reminder, yes, but the question is still honest. I
don't know what the expected merge window is here, knowing that is
good to know if something got lost in the mix. I've got a couple other
patches as well that are standalone dt changes with no other deps.
I've had patches to other subsystems that have sat for four or five
cycles just waiting on the subsystem maintainers.
Aaron
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling
2026-03-10 20:31 ` Aaron Kling
@ 2026-03-10 20:48 ` Krzysztof Kozlowski
2026-03-11 13:45 ` Georgi Djakov
1 sibling, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2026-03-10 20:48 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Sibi Sankar, linux-arm-msm,
devicetree, linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
On 10/03/2026 21:31, Aaron Kling wrote:
>>>>
>>>> Best regards,
>>>> --
>>>> Aaron Kling <webgeek1234@gmail.com>
>>>
>>> What is the normal merge sequence and window for linux-arm-msm? I see
>>> several things that have been picked up for -next recently, but none
>>> of my sm8550 patches that have been reviewed / approved have been
>>> picked up yet.
>>
>>
>> This one is probably waiting on interconnect, no? Not saying that
>> merging here is easy, quite the opposite - it's frustrating, but you can
>> help by responding with actual data, e.g. bindings were merged and DTS
>> can go, instead of just content-less ping.
>
> So patch 1, the bindings, has to go via a different tree; then patch 2
> goes via linux-arm-msm?
Yes, at least typically.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling
2026-03-10 20:31 ` Aaron Kling
2026-03-10 20:48 ` Krzysztof Kozlowski
@ 2026-03-11 13:45 ` Georgi Djakov
1 sibling, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2026-03-11 13:45 UTC (permalink / raw)
To: Aaron Kling, Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, linux-arm-msm, devicetree,
linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
On 3/10/26 10:31 PM, Aaron Kling wrote:
> On Tue, Mar 10, 2026 at 3:20 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@oss.qualcomm.com> wrote:
>>
>> On 10/03/2026 21:05, Aaron Kling wrote:
>>>> ---
>>>> Aaron Kling (2):
>>>> dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
>>>> arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
>>>>
>>>> .../bindings/interconnect/qcom,osm-l3.yaml | 1 +
>>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++
>>>> 2 files changed, 368 insertions(+)
>>>> ---
>>>> base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
>>>> change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
>>>>
>>>> Best regards,
>>>> --
>>>> Aaron Kling <webgeek1234@gmail.com>
>>>
>>> What is the normal merge sequence and window for linux-arm-msm? I see
>>> several things that have been picked up for -next recently, but none
>>> of my sm8550 patches that have been reviewed / approved have been
>>> picked up yet.
>>
>>
>> This one is probably waiting on interconnect, no? Not saying that
>> merging here is easy, quite the opposite - it's frustrating, but you can
>> help by responding with actual data, e.g. bindings were merged and DTS
>> can go, instead of just content-less ping.
>
> So patch 1, the bindings, has to go via a different tree; then patch 2
> goes via linux-arm-msm? Or does the first patch need an ack from other
> people? I was assuming both of these could be handled by the
> linux-arm-msm maintainers.
>
> Part of this was a reminder, yes, but the question is still honest. I
> don't know what the expected merge window is here, knowing that is
> good to know if something got lost in the mix. I've got a couple other
> patches as well that are standalone dt changes with no other deps.
> I've had patches to other subsystems that have sat for four or five
> cycles just waiting on the subsystem maintainers.
Hi Aaron,
Last week i picked the 1st patch, so it's in this week's linux-next
releases already. I usually push an immutable branch if there are other
patches that depend on the one i picked, so i did that (icc-sm8550-osm-l3
branch).
Now the Qualcomm maintainers can pick the dts change if they want. My
observations are that the qcom dt tree is closing around -rc5, to give
some time for new patches to get tested before they send a pull request
to the arm-soc maintainers. If some patch is not picked, it's a good
idea to re-base and re-send when the next -rc1 is out.
Thanks,
Georgi
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
2026-02-20 4:07 ` [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
2026-02-23 1:16 ` Dmitry Baryshkov
@ 2026-03-30 14:33 ` Bjorn Andersson
2026-03-30 21:52 ` Aaron Kling
1 sibling, 1 reply; 11+ messages in thread
From: Bjorn Andersson @ 2026-03-30 14:33 UTC (permalink / raw)
To: webgeek1234
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Georgi Djakov, Sibi Sankar, linux-arm-msm, devicetree,
linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
On Thu, Feb 19, 2026 at 10:07:40PM -0600, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> frequency by aggregating bandwidth requests of all CPU core with referenc
> to the current OPP they are configured in by the LMH/EPSS hardware.
>
> The effect is a proper caches & DDR frequency scaling when CPU cores
> changes frequency.
>
> The OPP tables were built using the downstream memlat ddr, llcc & l3
> tables for each cluster types with the actual EPSS cpufreq LUT tables
> from running a QCS8550 device.
>
> Also add the OSC L3 Cache controller node.
>
> Also add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
>
"8 out of 11 hunks FAILED", it seems things moved since you wrote this.
Can you please help me by rebasing this onto linux-next and resubmitting
it?
Regards,
Bjorn
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
> 1 file changed, 367 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0fc36d25f3c2a6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -17,6 +17,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
> @@ -78,6 +79,13 @@ cpu0: cpu@0 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_0: l2-cache {
> compatible = "cache";
> @@ -104,6 +112,13 @@ cpu1: cpu@100 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_100: l2-cache {
> compatible = "cache";
> @@ -125,6 +140,13 @@ cpu2: cpu@200 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> capacity-dmips-mhz = <1024>;
> dynamic-power-coefficient = <100>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_200: l2-cache {
> compatible = "cache";
> @@ -146,6 +168,13 @@ cpu3: cpu@300 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_300: l2-cache {
> compatible = "cache";
> @@ -167,6 +196,13 @@ cpu4: cpu@400 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_400: l2-cache {
> compatible = "cache";
> @@ -188,6 +224,13 @@ cpu5: cpu@500 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_500: l2-cache {
> compatible = "cache";
> @@ -209,6 +252,13 @@ cpu6: cpu@600 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> capacity-dmips-mhz = <1792>;
> dynamic-power-coefficient = <270>;
> + operating-points-v2 = <&cpu3_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_600: l2-cache {
> compatible = "cache";
> @@ -230,6 +280,13 @@ cpu7: cpu@700 {
> qcom,freq-domain = <&cpufreq_hw 2>;
> capacity-dmips-mhz = <1894>;
> dynamic-power-coefficient = <588>;
> + operating-points-v2 = <&cpu7_opp_table>;
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&epss_l3 MASTER_EPSS_L3_APPS
> + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> #cooling-cells = <2>;
> l2_700: l2-cache {
> compatible = "cache";
> @@ -397,6 +454,306 @@ memory@a0000000 {
> reg = <0 0xa0000000 0 0>;
> };
>
> + cpu0_opp_table: opp-table-cpu0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-441600000 {
> + opp-hz = /bits/ 64 <441600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
> + };
> +
> + opp-556800000 {
> + opp-hz = /bits/ 64 <556800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-672000000 {
> + opp-hz = /bits/ 64 <672000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-787200000 {
> + opp-hz = /bits/ 64 <787200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
> + };
> +
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
> + };
> +
> + opp-1017600000 {
> + opp-hz = /bits/ 64 <1017600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1228800000 {
> + opp-hz = /bits/ 64 <1228800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
> + };
> +
> + opp-1344000000 {
> + opp-hz = /bits/ 64 <1344000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1459200000 {
> + opp-hz = /bits/ 64 <1459200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1555200000 {
> + opp-hz = /bits/ 64 <1555200000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1670400000 {
> + opp-hz = /bits/ 64 <1670400000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-1900800000 {
> + opp-hz = /bits/ 64 <1900800000>;
> + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-2016000000 {
> + opp-hz = /bits/ 64 <2016000000>;
> + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
> + };
> + };
> +
> + cpu3_opp_table: opp-table-cpu3 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-499200000 {
> + opp-hz = /bits/ 64 <499200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-844800000 {
> + opp-hz = /bits/ 64 <844800000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-940800000 {
> + opp-hz = /bits/ 64 <940800000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1171200000 {
> + opp-hz = /bits/ 64 <1171200000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1536000000 {
> + opp-hz = /bits/ 64 <1536000000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1651200000 {
> + opp-hz = /bits/ 64 <1651200000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1920000000 {
> + opp-hz = /bits/ 64 <1920000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-2054400000 {
> + opp-hz = /bits/ 64 <2054400000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2188800000 {
> + opp-hz = /bits/ 64 <2188800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2323200000 {
> + opp-hz = /bits/ 64 <2323200000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2457600000 {
> + opp-hz = /bits/ 64 <2457600000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2592000000 {
> + opp-hz = /bits/ 64 <2592000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2707200000 {
> + opp-hz = /bits/ 64 <2707200000>;
> + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2803200000 {
> + opp-hz = /bits/ 64 <2803200000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> + };
> +
> + cpu7_opp_table: opp-table-cpu7 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-595200000 {
> + opp-hz = /bits/ 64 <595200000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> + };
> +
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-864000000 {
> + opp-hz = /bits/ 64 <864000000>;
> + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> + };
> +
> + opp-998400000 {
> + opp-hz = /bits/ 64 <998400000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> + };
> +
> + opp-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> + };
> +
> + opp-1478400000 {
> + opp-hz = /bits/ 64 <1478400000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> + };
> +
> + opp-1708800000 {
> + opp-hz = /bits/ 64 <1708800000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1843200000 {
> + opp-hz = /bits/ 64 <1843200000>;
> + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-1977600000 {
> + opp-hz = /bits/ 64 <1977600000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> + };
> +
> + opp-2092800000 {
> + opp-hz = /bits/ 64 <2092800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2227200000 {
> + opp-hz = /bits/ 64 <2227200000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2342400000 {
> + opp-hz = /bits/ 64 <2342400000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2476800000 {
> + opp-hz = /bits/ 64 <2476800000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2592000000 {
> + opp-hz = /bits/ 64 <2592000000>;
> + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2726400000 {
> + opp-hz = /bits/ 64 <2726400000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
> + };
> +
> + opp-2841600000 {
> + opp-hz = /bits/ 64 <2841600000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-2956800000 {
> + opp-hz = /bits/ 64 <2956800000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> +
> + opp-3187200000 {
> + opp-hz = /bits/ 64 <3187200000>;
> + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> + };
> + };
> +
> pmu-a510 {
> compatible = "arm,cortex-a510-pmu";
> interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> @@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
> };
> };
>
> + epss_l3: interconnect@17d90000 {
> + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
> + reg = <0 0x17d90000 0 0x1000>;
> +
> + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #interconnect-cells = <1>;
> + };
> +
> cpufreq_hw: cpufreq@17d91000 {
> compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
> reg = <0 0x17d91000 0 0x1000>,
>
> --
> 2.52.0
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
2026-03-30 14:33 ` Bjorn Andersson
@ 2026-03-30 21:52 ` Aaron Kling
0 siblings, 0 replies; 11+ messages in thread
From: Aaron Kling @ 2026-03-30 21:52 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Georgi Djakov, Sibi Sankar, linux-arm-msm, devicetree,
linux-kernel, linux-pm, Neil Armstrong, Konrad Dybcio
On Mon, Mar 30, 2026 at 9:33 AM Bjorn Andersson <andersson@kernel.org> wrote:
>
> On Thu, Feb 19, 2026 at 10:07:40PM -0600, Aaron Kling via B4 Relay wrote:
> > From: Aaron Kling <webgeek1234@gmail.com>
> >
> > Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7)
> > to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache
> > frequency by aggregating bandwidth requests of all CPU core with referenc
> > to the current OPP they are configured in by the LMH/EPSS hardware.
> >
> > The effect is a proper caches & DDR frequency scaling when CPU cores
> > changes frequency.
> >
> > The OPP tables were built using the downstream memlat ddr, llcc & l3
> > tables for each cluster types with the actual EPSS cpufreq LUT tables
> > from running a QCS8550 device.
> >
> > Also add the OSC L3 Cache controller node.
> >
> > Also add the interconnect entry for each cpu, with 3 different paths:
> > - CPU to Last Level Cache Controller (LLCC)
> > - Last Level Cache Controller (LLCC) to DDR
> > - L3 Cache from CPU to DDR interface
> >
>
> "8 out of 11 hunks FAILED", it seems things moved since you wrote this.
> Can you please help me by rebasing this onto linux-next and resubmitting
> it?
This was a conflict from the EAS patch. I have sent a new revision
rebased on today's -next.
Aaron
> Regards,
> Bjorn
>
> > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 367 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..de4d43f7b8d2416997db70c98b0fc36d25f3c2a6 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -17,6 +17,7 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interconnect/qcom,icc.h>
> > #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> > +#include <dt-bindings/interconnect/qcom,osm-l3.h>
> > #include <dt-bindings/mailbox/qcom-ipcc.h>
> > #include <dt-bindings/power/qcom-rpmpd.h>
> > #include <dt-bindings/power/qcom,rpmhpd.h>
> > @@ -78,6 +79,13 @@ cpu0: cpu@0 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_0: l2-cache {
> > compatible = "cache";
> > @@ -104,6 +112,13 @@ cpu1: cpu@100 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_100: l2-cache {
> > compatible = "cache";
> > @@ -125,6 +140,13 @@ cpu2: cpu@200 {
> > qcom,freq-domain = <&cpufreq_hw 0>;
> > capacity-dmips-mhz = <1024>;
> > dynamic-power-coefficient = <100>;
> > + operating-points-v2 = <&cpu0_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_200: l2-cache {
> > compatible = "cache";
> > @@ -146,6 +168,13 @@ cpu3: cpu@300 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_300: l2-cache {
> > compatible = "cache";
> > @@ -167,6 +196,13 @@ cpu4: cpu@400 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_400: l2-cache {
> > compatible = "cache";
> > @@ -188,6 +224,13 @@ cpu5: cpu@500 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_500: l2-cache {
> > compatible = "cache";
> > @@ -209,6 +252,13 @@ cpu6: cpu@600 {
> > qcom,freq-domain = <&cpufreq_hw 1>;
> > capacity-dmips-mhz = <1792>;
> > dynamic-power-coefficient = <270>;
> > + operating-points-v2 = <&cpu3_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_600: l2-cache {
> > compatible = "cache";
> > @@ -230,6 +280,13 @@ cpu7: cpu@700 {
> > qcom,freq-domain = <&cpufreq_hw 2>;
> > capacity-dmips-mhz = <1894>;
> > dynamic-power-coefficient = <588>;
> > + operating-points-v2 = <&cpu7_opp_table>;
> > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > + <&epss_l3 MASTER_EPSS_L3_APPS
> > + &epss_l3 SLAVE_EPSS_L3_SHARED>;
> > #cooling-cells = <2>;
> > l2_700: l2-cache {
> > compatible = "cache";
> > @@ -397,6 +454,306 @@ memory@a0000000 {
> > reg = <0 0xa0000000 0 0>;
> > };
> >
> > + cpu0_opp_table: opp-table-cpu0 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-307200000 {
> > + opp-hz = /bits/ 64 <307200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-441600000 {
> > + opp-hz = /bits/ 64 <441600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>;
> > + };
> > +
> > + opp-556800000 {
> > + opp-hz = /bits/ 64 <556800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-672000000 {
> > + opp-hz = /bits/ 64 <672000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-787200000 {
> > + opp-hz = /bits/ 64 <787200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-902400000 {
> > + opp-hz = /bits/ 64 <902400000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>;
> > + };
> > +
> > + opp-1017600000 {
> > + opp-hz = /bits/ 64 <1017600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1113600000 {
> > + opp-hz = /bits/ 64 <1113600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1228800000 {
> > + opp-hz = /bits/ 64 <1228800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1152000 * 32)>;
> > + };
> > +
> > + opp-1344000000 {
> > + opp-hz = /bits/ 64 <1344000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1459200000 {
> > + opp-hz = /bits/ 64 <1459200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1555200000 {
> > + opp-hz = /bits/ 64 <1555200000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1670400000 {
> > + opp-hz = /bits/ 64 <1670400000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1785600000 {
> > + opp-hz = /bits/ 64 <1785600000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-1900800000 {
> > + opp-hz = /bits/ 64 <1900800000>;
> > + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-2016000000 {
> > + opp-hz = /bits/ 64 <2016000000>;
> > + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1804800 * 32)>;
> > + };
> > + };
> > +
> > + cpu3_opp_table: opp-table-cpu3 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-499200000 {
> > + opp-hz = /bits/ 64 <499200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-614400000 {
> > + opp-hz = /bits/ 64 <614400000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-729600000 {
> > + opp-hz = /bits/ 64 <729600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-844800000 {
> > + opp-hz = /bits/ 64 <844800000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-940800000 {
> > + opp-hz = /bits/ 64 <940800000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1056000000 {
> > + opp-hz = /bits/ 64 <1056000000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1171200000 {
> > + opp-hz = /bits/ 64 <1171200000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1286400000 {
> > + opp-hz = /bits/ 64 <1286400000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1401600000 {
> > + opp-hz = /bits/ 64 <1401600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1536000000 {
> > + opp-hz = /bits/ 64 <1536000000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1651200000 {
> > + opp-hz = /bits/ 64 <1651200000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1785600000 {
> > + opp-hz = /bits/ 64 <1785600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1920000000 {
> > + opp-hz = /bits/ 64 <1920000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-2054400000 {
> > + opp-hz = /bits/ 64 <2054400000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2188800000 {
> > + opp-hz = /bits/ 64 <2188800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2323200000 {
> > + opp-hz = /bits/ 64 <2323200000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2457600000 {
> > + opp-hz = /bits/ 64 <2457600000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2592000000 {
> > + opp-hz = /bits/ 64 <2592000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2707200000 {
> > + opp-hz = /bits/ 64 <2707200000>;
> > + opp-peak-kBps = <(933000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2803200000 {
> > + opp-hz = /bits/ 64 <2803200000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > + };
> > +
> > + cpu7_opp_table: opp-table-cpu7 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-595200000 {
> > + opp-hz = /bits/ 64 <595200000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>;
> > + };
> > +
> > + opp-729600000 {
> > + opp-hz = /bits/ 64 <729600000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-864000000 {
> > + opp-hz = /bits/ 64 <864000000>;
> > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>;
> > + };
> > +
> > + opp-998400000 {
> > + opp-hz = /bits/ 64 <998400000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1132800000 {
> > + opp-hz = /bits/ 64 <1132800000>;
> > + opp-peak-kBps = <(300000 * 16) (768000 * 4) (729600 * 32)>;
> > + };
> > +
> > + opp-1248000000 {
> > + opp-hz = /bits/ 64 <1248000000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1363200000 {
> > + opp-hz = /bits/ 64 <1363200000>;
> > + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (940800 * 32)>;
> > + };
> > +
> > + opp-1478400000 {
> > + opp-hz = /bits/ 64 <1478400000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1593600000 {
> > + opp-hz = /bits/ 64 <1593600000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1056000 * 32)>;
> > + };
> > +
> > + opp-1708800000 {
> > + opp-hz = /bits/ 64 <1708800000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1843200000 {
> > + opp-hz = /bits/ 64 <1843200000>;
> > + opp-peak-kBps = <(600000 * 16) (1708000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-1977600000 {
> > + opp-hz = /bits/ 64 <1977600000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1267200 * 32)>;
> > + };
> > +
> > + opp-2092800000 {
> > + opp-hz = /bits/ 64 <2092800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2227200000 {
> > + opp-hz = /bits/ 64 <2227200000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2342400000 {
> > + opp-hz = /bits/ 64 <2342400000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2476800000 {
> > + opp-hz = /bits/ 64 <2476800000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2592000000 {
> > + opp-hz = /bits/ 64 <2592000000>;
> > + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2726400000 {
> > + opp-hz = /bits/ 64 <2726400000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1478400 * 32)>;
> > + };
> > +
> > + opp-2841600000 {
> > + opp-hz = /bits/ 64 <2841600000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-2956800000 {
> > + opp-hz = /bits/ 64 <2956800000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > +
> > + opp-3187200000 {
> > + opp-hz = /bits/ 64 <3187200000>;
> > + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1689600 * 32)>;
> > + };
> > + };
> > +
> > pmu-a510 {
> > compatible = "arm,cortex-a510-pmu";
> > interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> > @@ -5437,6 +5794,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
> > };
> > };
> >
> > + epss_l3: interconnect@17d90000 {
> > + compatible = "qcom,sm8550-epss-l3", "qcom,epss-l3";
> > + reg = <0 0x17d90000 0 0x1000>;
> > +
> > + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
> > + clock-names = "xo", "alternate";
> > +
> > + #interconnect-cells = <1>;
> > + };
> > +
> > cpufreq_hw: cpufreq@17d91000 {
> > compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
> > reg = <0 0x17d91000 0 0x1000>,
> >
> > --
> > 2.52.0
> >
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2026-03-30 21:52 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
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2026-02-20 4:07 [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling via B4 Relay
2026-02-20 4:07 ` [PATCH v3 1/2] dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible Aaron Kling via B4 Relay
2026-02-20 4:07 ` [PATCH v3 2/2] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths Aaron Kling via B4 Relay
2026-02-23 1:16 ` Dmitry Baryshkov
2026-03-30 14:33 ` Bjorn Andersson
2026-03-30 21:52 ` Aaron Kling
2026-03-10 20:05 ` [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling Aaron Kling
2026-03-10 20:20 ` Krzysztof Kozlowski
2026-03-10 20:31 ` Aaron Kling
2026-03-10 20:48 ` Krzysztof Kozlowski
2026-03-11 13:45 ` Georgi Djakov
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