From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4428A3BE632; Tue, 31 Mar 2026 07:27:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942038; cv=none; b=SjY2wRn/DMv0MM0X8d1KG4giC1ro0Qiun4AzzrOYQTr5Y3TFIgsUk1di0b2VLSx9j1liCl1Voyzgzf8SAteGcuk/EiMpxHn7GmOTUy8sLyRkB9ChhvSPvT+4E7NvSHE3XRl79oK/NP0qsfirAZrD0lLBLa7bT7BTeqXSr1SBhPI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942038; c=relaxed/simple; bh=X3yeokNyZn70wlzcDKDkqaW2bU/NrHBKm0YhEEm8C3s=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=pM9m3ODD+VTMoC8kz95CShpDFlgpdKhcnLtwup+yR4jWZj55xmZhnn7EEZbwWiamjOFpXOPwzMejoMTlN4NI5cE14TeYpjA36dyeRo4iMN4nALMV3hPeaiaw/xn4y2sWMGIUyDwX38BgX+rXPO9kAbF5RfnYehXE5owL2bdJAz4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pLpjq19P; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pLpjq19P" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 859FFC19423; Tue, 31 Mar 2026 07:27:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774942037; bh=X3yeokNyZn70wlzcDKDkqaW2bU/NrHBKm0YhEEm8C3s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pLpjq19PE1SvYAIgikedhFgItbR1nnEWD5PfIOYkpgq1UhPPvheKQ6vZtsFZCaCBq u6T8jCDGkZi8NHC8rIRG4A8h9p9/x7bFjYWOixLN02gtHe6EwClLJ83jKSIOWAJtUN Dl0WvfrJ6kZL7V6xrGCaIXk2yw1OF1mwZAlNa6HcJ1egtOfv1JfKCoNOuFB8qxrl2j cG81rVGfxEbq1beD6Znz8Ja2INBnqa5RbQolxmANaiteZaTPfP9s5fKHZkv+a7uwNi rXNLXkxumleCcNn5vZC1Z7h6TSN7AUCmsrkEO3iC3oc9Jj26CEtXQ1wmn5upb2IKey YtJgUUgCLmmLQ== Date: Tue, 31 Mar 2026 09:27:15 +0200 From: Thierry Reding To: Mikko Perttunen Cc: Thierry Reding , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yi-Wei Wang Subject: Re: [PATCH v2 4/7] pwm: tegra: Parametrize enable register offset Message-ID: References: <20260325-t264-pwm-v2-0-998d885984b3@nvidia.com> <20260325-t264-pwm-v2-4-998d885984b3@nvidia.com> <177483744958.916245.860145469758840098.b4-reply@b4> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="czd7pk4dwbs6pmxq" Content-Disposition: inline In-Reply-To: <177483744958.916245.860145469758840098.b4-reply@b4> --czd7pk4dwbs6pmxq Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v2 4/7] pwm: tegra: Parametrize enable register offset MIME-Version: 1.0 On Mon, Mar 30, 2026 at 11:24:09AM +0900, Mikko Perttunen wrote: > On 2026-03-26 10:47 +0100, Thierry Reding wrote: > > On Wed, Mar 25, 2026 at 07:17:02PM +0900, Mikko Perttunen wrote: > > > On Tegra264, the PWM enablement bit is not located at the base address > > > of the PWM controller. Hence, introduce an enablement offset field in > > > the tegra_pwm_soc structure to describe the offset of the register. > > >=20 > > > Co-developed-by: Yi-Wei Wang > > > Signed-off-by: Yi-Wei Wang > > > Signed-off-by: Mikko Perttunen > > > --- > > > drivers/pwm/pwm-tegra.c | 17 ++++++++++++----- > > > 1 file changed, 12 insertions(+), 5 deletions(-) > > >=20 > > > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c > > > index cf54f75d92a5..22d709986e8c 100644 > > > --- a/drivers/pwm/pwm-tegra.c > > > +++ b/drivers/pwm/pwm-tegra.c > > > @@ -61,6 +61,7 @@ > > > =20 > > > struct tegra_pwm_soc { > > > unsigned int num_channels; > > > + unsigned int enable_reg; > > > }; > > > =20 > > > struct tegra_pwm_chip { > > > @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip= , struct pwm_device *pwm, > > > err =3D pm_runtime_resume_and_get(pwmchip_parent(chip)); > > > if (err) > > > return err; > > > - } else > > > + } else if (pc->soc->enable_reg =3D=3D PWM_CSR_0) { > > > val |=3D PWM_ENABLE; > > > + } > >=20 > > This looks incomplete for the Tegra264 case where > >=20 > > pc->soc->enable_reg =3D=3D PWM_CSR_1 > >=20 > > > =20 > > > pwm_writel(pwm, PWM_CSR_0, val); > >=20 > > I think we need another write for PWM_CSR_1 here to properly toggle the > > PWM_ENABLE bit on Tegra264. > >=20 > > Or am I missing something? >=20 > This check is here just so we don't change the value of PWM_ENABLE when > writing the CSR_0 register. The function doesn't write to CSR_1 so > nothing needs to be done on Tegra264. >=20 > I agree it's not the clearest, but it'll get cleaned up when adding > support for configurable depth, as at that point we will need to write > both registers on Tegra264. Ah... nevermind. I realize now that we're not touching PWM_CSR_1 at all in tegra_pwm_config(), so there's no need to explicitly set PWM_ENABLE. If moving to the new APIs, that would need to change, but for the legacy PWM callbacks this is probably fine. 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