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[2003:f6:5f20:eb04:8bf9:5aaa:6251:6f6f]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-4887e93c014sm16826495e9.10.2026.03.31.00.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 00:03:44 -0700 (PDT) Date: Tue, 31 Mar 2026 09:03:43 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Geert Uytterhoeven Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Sean Anderson , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Chris Packham , Marek Vasut Subject: Re: New default binding for PWM devices? [Was: Re: [PATCH] dt-bindings: timer: xlnx,xps-timer: Make PWM in example usable] Message-ID: References: <20250527171504.346696-2-u.kleine-koenig@baylibre.com> <20250606141324.GA1383279-robh@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="wyl7ytgv5wvrmgoq" Content-Disposition: inline In-Reply-To: --wyl7ytgv5wvrmgoq Content-Type: text/plain; protected-headers=v1; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: New default binding for PWM devices? [Was: Re: [PATCH] dt-bindings: timer: xlnx,xps-timer: Make PWM in example usable] MIME-Version: 1.0 Hello Geert, On Mon, Mar 30, 2026 at 02:12:47PM +0200, Geert Uytterhoeven wrote: > On Sat, 7 Jun 2025 at 09:23, Uwe Kleine-K=F6nig > wrote: > > On Fri, Jun 06, 2025 at 09:13:24AM -0500, Rob Herring wrote: > > > reg: > > > > maxItems: 1 > > > > > > > > - '#pwm-cells': true > > > > + '#pwm-cells': > > > > + const: 3 > > > > > > > > xlnx,count-width: > > > > $ref: /schemas/types.yaml#/definitions/uint32 > > > > @@ -82,7 +83,7 @@ examples: > > > > }; > > > > > > > > timer@800f0000 { > > > > - #pwm-cells =3D <0>; > > > > + #pwm-cells =3D <3>; > > > > clock-names =3D "s_axi_aclk"; > > > > clocks =3D <&zynqmp_clk 71>; > > > > compatible =3D "xlnx,xps-timer-1.00.a"; > > > > > > > > There is however one concern that I want to get resolved first to > > > > prevent churn: > > > > > > > > In principle I think it's bad that a phandle to a PWM must contain a > > > > period and flags specifying the polarity. For some use cases the pe= riod > > > > might not matter or is implicitly given or more than one period len= gth > > > > is relevant. > > > > > > Why can't the period be 0 and no flags set if they aren't needed? > > > > I don't say they cannot, and probably that's the most sane option if > > there is no fixed default period and flags and we're sticking to 3 > > cells. >=20 > So zero should have been used for drivers/pwm/pwm-argon-fan-hat.c? Do you mean #pwm-cells =3D <0>? Or period =3D flags =3D 0? If the phandle wouldn't contain period and flags and so it would only be used to identify the PWM to use and say nothing about how it is used, then using #pwm-cells =3D <0> for PWM chips that only have a single PWM would work fine. Best regards Uwe --wyl7ytgv5wvrmgoq Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEP4GsaTp6HlmJrf7Tj4D7WH0S/k4FAmnLccUACgkQj4D7WH0S /k5NrAf/fw5ux7T53E9Vam6KUGE1olp2rUotaB1fGpB//Vp+V05CVJJV5GDV4VhH y2GFYYQbq1ITeXnvxHBYEbm4QRZ78Pcw10MsfyX9DmRyyFcc2Px2PI0EnkHbExfY gShB5qrky/K+ZWxwLWg4H8d5IrrTW5ol+ha7TenzMS1JjDxzjv/lMgGkyXdwLhhJ ufQzICkv2TzQw0Go1IQM3qwf62IAk8VI7j9Y2QtSStTCAVObtx3dx/PJ01rk6YVK 3AJwhMuSUEP6F1BPxKPRM1zZwet5rTfTbYUOIm1yVU2WyN2xFq/x5ExQPtQvVsxK AFcszk2tlKcAZx+GW8MHjL+1N1Oa0g== =KGrq -----END PGP SIGNATURE----- --wyl7ytgv5wvrmgoq--