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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12aba581027sm15063809c88.4.2026.03.31.02.59.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 02:59:14 -0700 (PDT) Date: Tue, 31 Mar 2026 02:59:12 -0700 From: Qiang Yu To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/5] phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur Message-ID: References: <20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com> <20260323-glymur_gen5x8_phy_0323-v2-4-ce0fc07f0e52@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: Uk2SDit8Fpp4G7znfoa0LAQtzxVQ_hdw X-Authority-Analysis: v=2.4 cv=C5LkCAP+ c=1 sm=1 tr=0 ts=69cb9af4 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=56H2F1Fm8OXBRpAn5E4A:9 a=CjuIK1q_8ugA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-GUID: Uk2SDit8Fpp4G7znfoa0LAQtzxVQ_hdw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzMxMDA5NSBTYWx0ZWRfX3HfMZ3M+5Z2v 2F8WYzBGepBhDaQ7jH0Cufb47A3Zc4iJyQGOwZ2oqr0z//t6sw4x3VysSwqrINsPoI+ZioIcKYN yIoS0nGM2HppO8KAK/abt79+v/BY+qGKruo9blL1fRQKLjzRGTSlBNXiijUh0p15nQl7iFmem8Q jQtwZ4YbvgUQBodwxex9fw+hj2XFB5eZjQCfGGH1EwRbnXE7nR0hKDesEKWoQIOPWI/l5VZdvuT ZkOXaAfdFdIcpArDd0nNn+ogxqCq5MLjmzJ+wDYSSejD3bSBB833PMk0kaqiNcw93Zthat/CAsx Y2NaAKbxvBF8Vx0WfsBnLaYaOckwPN533FvRhcoGSM2SoZqVhQRp8iN9YXHM0GeSdrMxJQy25j9 f/2PC1+nFk6CVVpzjEBLOd4EjgBI0KTDnCR5Spzddi7oSVjrCN4J1EFAInYzPA0PZuxzNGqNDr6 p1kqHL844nZj3WVDcJg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-31_02,2026-03-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603310095 On Tue, Mar 24, 2026 at 11:23:19PM +0200, Dmitry Baryshkov wrote: > On Mon, Mar 23, 2026 at 12:15:31AM -0700, Qiang Yu wrote: > > The third PCIe controller on Glymur SoC supports 8-lane operation via > > bifurcation of two PHYs (each requires separate power domian, resets and > > aux clk). > > > > Add dedicated reset/no_csr reset list ("phy_b", "phy_b_nocsr") and > > clock ("phy_b_aux") required for 8-lane operation. Introduce new > > glymur_qmp_gen5x8_pciephy_cfg configuration to enable PCIe Gen5 x8 mode. > > > > Signed-off-by: Qiang Yu > > --- > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 30 +++++++++++++++++++++++++++++- > > 1 file changed, 29 insertions(+), 1 deletion(-) > > > > @@ -4705,6 +4713,23 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { > > .phy_status = PHYSTATUS_4_20, > > }; > > > > +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg = { > > + .lanes = 8, > > + > > + .offsets = &qmp_pcie_offsets_v8_50, > > + > > + .reset_list = glymur_pciephy_reset_l, > > + .num_resets = ARRAY_SIZE(glymur_pciephy_reset_l), > > + .nocsr_reset_list = glymur_pciephy_nocsr_reset_l, > > + .num_nocsr_resets = ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), > > Just for my understanding. If it was not the NOCSR case and had to > program the registers, would we have needed to program anything in the > PCIe3B space? The PCIe3B PHY registers need to be programmed. But we don't need to do it explicitly because there are also broadcast registers: writing to these registers will automatically write the same offset and value to both PHY ports simultaneously. - Qiang Yu > > > + .vreg_list = qmp_phy_vreg_l, > > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > > + > > + .regs = pciephy_v8_50_regs_layout, > > + > > + .phy_status = PHYSTATUS_4_20, > > +}; > > + > > static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) > > { > > const struct qmp_phy_cfg *cfg = qmp->cfg; > > @@ -5483,6 +5508,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { > > }, { > > .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy", > > .data = &glymur_qmp_gen5x4_pciephy_cfg, > > + }, { > > + .compatible = "qcom,glymur-qmp-gen5x8-pcie-phy", > > + .data = &glymur_qmp_gen5x8_pciephy_cfg, > > }, { > > .compatible = "qcom,ipq6018-qmp-pcie-phy", > > .data = &ipq6018_pciephy_cfg, > > > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry