From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B72DA4AD4AF; Tue, 13 Oct 2026 06:18:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791872298; cv=none; b=ZpY4BhfTdO8vDahJKlcEGxT+kaCgZ/4qoXBheLboRIneDq/lWO6qfpAy5UazLbUCtDGKlZT9TGa8LjNt1QyJmAwSaRGyrF88zvk0LS6GVri846q89vpwfrIpyBXwzwQ7UZsJ6ISw9rsPaeYAjei+nbuBrthQPtrCZ9uLNegaxk8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791872298; c=relaxed/simple; bh=a6IdMJ4Ehai4AzAzwmTbXCyofjxWQVEE1jiwx+HKFqY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=XT8HL6BiSFGGpPLHKxKgw8JUs2rlzK3WLDzD5T1cddHcI5wrBPkBiMVdwGwyNB212jM7jV0d4ZkrB5wqU46xf7bYfSmsp3uBYKJB84ElfBhh9TnltpnTpAeUfDXDCotvm+mSUAfNbyx0l9MVukVRn+SJbVs8wZVKOwKH07ACsbQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MjfJ0rkX; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MjfJ0rkX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C19271F000FF; Tue, 13 Oct 2026 06:18:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1791872297; bh=s0Owovj5yCN/YII+i8I65SUoJkW/splLTgjlRzLW90g=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=MjfJ0rkXJ2DyoAcWmEtDVDVvUKbYdcZ1Vcerv5B3uXjESwdAbG8iBg7y2LS2MeyTW 4fhCrHGYMaDTgQiiRkQBAZyTlt5KyKDsBfG0db/ywbnxyQaO949953DNJUa8X9yfSZ OvhspphTmsyF68ALJrx+RMHJ1SFPC9Kf7Kd/z2Dzts0/Lh6SjPP9RWlMiIvAWW27E7 R7APQlWX8TT7Z8WdBGWaUjfDr7SLWW38d2WZOpTkNt+l1z5WYImuYUHxJKCCs4oz8w bSpLfHRzzHfoZQHKRQ/gp3CO7sx+TsQqbN1Ts+4FFaSWlkbFCi9J3n1GItPchZBaqz iO8QfBEJdkYiw== Message-ID: Date: Tue, 13 Oct 2026 08:18:08 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 00/11] Cortina Systems CS75xx: interrupt controller, GPIO, I2C and TWD watchdog To: filipp.dunsky@gmail.com, Thomas Gleixner , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Andi Shyti , Wim Van Sebroeck , Guenter Roeck , Russell King , Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-watchdog@vger.kernel.org References: <20261013-b4-cs75xx-s2-v3-0-181bb0d23f4c@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 13/10/2026 08:07, Fil Dunsky via B4 Relay wrote: > This is the second step of the Cortina Systems CS75xx ("Goldengate G2") > / Securifi Almond+ support. It applies on top of the platform series > "ARM: Add support for Cortina Systems CS75xx and Securifi Almond+" > v6 [1] and adds: > > - a driver for the per-CPU private watchdog of the ARM11 MPCore, > Cortex-A5 and Cortex-A9 ("arm,cortex-a9-twd-wdt"), > - the peripheral interrupt controller that combines the interrupts of > the low speed peripherals into one GIC interrupt, > - the GPIO banks, > - the I2C controller, > - the device tree nodes, including the reset button of the Almond+, > and the multi_v7_defconfig and MAINTAINERS updates. > Slow down. One small patchset per 24h. If you send some big work, then once per 48h. Implement previous review. Best regards, Krzysztof