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Fri, 22 Apr 2022 14:02:20 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 22 Apr 2022 14:02:20 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 22 Apr 2022 14:02:20 -0500 Received: from [10.249.34.110] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23MJ2Jlc051088; Fri, 22 Apr 2022 14:02:19 -0500 Message-ID: Date: Fri, 22 Apr 2022 14:02:19 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/6] dt-bindings: ti,sci: Add ti,ctx-memory-region property Content-Language: en-US To: Dave Gerlach , Rob Herring , Santosh Shilimkar , Krzysztof Kozlowski , Tero Kristo , Nishanth Menon CC: , , , Vignesh Raghavendra References: <20220421203659.27853-1-d-gerlach@ti.com> <20220421203659.27853-2-d-gerlach@ti.com> From: Andrew Davis In-Reply-To: <20220421203659.27853-2-d-gerlach@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Message-ID: <20220422190219.QQQe93CSCD6PueKn-4wgRPU0CXYFDQuE6JUpDRZd97o@z> On 4/21/22 3:36 PM, Dave Gerlach wrote: > Add documentation for the ti,ctx-memory-region property which is a > phandle to a reserved-memory carveout to be used by the ti_sci driver > storage of low power mode memory context. This is optional for normal > system operation but required to enabled suspend-to-mem usage of Deep > Sleep state. > > Signed-off-by: Dave Gerlach > --- > .../devicetree/bindings/arm/keystone/ti,sci.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml > index 34f5f877d444..ec88aa88a2a0 100644 > --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml > +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml > @@ -61,6 +61,15 @@ properties: > mboxes: > minItems: 2 > > + ti,ctx-memory-region: > + description: > + Phandle to the reserved memory node to be associated with the > + ti-sci device, to be used for saving low power context. The > + reserved memory node should be a carveout node, and should > + be defined as per the bindings in > + Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml > + $ref: /schemas/types.yaml#/definitions/string > + Why does this have to be yet another reserved carveout region, should be dynamically allocated. Andrew > ti,system-reboot-controller: > description: Determines If system reboot can be triggered by SoC reboot > type: boolean