[PATCH RFC 0/2] Add Renesas RPC-IF support

[PATCH RFC 0/2] Add Renesas RPC-IF support

[Sergei Shtylyov]

Hello!

Here's a set of 2 patches against the 'for-mfd-next' branch of Lee Jones's
'mfd.git' repo. Renesas Reduced Pin Count Interface (RPC-IF) allows a SPI
flash or HyperFlash connected to the SoC to be accessed via the external
address space read mode or the manual mode. The MFD driver for RPC-IF
registers either the SPI or HyperFLash subdevice, depending on the contents
of the device tree subnode; it also provides the absract "back end" API
that can be used by the "front end" SPI/MTD drivers to talk to the real
hardware... The HyperFlash subdriver isn't ready yet, so the MFD driver
may need some updates in order to serve it, hence the RFC status...

Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>.

[1/2] dt-bindings: mfd: document Renesas RPC-IF bindings
[2/2] mfd: add Renesas RPC-IF driver

MBR, Sergei

[PATCH RFC 1/2] dt-bindings: mfd: document Renesas RPC-IF bindings

[Sergei Shtylyov]

Renesas Reduced Pin Count Interface (RPC-IF) allows a SPI flash or
HyperFlash connected to the SoC to be accessed via the external address
space read mode or the manual mode.

Document the device tree bindings for the Renesas RPC-IF found in the R-Car
gen3 SoCs.

Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 Documentation/devicetree/bindings/mfd/rpc-if.txt |   52 +++++++++++++++++++++++
 1 file changed, 52 insertions(+)

Index: mfd/Documentation/devicetree/bindings/mfd/rpc-if.txt
===================================================================
--- /dev/null
+++ mfd/Documentation/devicetree/bindings/mfd/rpc-if.txt
@@ -0,0 +1,52 @@
+Renesas Reduced Pin Count Interface (RPC-IF)
+--------------------------------------------
+
+Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
+be accessed via the external address space read mode or the manual mode.
+
+Required properties:
+- compatible: should be an SoC-specific compatible value, followed by
+		"renesas,rcar-gen3-rpcif" as a fallback.
+		supported SoC-specific values are:
+		"renesas,r8a77980-rpcif" (R-Car V3H),
+		"renesas,r8a77995-rpcif" (R-Car D3).
+- reg: should list 3 register areas:
+	1st for the RPC-IF registers,
+	2nd for the direct mapping read mode,
+	3rd for the write buffer area.
+- reg-names: should contain "regs", "dirmap", and "wbuf".
+- clocks: should contain the clock phandle/specifier pair for the module clock.
+- power-domains: should contain the power domain phandle/specifier pair.
+- resets: should contain the reset controller phandle/specifier pair.
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+
+The flash chip itself should be represented by a subnode of the RPC-IF node.
+The flash interface is selected based on the "compatible" property of this
+subnode:
+- if it contains "jedec,spi-nor", then SPI is used;
+- if it contains "cfi-flash", then HyperFlash is used.
+
+Example:
+
+	rpc: spi@ee200000 {
+		compatible = "renesas,r8a77995-rpcif",
+			     "renesas,rcar-gen3-rpcif";
+		reg = <0 0xee200000 0 0x200>,
+		      <0 0x08000000 0 0x4000000>,
+		      <0 0xee208000 0 0x100>;
+		reg-names = "regs", "dirmap", "wbuf";
+		clocks = <&cpg CPG_MOD 917>;
+		power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+		resets = <&cpg 917>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <40000000>;
+			spi-tx-bus-width = <1>;
+			spi-rx-bus-width = <1>;
+		};
+	};

Re: [PATCH RFC 0/2] Add Renesas RPC-IF support

[Lee Jones]

On Thu, 30 May 2019, Sergei Shtylyov wrote:

> Hello!
> 
> Here's a set of 2 patches against the 'for-mfd-next' branch of Lee Jones's
> 'mfd.git' repo. Renesas Reduced Pin Count Interface (RPC-IF) allows a SPI
> flash or HyperFlash connected to the SoC to be accessed via the external
> address space read mode or the manual mode. The MFD driver for RPC-IF
> registers either the SPI or HyperFLash subdevice, depending on the contents
> of the device tree subnode; it also provides the absract "back end" API
> that can be used by the "front end" SPI/MTD drivers to talk to the real
> hardware... The HyperFlash subdriver isn't ready yet, so the MFD driver
> may need some updates in order to serve it, hence the RFC status...
> 
> Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>.
> 
> [1/2] dt-bindings: mfd: document Renesas RPC-IF bindings
> [2/2] mfd: add Renesas RPC-IF driver

Please use `git` to create your cover letters.

You are missing useful information e.g. the change stats.

-- 
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH RFC 0/2] Add Renesas RPC-IF support

[Sergei Shtylyov]

Hello!

Here's a set of 2 patches against Linus' repo. Renesas Reduced Pin Count
Interface (RPC-IF) allows a SPI flash or HyperFlash connected to the SoC
to be accessed via the external address space read mode or the manual mode.
The memory controller driver for RPC-IF registers either the SPI or HyperFLash
subdevice, depending on the contents of the device tree subnode; it also
provides the abstract "back end" API that can be used by the "front end"
SPI/MTD drivers to talk to the real hardware...

Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>.

[1/2] dt-bindings: memory: document Renesas RPC-IF bindings
[2/2] memory: add Renesas RPC-IF driver

MBR, Sergei

RE: [PATCH RFC 0/2] Add Renesas RPC-IF support

[Chris Brandt]

Hello Sergei,

On Tue, Dec 10, 2019, Sergei Shtylyov wrote:
> Here's a set of 2 patches against Linus' repo. Renesas Reduced Pin Count
> Interface (RPC-IF) allows a SPI flash or HyperFlash connected to the SoC to
> be accessed via the external address space read mode or the manual mode.

Looking at this driver, all it is are APIs. Meaning another driver is 
needed to sit in between the MTD layer and this HW driver layer.

In the driver that I did, if the "RPC" HW is going to be used to control
a SPI Flash device, it registered a spi controller and then the MTD 
layer could access the device just like any other SPI controller driver. No
additional drivers are needed.

Looking at the hyperbus driver that is in drivers/mtd/hyperbus/, it 
seems that if the "RPC" HW is going to be used to control HyperFlash, then 
all you would need to do is register a hyperbus controller using 
hyperbus_register_device(). Then the MTD layer could read/write the flash using 
normal MTD CFI interface.

Why do you think you need another layer in between the HW driver and the
MTD layer?
Is your goal to make a multi-layered system where the HW jumps back and forth
in between operating modes at runtime? I'm not sure of the use case for all of
this.

Chris

Re: [PATCH RFC 0/2] Add Renesas RPC-IF support

[Sergei Shtylyov]

HEllo

On 12/11/2019 05:33 PM, Chris Brandt wrote:

>> Here's a set of 2 patches against Linus' repo. Renesas Reduced Pin Count
>> Interface (RPC-IF) allows a SPI flash or HyperFlash connected to the SoC to
>> be accessed via the external address space read mode or the manual mode.
> 
> Looking at this driver, all it is are APIs. Meaning another driver is 
> needed to sit in between the MTD layer and this HW driver layer.

   Between the hardware and SPI, and between the hardware and HyperFlash
infrastructure. There's a lot of the common hardware code common between
these 2 driver areas.

> In the driver that I did, if the "RPC" HW is going to be used to control
> a SPI Flash device, it registered a spi controller and then the MTD 
> layer could access the device just like any other SPI controller driver. No
> additional drivers are needed.

   We're already been thru that with Mason's patch -- I don't want the code
duplicated between 2 drivers.

> Looking at the hyperbus driver that is in drivers/mtd/hyperbus/, it 
> seems that if the "RPC" HW is going to be used to control HyperFlash, then 

   Sure. But the code controlling RPC hardware is largely the same b/w 2 cases.

> all you would need to do is register a hyperbus controller using 
> hyperbus_register_device(). Then the MTD layer could read/write the flash using 
> normal MTD CFI interface.

   That's what I do (the current realization makes too many assumptions about
the HF hardware (both direct read and write). 

> Why do you think you need another layer in between the HW driver and the
> MTD layer?

   Because we don't want any duplicated code. Also, think about DT -- it
describes the hardware, not the driver configuration.

> Is your goal to make a multi-layered system where the HW jumps back and forth
> in between operating modes at runtime? I'm not sure of the use case for all of
> this.

   My goal is to prevent the code duplication (and keep DT sane too).

> Chris

MBR, Sergei

Re: [PATCH RFC 0/2] Add Renesas RPC-IF support

[Sergei Shtylyov]

On 12/11/2019 05:33 PM, Chris Brandt wrote:

>> Here's a set of 2 patches against Linus' repo. Renesas Reduced Pin Count
>> Interface (RPC-IF) allows a SPI flash or HyperFlash connected to the SoC to
>> be accessed via the external address space read mode or the manual mode.
> 
> Looking at this driver, all it is are APIs. Meaning another driver is 
> needed to sit in between the MTD layer and this HW driver layer.
> 
> In the driver that I did, if the "RPC" HW is going to be used to control
> a SPI Flash device, it registered a spi controller and then the MTD 
> layer could access the device

   Via the SPI-to-MTD sublayer for (at least) direct mapping -- grep for "dirmap"
in drivers/mtd/spi-nor/spi-nor.c...

> just like any other SPI controller driver. No
> additional drivers are needed.

   Then why do we have *struct* spi_controller_mem_ops? Do All drivers implement
such ops?

[...]

MBR, Sergei