From: "Uwe Kleine-König" <ukleinek@kernel.org>
To: George Moussalem <george.moussalem@outlook.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Baruch Siach <baruch@tkos.co.il>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Devi Priya <quic_devipriy@quicinc.com>,
Baruch Siach <baruch.siach@siklu.com>
Subject: Re: [PATCH v20 2/6] pwm: driver for qualcomm ipq6018 pwm block
Date: Sat, 4 Apr 2026 23:09:26 +0200 [thread overview]
Message-ID: <adF9VdZYEGQfRqyl@monoceros> (raw)
In-Reply-To: <DS7PR19MB8883555F6B620250D1CB55689D5EA@DS7PR19MB8883.namprd19.prod.outlook.com>
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Hello George,
On Fri, Apr 03, 2026 at 12:40:32PM +0200, George Moussalem wrote:
> On 4/2/2026 5:35 PM, Uwe Kleine-König wrote:
> > diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c
> > index b944ecb456d5..4818d0170d53 100644
> > --- a/drivers/pwm/pwm-ipq.c
> > +++ b/drivers/pwm/pwm-ipq.c
> > @@ -97,9 +97,10 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > if (state->polarity != PWM_POLARITY_NORMAL)
> > return -EINVAL;
> >
> > - if (!ipq_chip->clk_rate)
> > - return -EINVAL;
> > -
> > + /*
> > + * XXX Why? A comment please. (Is this already covered by the checks
> > + * below?)
> > + */
>
> This check can be safely removed as it is indeed covered by the check
> where the period_ns is limited to IPQ_PWM_MAX_PERIOD_NS which equals to
> NSEC_PER_SEC as per macro definition above.
>
> > if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC,
> > ipq_chip->clk_rate))
> > return -ERANGE;
> > @@ -107,18 +108,29 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);
> > duty_ns = min(state->duty_cycle, period_ns);
> >
> > + /*
> > + * Pick the maximal value for PWM_DIV that still allows a
> > + * 100% relative duty cycle. This allows a fine grained
> > + * selection of duty cycles.
> > + */
> > pwm_div = IPQ_PWM_MAX_DIV - 1;
> > +
> > + /*
> > + * XXX mul_u64_u64_div_u64 returns an u64, this might overflow the
> > + * unsigned int pre_div.
> > + */
>
> Theoretically, yes, but in practice it won't due to above constraints.
> Take the max period of 10^9 (NSEC_PER_SEC) * max clock rate of 10^9 (1
> GHz), then the numerator becomes 10^18. Divide that by 10^9
> (NSEC_PER_SEC) * 65,535 (IPQ_PWM_MAX_DIV) and that fits well into a
> 32-bit integer.
OK, please put that in a comment.
> Do you want me to send a v21 or can you apply the diff in your tree with
> above deletion and comment?
Yes, please send a v21.
Best regards
Uwe
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next prev parent reply other threads:[~2026-04-04 21:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-04 11:25 [PATCH v20 0/6] Add PWM support for IPQ chipsets George Moussalem via B4 Relay
2026-02-04 11:25 ` [PATCH v20 1/6] dt-bindings: pwm: add IPQ6018 binding George Moussalem via B4 Relay
2026-02-04 11:25 ` [PATCH v20 2/6] pwm: driver for qualcomm ipq6018 pwm block George Moussalem via B4 Relay
2026-04-02 15:35 ` Uwe Kleine-König
2026-04-03 10:40 ` George Moussalem
2026-04-04 21:09 ` Uwe Kleine-König [this message]
2026-02-04 11:25 ` [PATCH v20 3/6] arm64: dts: qcom: ipq6018: add pwm node George Moussalem via B4 Relay
2026-02-04 12:24 ` Konrad Dybcio
2026-02-04 11:25 ` [PATCH v20 4/6] arm64: dts: qcom: ipq5018: " George Moussalem via B4 Relay
2026-02-04 12:25 ` Konrad Dybcio
2026-02-04 11:25 ` [PATCH v20 5/6] arm64: dts: qcom: ipq5332: " George Moussalem via B4 Relay
2026-02-04 12:25 ` Konrad Dybcio
2026-02-04 11:25 ` [PATCH v20 6/6] arm64: dts: qcom: ipq9574: " George Moussalem via B4 Relay
2026-02-04 12:26 ` Konrad Dybcio
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