Re: [PATCH 2/3] pinctrl: qcom: add the TLMM driver for the Nord platforms

[Bjorn Andersson <andersson@kernel.org>]

On Fri, Apr 03, 2026 at 03:27:56PM +0200, Bartosz Golaszewski wrote:
[..]
> diff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c
[..]
> +enum nord_functions {
> +	msm_mux_gpio,
> +	msm_mux_aoss_cti,
> +	msm_mux_atest_char0,
> +	msm_mux_atest_char1,
> +	msm_mux_atest_char2,
> +	msm_mux_atest_char3,
> +	msm_mux_atest_char_start,
> +	msm_mux_atest_usb20,
> +	msm_mux_atest_usb21,
> +	msm_mux_aud_intfc0_clk,
> +	msm_mux_aud_intfc0_data0,
> +	msm_mux_aud_intfc0_data1,
> +	msm_mux_aud_intfc0_data2,
> +	msm_mux_aud_intfc0_data3,
> +	msm_mux_aud_intfc0_data4,
> +	msm_mux_aud_intfc0_data5,
> +	msm_mux_aud_intfc0_data6,
> +	msm_mux_aud_intfc0_data7,

Keeping functions like this split per pin forces the DT author to
write per-pin states. We avoid this by dropping/adjusting the function
suffix.

The only case where we want to see a suffix for a given endpoint is when
it's necessary to allow us to select some secondary function of that pin
(e.g. we've seen QUP SE instances that spread their 4 pins pair-wise
across only two pins, with two different functions).

[..]
> +	msm_mux_qup3_se0_l0_mira,
> +	msm_mux_qup3_se0_l0_mirb,
> +	msm_mux_qup3_se0_l1_mira,
> +	msm_mux_qup3_se0_l1_mirb,

Here's such example, where the first two pins of qup3_se0 have two
different mappings on gpio 102/103 (for some reason). So, we somehow
need two functions for these.

> +	msm_mux_qup3_se0_l2,
> +	msm_mux_qup3_se0_l3,
> +	msm_mux_qup3_se0_l4,
> +	msm_mux_qup3_se0_l5,
> +	msm_mux_qup3_se0_l6,

But in order to select qup3_se0 muxing on pins 102-108 the DT author
need to write 6 different pinctrl states; where 1-2 should suffice.

[..]
> +static const struct msm_pingroup nord_groups[] = {
[..]
> +	[102] = PINGROUP(102, qspi0, qup3_se0_l0_mira, qup3_se0_l1_mirb, _, _, _, _, _, _, _, _),
> +	[103] = PINGROUP(103, qspi1, qup3_se0_l1_mira, qup3_se0_l0_mirb, _, _, _, _, _, _, _, _),
> +	[104] = PINGROUP(104, qspi_clk, qup3_se0_l2, _, _, _, _, _, _, _, _, _),
> +	[105] = PINGROUP(105, qspi_cs0_n, qup3_se0_l3, gcc_gp5_clk, _, _, _, _, _, _, _, _),
> +	[106] = PINGROUP(106, qspi2, qup3_se0_l4, gcc_gp6_clk, _, _, _, _, _, _, _, _),
> +	[107] = PINGROUP(107, qspi3, qup3_se0_l5, _, _, _, _, _, _, _, _, _),
> +	[108] = PINGROUP(108, qspi_cs1_n, qup3_se0_l6, qdss_gpio, _, _, _, _, _, _, _, _),

Regards,
Bjorn