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Tue, 07 Apr 2026 12:58:15 -0700 (PDT) Received: from redhat.com ([2600:382:772d:3619:ed0:4a9c:acd6:3fc9]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8d2a8648c17sm1388436585a.33.2026.04.07.12.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Apr 2026 12:58:14 -0700 (PDT) Date: Tue, 7 Apr 2026 15:58:12 -0400 From: Brian Masney To: Marek Vasut Cc: linux-clk@vger.kernel.org, Peng Fan , Conor Dooley , Krzysztof Kozlowski , Michael Turquette , Michael Walle , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/6] clk: fsl-sai: Add i.MX8M support with 8 byte register offset Message-ID: References: <20260406215150.176599-1-marex@nabladev.com> <20260406215150.176599-2-marex@nabladev.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260406215150.176599-2-marex@nabladev.com> User-Agent: Mutt/2.3.0 (2026-01-25) Hi Marek, On Mon, Apr 06, 2026 at 11:49:42PM +0200, Marek Vasut wrote: > The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers > shifted by +8 bytes and requires additional bus clock. Add support for > the i.MX8M variant of the IP with this register shift and additional > clock. > > Reviewed-by: Brian Masney > Reviewed-by: Peng Fan > Signed-off-by: Marek Vasut > --- > Cc: Brian Masney > Cc: Conor Dooley > Cc: Krzysztof Kozlowski > Cc: Michael Turquette > Cc: Michael Walle > Cc: Rob Herring > Cc: Stephen Boyd > Cc: devicetree@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > --- > V2: Update commit message, align it with the bindings one > V3: - Rebase on current next, update mail address > - Pick ancient RB from Peng, although this may be outdated > https://patchwork.kernel.org/project/alsa-devel/patch/20241226162234.40141-2-marex@denx.de/ > - Optionally enable "bus" clock, which are needed on MX8M to operate > register file > V4: Add RB from Brian > --- > drivers/clk/Kconfig | 2 +- > drivers/clk/clk-fsl-sai.c | 27 +++++++++++++++++++++++---- > 2 files changed, 24 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index cc8743b11bb1f..9f7f391a5615a 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -255,7 +255,7 @@ config COMMON_CLK_FSL_FLEXSPI > > config COMMON_CLK_FSL_SAI > bool "Clock driver for BCLK of Freescale SAI cores" > - depends on ARCH_LAYERSCAPE || COMPILE_TEST > + depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST > help > This driver supports the Freescale SAI (Synchronous Audio Interface) > to be used as a generic clock output. Some SoCs have restrictions > diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c > index cba45e07562da..336aa8477d0ea 100644 > --- a/drivers/clk/clk-fsl-sai.c > +++ b/drivers/clk/clk-fsl-sai.c > @@ -26,11 +26,17 @@ struct fsl_sai_clk { > spinlock_t lock; > }; > > +struct fsl_sai_data { > + unsigned int offset; /* Register offset */ > +}; > + > static int fsl_sai_clk_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > + const struct fsl_sai_data *data = device_get_match_data(dev); > struct fsl_sai_clk *sai_clk; > struct clk_parent_data pdata = { .index = 0 }; > + struct clk *clk_bus; > void __iomem *base; > struct clk_hw *hw; > > @@ -42,19 +48,23 @@ static int fsl_sai_clk_probe(struct platform_device *pdev) > if (IS_ERR(base)) > return PTR_ERR(base); > > + clk_bus = devm_clk_get_optional_enabled(dev, "bus"); This patch needs to include and drop it from patch 6 to keep bisectability. Brian