From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Stephen Boyd <swboyd@chromium.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org
Subject: Re: [PATCH v3 3/6] arm64: dts: qcom: sm8350: move more nodes to correct place
Date: Fri, 10 Feb 2023 12:03:59 +0100 [thread overview]
Message-ID: <addce6b1-1d3c-9094-b6e6-c060b0d0435a@linaro.org> (raw)
In-Reply-To: <20230209133839.762631-4-dmitry.baryshkov@linaro.org>
On 9.02.2023 14:38, Dmitry Baryshkov wrote:
> Continue ordering DT nodes by their address. Move RNG, UFS, system NoC
> and SLPI nodes to the proper position.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +++++++++++++--------------
> 1 file changed, 157 insertions(+), 157 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index b85bd8fd28c0..8bf38d350521 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -1421,6 +1421,13 @@ spi13: spi@a94000 {
> };
> };
>
> + rng: rng@10d3000 {
> + compatible = "qcom,prng-ee";
> + reg = <0 0x010d3000 0 0x1000>;
> + clocks = <&rpmhcc RPMH_HWKM_CLK>;
> + clock-names = "core";
> + };
> +
> config_noc: interconnect@1500000 {
> compatible = "qcom,sm8350-config-noc";
> reg = <0 0x01500000 0 0xa580>;
> @@ -1641,18 +1648,76 @@ pcie1_phy: phy@1c0f000 {
> status = "disabled";
> };
>
> - lpass_ag_noc: interconnect@3c40000 {
> - compatible = "qcom,sm8350-lpass-ag-noc";
> - reg = <0 0x03c40000 0 0xf080>;
> - #interconnect-cells = <2>;
> - qcom,bcm-voters = <&apps_bcm_voter>;
> + ufs_mem_hc: ufshc@1d84000 {
> + compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0 0x01d84000 0 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy_lanes>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <2>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc UFS_PHY_GDSC>;
> +
> + iommus = <&apps_smmu 0xe0 0x0>;
> +
> + clock-names =
> + "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + clocks =
> + <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + freq-table-hz =
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <75000000 300000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> + status = "disabled";
> };
>
> - compute_noc: interconnect@a0c0000 {
> - compatible = "qcom,sm8350-compute-noc";
> - reg = <0 0x0a0c0000 0 0xa180>;
> - #interconnect-cells = <2>;
> - qcom,bcm-voters = <&apps_bcm_voter>;
> + ufs_mem_phy: phy@1d87000 {
> + compatible = "qcom,sm8350-qmp-ufs-phy";
> + reg = <0 0x01d87000 0 0x1c4>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + clock-names = "ref",
> + "ref_aux";
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> + status = "disabled";
> +
> + ufs_mem_phy_lanes: phy@1d87400 {
> + reg = <0 0x01d87400 0 0x188>,
> + <0 0x01d87600 0 0x200>,
> + <0 0x01d87c00 0 0x200>,
> + <0 0x01d87800 0 0x188>,
> + <0 0x01d87a00 0 0x200>;
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> + };
> };
>
> ipa: ipa@1e40000 {
> @@ -1700,6 +1765,13 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + lpass_ag_noc: interconnect@3c40000 {
> + compatible = "qcom,sm8350-lpass-ag-noc";
> + reg = <0 0x03c40000 0 0xf080>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> mpss: remoteproc@4080000 {
> compatible = "qcom,sm8350-mpss-pas";
> reg = <0x0 0x04080000 0x0 0x4040>;
> @@ -1742,6 +1814,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
> };
> };
>
> + slpi: remoteproc@5c00000 {
> + compatible = "qcom,sm8350-slpi-pas";
> + reg = <0 0x05c00000 0 0x4000>;
> +
> + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
> + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd SM8350_LCX>,
> + <&rpmhpd SM8350_LMX>;
> + power-domain-names = "lcx", "lmx";
> +
> + memory-region = <&pil_slpi_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&smp2p_slpi_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_SLPI
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + label = "slpi";
> + qcom,remote-pid = <3>;
> +
> + fastrpc {
> + compatible = "qcom,fastrpc";
> + qcom,glink-channels = "fastrpcglink-apps-dsp";
> + label = "sdsp";
> + qcom,non-secure-domain;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + compute-cb@1 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <1>;
> + iommus = <&apps_smmu 0x0541 0x0>;
> + };
> +
> + compute-cb@2 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <2>;
> + iommus = <&apps_smmu 0x0542 0x0>;
> + };
> +
> + compute-cb@3 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <3>;
> + iommus = <&apps_smmu 0x0543 0x0>;
> + /* note: shared-cb = <4> in downstream */
> + };
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8350-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> @@ -2012,153 +2152,6 @@ qup_i2c19_default: qup-i2c19-default-state {
> };
> };
>
> - rng: rng@10d3000 {
> - compatible = "qcom,prng-ee";
> - reg = <0 0x010d3000 0 0x1000>;
> - clocks = <&rpmhcc RPMH_HWKM_CLK>;
> - clock-names = "core";
> - };
> -
> - ufs_mem_hc: ufshc@1d84000 {
> - compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
> - "jedec,ufs-2.0";
> - reg = <0 0x01d84000 0 0x3000>;
> - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> - phys = <&ufs_mem_phy_lanes>;
> - phy-names = "ufsphy";
> - lanes-per-direction = <2>;
> - #reset-cells = <1>;
> - resets = <&gcc GCC_UFS_PHY_BCR>;
> - reset-names = "rst";
> -
> - power-domains = <&gcc UFS_PHY_GDSC>;
> -
> - iommus = <&apps_smmu 0xe0 0x0>;
> -
> - clock-names =
> - "core_clk",
> - "bus_aggr_clk",
> - "iface_clk",
> - "core_clk_unipro",
> - "ref_clk",
> - "tx_lane0_sync_clk",
> - "rx_lane0_sync_clk",
> - "rx_lane1_sync_clk";
> - clocks =
> - <&gcc GCC_UFS_PHY_AXI_CLK>,
> - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> - <&gcc GCC_UFS_PHY_AHB_CLK>,
> - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> - <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> - freq-table-hz =
> - <75000000 300000000>,
> - <0 0>,
> - <0 0>,
> - <75000000 300000000>,
> - <0 0>,
> - <0 0>,
> - <0 0>,
> - <0 0>;
> - status = "disabled";
> - };
> -
> - ufs_mem_phy: phy@1d87000 {
> - compatible = "qcom,sm8350-qmp-ufs-phy";
> - reg = <0 0x01d87000 0 0x1c4>;
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> - clock-names = "ref",
> - "ref_aux";
> - clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> -
> - resets = <&ufs_mem_hc 0>;
> - reset-names = "ufsphy";
> - status = "disabled";
> -
> - ufs_mem_phy_lanes: phy@1d87400 {
> - reg = <0 0x01d87400 0 0x188>,
> - <0 0x01d87600 0 0x200>,
> - <0 0x01d87c00 0 0x200>,
> - <0 0x01d87800 0 0x188>,
> - <0 0x01d87a00 0 0x200>;
> - #clock-cells = <1>;
> - #phy-cells = <0>;
> - };
> - };
> -
> - slpi: remoteproc@5c00000 {
> - compatible = "qcom,sm8350-slpi-pas";
> - reg = <0 0x05c00000 0 0x4000>;
> -
> - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
> - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
> - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
> - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
> - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
> - interrupt-names = "wdog", "fatal", "ready",
> - "handover", "stop-ack";
> -
> - clocks = <&rpmhcc RPMH_CXO_CLK>;
> - clock-names = "xo";
> -
> - power-domains = <&rpmhpd SM8350_LCX>,
> - <&rpmhpd SM8350_LMX>;
> - power-domain-names = "lcx", "lmx";
> -
> - memory-region = <&pil_slpi_mem>;
> -
> - qcom,qmp = <&aoss_qmp>;
> -
> - qcom,smem-states = <&smp2p_slpi_out 0>;
> - qcom,smem-state-names = "stop";
> -
> - status = "disabled";
> -
> - glink-edge {
> - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
> - IPCC_MPROC_SIGNAL_GLINK_QMP
> - IRQ_TYPE_EDGE_RISING>;
> - mboxes = <&ipcc IPCC_CLIENT_SLPI
> - IPCC_MPROC_SIGNAL_GLINK_QMP>;
> -
> - label = "slpi";
> - qcom,remote-pid = <3>;
> -
> - fastrpc {
> - compatible = "qcom,fastrpc";
> - qcom,glink-channels = "fastrpcglink-apps-dsp";
> - label = "sdsp";
> - qcom,non-secure-domain;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - compute-cb@1 {
> - compatible = "qcom,fastrpc-compute-cb";
> - reg = <1>;
> - iommus = <&apps_smmu 0x0541 0x0>;
> - };
> -
> - compute-cb@2 {
> - compatible = "qcom,fastrpc-compute-cb";
> - reg = <2>;
> - iommus = <&apps_smmu 0x0542 0x0>;
> - };
> -
> - compute-cb@3 {
> - compatible = "qcom,fastrpc-compute-cb";
> - reg = <3>;
> - iommus = <&apps_smmu 0x0543 0x0>;
> - /* note: shared-cb = <4> in downstream */
> - };
> - };
> - };
> - };
> -
> sdhc_2: mmc@8804000 {
> compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
> reg = <0 0x08804000 0 0x1000>;
> @@ -2307,6 +2300,13 @@ system-cache-controller@9200000 {
> reg-names = "llcc_base", "llcc_broadcast_base";
> };
>
> + compute_noc: interconnect@a0c0000 {
> + compatible = "qcom,sm8350-compute-noc";
> + reg = <0 0x0a0c0000 0 0xa180>;
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> usb_1: usb@a6f8800 {
> compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
> reg = <0 0x0a6f8800 0 0x400>;
next prev parent reply other threads:[~2023-02-10 11:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-09 13:38 [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 1/6] dt-bindings: display/msm/gmu: add Adreno 660 support Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 2/6] arm64: dts: qcom: sm8350: reorder device nodes Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 3/6] arm64: dts: qcom: sm8350: move more nodes to correct place Dmitry Baryshkov
2023-02-10 11:03 ` Konrad Dybcio [this message]
2023-02-09 13:38 ` [PATCH v3 4/6] arm64: dts: qcom: sm8350: finish reordering nodes Dmitry Baryshkov
2023-02-10 11:09 ` Konrad Dybcio
2023-02-10 11:12 ` Dmitry Baryshkov
2023-02-10 11:13 ` Konrad Dybcio
2023-02-09 13:38 ` [PATCH v3 5/6] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes Dmitry Baryshkov
2023-02-10 11:10 ` Konrad Dybcio
2023-02-10 11:14 ` Dmitry Baryshkov
2023-02-09 13:38 ` [PATCH v3 6/6] arm64: dts: qcom: sm8350-hdk: enable GPU Dmitry Baryshkov
2023-02-10 8:29 ` [PATCH v3 0/6] arm64: dts: qcom: sm8350: enable GPU on the HDK board Neil Armstrong
2023-02-10 10:32 ` Dmitry Baryshkov
2023-02-10 11:06 ` neil.armstrong
2023-02-13 22:23 ` Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=addce6b1-1d3c-9094-b6e6-c060b0d0435a@linaro.org \
--to=konrad.dybcio@linaro.org \
--cc=agross@kernel.org \
--cc=airlied@gmail.com \
--cc=andersson@kernel.org \
--cc=daniel@ffwll.ch \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=quic_abhinavk@quicinc.com \
--cc=robdclark@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sean@poorly.run \
--cc=swboyd@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).