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Wysocki" , Robert Moore , Len Brown , Guenter Roeck , Philipp Zabel , Eric Biggers , Sakari Ailus , Wolfram Sang , Miquel Raynal , linux-i3c@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, linux-hwmon@vger.kernel.org Subject: Re: [PATCH v2 09/13] i3c: dw-i3c-master: Add a quirk to skip clock and reset Message-ID: References: <20260409105747.48158-1-akhilrajeev@nvidia.com> <20260409105747.48158-10-akhilrajeev@nvidia.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260409105747.48158-10-akhilrajeev@nvidia.com> X-ClientProxiedBy: BY5PR04CA0002.namprd04.prod.outlook.com (2603:10b6:a03:1d0::12) To PA4PR04MB9366.eurprd04.prod.outlook.com (2603:10a6:102:2a9::8) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9366:EE_|AM7PR04MB6952:EE_ X-MS-Office365-Filtering-Correlation-Id: 6fba2a9f-f7a7-4898-c3ab-08de96ab3461 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|19092799006|52116014|376014|7416014|38350700014|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?5oBg7IksiezJ1hbcYYGIOJaImDOaJLRrANxOwn01uy0yVjPXcjg25gCNl67i?= =?us-ascii?Q?6uAJ+IVpHeRLY1VUMfXV95gWXYN55IQl9uoDfevsrNHq1L6+LktMlcbaXYGG?= =?us-ascii?Q?nRKP+swL79uRmZDGQBvMyXKuxrInM7NtPgdfqdsBziP/3EeuUP9LvzGpLJBW?= =?us-ascii?Q?rLV20JFQU7rWQKAQ3pl8ysga6rLX8+HkGs+qIKPAluWv0hqmXyarqjsT08GP?= =?us-ascii?Q?T3TxX+HoWqFVzohf5vBx0j7Nb9cEJvL62SKNKHAPMh+cVpr10sHgkDFhMtmj?= =?us-ascii?Q?wp/DjKitfAEdba0vGZa2iPVO2zGdJke+JPtc9hY1H0k1c2Y0Ba8yxLwCqk6v?= =?us-ascii?Q?6cE1GTI5PJImmklD55ggGP2mfrH3uWbCGXR+FfQjhr4IjcnVL4ssKgKHBDeX?= =?us-ascii?Q?avn2zDaJndagTtPQdFcopTzf6V1l445spiQV8ciVxn3jz7cPllaH4LFtf336?= =?us-ascii?Q?YEe5NiGJCN7SP5OmphmYxT7F4INq7ym2yjTPIWlTQcYWVoF0KEUYYipGdMYZ?= =?us-ascii?Q?ynT1ixIGgn28pJpHQg3dBlox4HhzzXXN9jn/af0Pn6HMiaxrTZfpxlYV2hgK?= =?us-ascii?Q?4eZhwposQwsL5UNRAHj7NuyWS6yp8CJmlaq3Dtpn9n++DneBfGzl9YYe4kf+?= =?us-ascii?Q?cBfGB1opwE96eHaCNFEjhbdn7I2R5IfYD9/IG24jtXtuyQ05xvcCIrVDNgaT?= =?us-ascii?Q?KnB43Sgf7EhB1Xf2h8BYJooWm3i1UEmhVEWvJepfi+EfNjHp2KUUWbyhJUmU?= =?us-ascii?Q?syRWFxjIxECv2LblzYppm8u8Rsz8cjarkTdZIyyD4zzCPXCIq8ykZthBTDUd?= =?us-ascii?Q?Ia/MenOXqEIXr0fvOX41ttGP8m7A4866N6uS+sWF6pmycqiOB+5RXCPGrMrH?= =?us-ascii?Q?/B6crWnf4AtYattaVpLSXmo0b5zgw9bW8Pk6EMcMDBM5KzFNW5HNVgL5Ahu1?= =?us-ascii?Q?+jAQymeDzMB2v5O0GdCQVOja9XhUu2g7e4YQDngfxdBm/my3SeFXGvX6RqtF?= =?us-ascii?Q?2imuh4txWCBsfTe/c2hdgN8euLOueXAl0+3g5j1X7MufA7Hodw2ddKu12ZOl?= =?us-ascii?Q?1Mt2cQxVM3HbJf9ZW4cjHLiS8lfiyfwPcIH+5M9DLOx7DBQTUdLzqWf6UpfR?= =?us-ascii?Q?rIeP1TWKvzxLYhSX/nUeTMT71bpm4Kq73KSucU5usCWxQgBe4nCjwZOJYxG0?= =?us-ascii?Q?BlciZoCbcVj7dfut0vOOYL3gFtDGVYTAp9rqcmOC8E5q7FdgzR7WN4+5DPbd?= =?us-ascii?Q?k5ftZotpkMYDsWXTdH9ZAcPp7QOgYNf+XXk5/JUNYbr7SMqW5W7QNdLvtFdZ?= =?us-ascii?Q?8UiB8erag9nh75bdhCJNB55fqJC2u5SiXK49QjJ4lvhvu6RuEu1hJsJGd1qA?= =?us-ascii?Q?dwWUYen/SbmEuZy/y2qUtWmRf7Ug1OALw4BJxhPLS59yU1iwh3tZozQzZ/S7?= =?us-ascii?Q?NluFP4KoELcRePrO7gpzlqSJfYxUSEkLGUEAcyDazI4rVapoOyG2acKDslp2?= =?us-ascii?Q?MMr/xftIjJKjY3Ew6uazdBWDhj4PmEwbC7u7ijR7pPkAmSnSE9FyBmy7xsbU?= =?us-ascii?Q?PSmRb9MBjVKMsY1vLjeQpxrjOHBnWPFeDsSe29wmnMU6aleZ1Zjbb09ELPii?= =?us-ascii?Q?IGUeSAj1IY/nGMwGiiG5FDXLtze0u1wO7n97zG1vUMtDsJRuc92ngifeAwiI?= =?us-ascii?Q?xbp9X2TdoCFyd8XZy8SMx7GFprPCAINU1oEWkstL+OQni/uduQqIgo2tQ5qD?= =?us-ascii?Q?Qk/dRRVe5A=3D=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6fba2a9f-f7a7-4898-c3ab-08de96ab3461 X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9366.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 02:45:19.7694 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: aWfVVYVHeiUoSxQAp6uHqOZ8cqGtxuhefFqG/kje1xx88CnF5q1HBmX8s71b7oaxoBEvs2egfWzuxFHUQGVg4w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR04MB6952 On Thu, Apr 09, 2026 at 04:27:39PM +0530, Akhil R wrote: > Some ACPI-enumerated devices like Tegra410 do not have clock and reset > resources exposed via the clk/reset frameworks. Add a match data for why not export fix clock at ACPI? > such devices to skip acquiring clock and reset controls during probe. > > Move match data parsing before clock/reset acquisition so the quirk is > available early enough. When the quirk is set, fall back to reading > the clock rate from the "clock-frequency" device property instead. "clock-frequency" is legacy proptery. Frank > > Signed-off-by: Akhil R > --- > drivers/i3c/master/dw-i3c-master.c | 60 +++++++++++++++++++----------- > 1 file changed, 39 insertions(+), 21 deletions(-) > > diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c > index 05ccdf177b6d..a62eec6d2ac0 100644 > --- a/drivers/i3c/master/dw-i3c-master.c > +++ b/drivers/i3c/master/dw-i3c-master.c > @@ -241,6 +241,7 @@ > /* List of quirks */ > #define AMD_I3C_OD_PP_TIMING BIT(1) > #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2) > +#define DW_I3C_ACPI_SKIP_CLK_RST BIT(3) > > struct dw_i3c_cmd { > u32 cmd_lo; > @@ -560,13 +561,26 @@ static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) > writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); > } > > +static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *master) > +{ > + unsigned int core_rate_prop; > + > + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) > + return clk_get_rate(master->core_clk); > + > + if (device_property_read_u32(master->dev, "clock-frequency", &core_rate_prop)) > + return 0; > + > + return core_rate_prop; > +} > + > static int dw_i3c_clk_cfg(struct dw_i3c_master *master) > { > unsigned long core_rate, core_period; > u32 scl_timing; > u8 hcnt, lcnt; > > - core_rate = clk_get_rate(master->core_clk); > + core_rate = dw_i3c_master_get_core_rate(master); > if (!core_rate) > return -EINVAL; > > @@ -619,7 +633,7 @@ static int dw_i2c_clk_cfg(struct dw_i3c_master *master) > u16 hcnt, lcnt; > u32 scl_timing; > > - core_rate = clk_get_rate(master->core_clk); > + core_rate = dw_i3c_master_get_core_rate(master); > if (!core_rate) > return -EINVAL; > > @@ -1600,21 +1614,34 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, > if (IS_ERR(master->regs)) > return PTR_ERR(master->regs); > > - master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL); > - if (IS_ERR(master->core_clk)) > - return PTR_ERR(master->core_clk); > + if (has_acpi_companion(&pdev->dev)) { > + quirks = (unsigned long)device_get_match_data(&pdev->dev); > + } else if (pdev->dev.of_node) { > + drvdata = device_get_match_data(&pdev->dev); > + if (drvdata) > + quirks = drvdata->flags; > + } > + master->quirks = quirks; > + > + if (master->quirks & DW_I3C_ACPI_SKIP_CLK_RST) { > + master->core_clk = NULL; > + master->core_rst = NULL; > + } else { > + master->core_clk = devm_clk_get_enabled(&pdev->dev, NULL); > + if (IS_ERR(master->core_clk)) > + return PTR_ERR(master->core_clk); > + > + master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, > + "core_rst"); > + if (IS_ERR(master->core_rst)) > + return PTR_ERR(master->core_rst); > + reset_control_deassert(master->core_rst); > + } > > master->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk"); > if (IS_ERR(master->pclk)) > return PTR_ERR(master->pclk); > > - master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, > - "core_rst"); > - if (IS_ERR(master->core_rst)) > - return PTR_ERR(master->core_rst); > - > - reset_control_deassert(master->core_rst); > - > spin_lock_init(&master->xferqueue.lock); > INIT_LIST_HEAD(&master->xferqueue.list); > > @@ -1647,15 +1674,6 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, > master->maxdevs = ret >> 16; > master->free_pos = GENMASK(master->maxdevs - 1, 0); > > - if (has_acpi_companion(&pdev->dev)) { > - quirks = (unsigned long)device_get_match_data(&pdev->dev); > - } else if (pdev->dev.of_node) { > - drvdata = device_get_match_data(&pdev->dev); > - if (drvdata) > - quirks = drvdata->flags; > - } > - master->quirks = quirks; > - > /* Keep controller enabled by preventing runtime suspend */ > if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK) > pm_runtime_get_noresume(&pdev->dev); > -- > 2.50.1 >