[PATCH RFC v2 0/5] Add support for MBG Thermal monitoring device

[PATCH RFC v2 0/5] Add support for MBG Thermal monitoring device

[Satya Priya Kakitapalli]

Add bindings, driver and DT for the Qualcomm's MBG thermal
monitoring device.

Please note that this series is dependent on [1] which adds
ADC5-GEN3 support.

[1] https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
Satya Priya Kakitapalli (5):
      dt-bindings: thermal: Add MBG thermal monitor support
      dt-bindings: mfd: qcom,spmi-pmic: Add MBG thermal monitor ref
      thermal: qcom: Add support for MBG thermal monitoring
      arm64: dts: qcom: sa8775p-pmics: Add vadc support on SA8775P
      arm64: dts: qcom: sa8775p-pmics: Add support for MBG TM

 .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml    |   4 +
 .../bindings/thermal/qcom-spmi-mbg-tm.yaml         |  86 ++++++++
 arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi        | 210 ++++++++++++++++++
 drivers/thermal/qcom/Kconfig                       |  11 +
 drivers/thermal/qcom/Makefile                      |   1 +
 drivers/thermal/qcom/qcom-spmi-mbg-tm.c            | 245 +++++++++++++++++++++
 .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h           |  41 ++++
 7 files changed, 598 insertions(+)
---
base-commit: b4ba0e91c6f0de7bebe1b9d209bebe9bd56daa42
change-id: 20241209-mbg-v2-support-63df41a40d53
prerequisite-message-id: <c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com>
prerequisite-patch-id: b4aee2e3887f478bdb7ef86519d4e2233a7e8600
prerequisite-patch-id: f1a62cf8dff80669a7b2cac238a033e92853ad38
prerequisite-patch-id: bc6d5a0b2448ed92c77ba0b13fb211ee605b58c7
prerequisite-patch-id: 80bfefa75a9ee0440cc6ad195e424e71bf3c91e9

Best regards,
-- 
Satya Priya Kakitapalli <quic_skakitap@quicinc.com>

[PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Satya Priya Kakitapalli]

Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp
alarm peripheral found on PM8775 pmic.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 .../bindings/thermal/qcom-spmi-mbg-tm.yaml         | 86 ++++++++++++++++++++++
 .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h           | 41 +++++++++++
 2 files changed, 127 insertions(+)

diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..909373eb758e4a8b7c2bbd0022c56ab2e823ca13
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom-spmi-mbg-tm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SPMI PMIC MBG Thermal Monitoring
+
+maintainers:
+  - Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
+
+description:
+  Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die
+  temperature and generates an interrupt if the PMIC die temperature is
+  over a set of programmable temperature thresholds. It allows monitoring
+  for both hot and cold, LVL1 and LVL2 thresholds, which makes it different
+  from the existing temp alarm peripheral. The interrupt comes over SPMI
+  and the MBG's fault status register gives details to understand whether
+  it is a hot/cold and LVL1/LVL2 violation.
+
+allOf:
+  - $ref: thermal-sensor.yaml#
+
+properties:
+  compatible:
+    const: qcom,spmi-pm8775-mbg-tm
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  io-channels:
+    items:
+      - description: ADC channel, which reports chip die temperature.
+
+  io-channel-names:
+    const: thermal
+
+  "#thermal-sensor-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - io-channels
+  - io-channel-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h>
+
+    pmic {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        pmm8654au_0_tz: temperature-sensor@d700 {
+            compatible = "qcom,spmi-pm8775-mbg-tm";
+            reg = <0xd700>;
+            interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+            io-channels = <&pm8775_1_adc PM8775_ADC5_GEN3_DIE_TEMP(1)>;
+            io-channel-names = "thermal";
+            #thermal-sensor-cells = <0>;
+        };
+    };
+
+    thermal-zones {
+        pm8775-mbg0-thermal {
+            polling-delay-passive = <100>;
+            thermal-sensors = <&pmm8654au_0_tz>;
+
+            trips {
+                trip0 {
+                  temperature = <115000>;
+                  hysteresis = <5000>;
+                  type = "passive";
+                };
+            };
+        };
+    };
+...
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h
new file mode 100644
index 0000000000000000000000000000000000000000..33f5454367777b10fda248476a0abd17da86ecf6
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+#define PM8775_ADC5_GEN3_REF_GND(sid)			((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8775_ADC5_GEN3_1P25VREF(sid)			((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8775_ADC5_GEN3_VREF_VADC(sid)			((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8775_ADC5_GEN3_DIE_TEMP(sid)			((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8775_ADC5_GEN3_AMUX1_THM(sid)			((sid) << 8 | ADC5_GEN3_AMUX1_THM)
+#define PM8775_ADC5_GEN3_AMUX2_THM(sid)			((sid) << 8 | ADC5_GEN3_AMUX2_THM)
+#define PM8775_ADC5_GEN3_AMUX3_THM(sid)			((sid) << 8 | ADC5_GEN3_AMUX3_THM)
+#define PM8775_ADC5_GEN3_AMUX4_THM(sid)			((sid) << 8 | ADC5_GEN3_AMUX4_THM)
+#define PM8775_ADC5_GEN3_AMUX5_THM(sid)			((sid) << 8 | ADC5_GEN3_AMUX5_THM)
+#define PM8775_ADC5_GEN3_AMUX6_THM(sid)			((sid) << 8 | ADC5_GEN3_AMUX6_THM)
+#define PM8775_ADC5_GEN3_AMUX1_GPIO9(sid)		((sid) << 8 | ADC5_GEN3_AMUX1_GPIO)
+#define PM8775_ADC5_GEN3_AMUX2_GPIO10(sid)		((sid) << 8 | ADC5_GEN3_AMUX2_GPIO)
+#define PM8775_ADC5_GEN3_AMUX3_GPIO11(sid)		((sid) << 8 | ADC5_GEN3_AMUX3_GPIO)
+#define PM8775_ADC5_GEN3_AMUX4_GPIO12(sid)		((sid) << 8 | ADC5_GEN3_AMUX4_GPIO)
+
+/* 100k pull-up2 */
+#define PM8775_ADC5_GEN3_AMUX1_THM_100K_PU(sid)		((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX2_THM_100K_PU(sid)		((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX3_THM_100K_PU(sid)		((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX4_THM_100K_PU(sid)		((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX5_THM_100K_PU(sid)		((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX6_THM_100K_PU(sid)		((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX1_GPIO9_100K_PU(sid)	((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX2_GPIO10_100K_PU(sid)	((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX3_GPIO11_100K_PU(sid)	((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
+#define PM8775_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid)	((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
+
+#define PM8775_ADC5_GEN3_VPH_PWR(sid)			((sid) << 8 | ADC5_GEN3_VPH_PWR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */

-- 
2.25.1

[PATCH RFC v2 2/5] dt-bindings: mfd: qcom,spmi-pmic: Add MBG thermal monitor ref

[Satya Priya Kakitapalli]

Add reference to the newly added MBG thermal monitor bindings.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index 11da55644262fada1bcd215943078330332156aa..3a1acb658960329e881d67e264d221764bcec57e 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -209,6 +209,10 @@ patternProperties:
     $ref: /schemas/leds/backlight/qcom-wled.yaml#
     unevaluatedProperties: false
 
+  "temperature-sensor@[0-9a-f]+$":
+    type: object
+    $ref: /schemas/thermal/qcom-spmi-mbg-tm.yaml#
+
 required:
   - compatible
   - reg

-- 
2.25.1

[PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring

[Satya Priya Kakitapalli]

Add driver for the MBG thermal monitoring device. It monitors
the die temperature, and when there is a level 1 upper threshold
violation, it receives an interrupt over spmi. The driver reads
the fault status register and notifies thermal accordingly.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 drivers/thermal/qcom/Kconfig            |  11 ++
 drivers/thermal/qcom/Makefile           |   1 +
 drivers/thermal/qcom/qcom-spmi-mbg-tm.c | 245 ++++++++++++++++++++++++++++++++
 3 files changed, 257 insertions(+)

diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig
index f9876fb8606dd05022bd5ace56a0804f5a8cbfce..2ddfb6228edc7369355d9091fba3b1c130cad459 100644
--- a/drivers/thermal/qcom/Kconfig
+++ b/drivers/thermal/qcom/Kconfig
@@ -32,6 +32,17 @@ config QCOM_SPMI_ADC_TM5_GEN3
 	  Thermal client sets threshold temperature for both warm and cool and
 	  gets updated when a threshold is reached.
 
+config QCOM_SPMI_MBG_TM
+	tristate "Qualcomm Technologies, Inc. SPMI PMIC MBG Temperature monitor"
+	depends on QCOM_SPMI_ADC5_GEN3
+	select REGMAP_SPMI
+	help
+	 This enables a thermal driver for the MBG thermal monitoring device.
+	 It shows up in sysfs as a thermal sensor with single trip point.
+	 It notifies the thermal framework when this trip is violated. The
+	 temperature reported by the thermal sensor reflects the real
+	 time die temperature through ADC channel.
+
 config QCOM_SPMI_TEMP_ALARM
 	tristate "Qualcomm SPMI PMIC Temperature Alarm"
 	depends on OF && SPMI && IIO
diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
index 828d9e7bc797094453566f310b1aea558294162b..937ba0fe2801325592ba8e4354ba1f0ec3109c32 100644
--- a/drivers/thermal/qcom/Makefile
+++ b/drivers/thermal/qcom/Makefile
@@ -5,5 +5,6 @@ qcom_tsens-y			+= tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \
 				   tsens-8960.o
 obj-$(CONFIG_QCOM_SPMI_ADC_TM5)	+= qcom-spmi-adc-tm5.o
 obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3)	+= qcom-spmi-adc-tm5-gen3.o
+obj-$(CONFIG_QCOM_SPMI_MBG_TM) += qcom-spmi-mbg-tm.o
 obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM)	+= qcom-spmi-temp-alarm.o
 obj-$(CONFIG_QCOM_LMH)		+= lmh.o
diff --git a/drivers/thermal/qcom/qcom-spmi-mbg-tm.c b/drivers/thermal/qcom/qcom-spmi-mbg-tm.c
new file mode 100644
index 0000000000000000000000000000000000000000..22ca331a6de355af22f270d6e047167ce1bcb55a
--- /dev/null
+++ b/drivers/thermal/qcom/qcom-spmi-mbg-tm.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/thermal.h>
+#include <linux/iio/consumer.h>
+
+#include "../thermal_core.h"
+
+#define MBG_TEMP_MON2_FAULT_STATUS	0x50
+
+#define MON_FAULT_STATUS_MASK		GENMASK(7, 6)
+#define MON_POLARITY_STATUS_MASK	GENMASK(5, 4)
+
+#define MON_FAULT_STATUS_LVL1		BIT(6)
+#define MON_POLARITY_STATUS_UPR		BIT(4)
+
+#define MON2_LVL1_UP_THRESH		0x59
+
+#define MBG_TEMP_MON2_MISC_CFG		0x5f
+#define MON2_UP_THRESH_EN		BIT(1)
+
+#define MBG_TEMP_STEP_MV		8
+#define MBG_TEMP_DEFAULT_TEMP_MV	600
+#define MBG_TEMP_CONSTANT		1000
+#define MBG_MIN_TRIP_TEMP		25000
+#define MBG_MAX_SUPPORTED_TEMP		160000
+
+struct mbg_tm_chip {
+	struct regmap			*map;
+	struct device			*dev;
+	struct thermal_zone_device	*tz_dev;
+	struct mutex                    lock;
+	unsigned int			base;
+	int				irq;
+	int				last_temp;
+	bool				last_thres_crossed;
+	struct iio_channel		*adc;
+};
+
+struct mbg_map_table {
+	int min_temp;
+	int vtemp0;
+	int tc;
+};
+
+static const struct mbg_map_table map_table[] = {
+	/* minT	vtemp0	tc */
+	{ -60000, 4337, 1967 },
+	{ -40000, 4731, 1964 },
+	{ -20000, 5124, 1957  },
+	{ 0,      5515, 1949 },
+	{ 20000,  5905, 1940 },
+	{ 40000,  6293, 1930 },
+	{ 60000,  6679, 1921 },
+	{ 80000,  7064, 1910 },
+	{ 100000, 7446, 1896 },
+	{ 120000, 7825, 1878 },
+	{ 140000, 8201, 1859 },
+};
+
+static int mbg_tm_get_temp(struct thermal_zone_device *tz, int *temp)
+{
+	struct mbg_tm_chip *chip = thermal_zone_device_priv(tz);
+	int ret, milli_celsius;
+
+	if (!temp)
+		return -EINVAL;
+
+	if (chip->last_thres_crossed) {
+		pr_debug("last_temp: %d\n", chip->last_temp);
+		chip->last_thres_crossed = false;
+		*temp = chip->last_temp;
+		return 0;
+	}
+
+	ret = iio_read_channel_processed(chip->adc, &milli_celsius);
+	if (ret < 0) {
+		dev_err(chip->dev, "failed to read iio channel %d\n", ret);
+		return ret;
+	}
+
+	*temp = milli_celsius;
+
+	return 0;
+}
+
+static int temp_to_vtemp(int temp)
+{
+
+	int idx, vtemp, tc = 0, t0 = 0, vtemp0 = 0;
+
+	for (idx = 0; idx < ARRAY_SIZE(map_table); idx++)
+		if (temp >= map_table[idx].min_temp &&
+				temp < (map_table[idx].min_temp + 20000)) {
+			tc = map_table[idx].tc;
+			t0 = map_table[idx].min_temp;
+			vtemp0 = map_table[idx].vtemp0;
+			break;
+		}
+
+	/*
+	 * Formula to calculate vtemp(mV) from a given temp
+	 * vtemp = (temp - minT) * tc + vtemp0
+	 * tc, t0 and vtemp0 values are mentioned in the map_table array.
+	 */
+	vtemp = ((temp - t0) * tc + vtemp0 * 100000) / 1000000;
+
+	return abs(vtemp - MBG_TEMP_DEFAULT_TEMP_MV) / MBG_TEMP_STEP_MV;
+}
+
+static int mbg_tm_set_trip_temp(struct thermal_zone_device *tz, int low_temp,
+						int temp)
+{
+	struct mbg_tm_chip *chip = thermal_zone_device_priv(tz);
+	int ret = 0;
+
+	guard(mutex)(&chip->lock);
+
+	/* The HW has a limitation that the trip set must be above 25C */
+	if (temp > MBG_MIN_TRIP_TEMP && temp < MBG_MAX_SUPPORTED_TEMP) {
+		regmap_set_bits(chip->map,
+			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
+		ret = regmap_write(chip->map, chip->base + MON2_LVL1_UP_THRESH,
+						temp_to_vtemp(temp));
+		if (ret < 0)
+			return ret;
+	} else {
+		dev_dbg(chip->dev, "Set trip b/w 25C and 160C\n");
+		regmap_clear_bits(chip->map,
+			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
+	}
+
+	/*
+	 * Configure the last_temp one degree higher, to ensure the
+	 * violated temp is returned to thermal framework when it reads
+	 * temperature for the first time after the violation happens.
+	 * This is needed to account for the inaccuracy in the conversion
+	 * formula used which leads to the thermal framework setting back
+	 * the same thresholds in case the temperature it reads does not
+	 * show violation.
+	 */
+	chip->last_temp = temp + MBG_TEMP_CONSTANT;
+
+	return ret;
+}
+
+static const struct thermal_zone_device_ops mbg_tm_ops = {
+	.get_temp = mbg_tm_get_temp,
+	.set_trips = mbg_tm_set_trip_temp,
+};
+
+static irqreturn_t mbg_tm_isr(int irq, void *data)
+{
+	struct mbg_tm_chip *chip = data;
+	int ret, val;
+
+	scoped_guard(mutex, &chip->lock) {
+		ret = regmap_read(chip->map,
+			chip->base + MBG_TEMP_MON2_FAULT_STATUS, &val);
+		if (ret < 0)
+			return IRQ_HANDLED;
+	}
+
+	if ((val & MON_FAULT_STATUS_MASK) & MON_FAULT_STATUS_LVL1) {
+		if ((val & MON_POLARITY_STATUS_MASK) & MON_POLARITY_STATUS_UPR) {
+			chip->last_thres_crossed = true;
+			thermal_zone_device_update(chip->tz_dev,
+						THERMAL_TRIP_VIOLATED);
+			dev_dbg(chip->dev, "Notifying Thermal, fault status=%d\n", val);
+		} else {
+			dev_dbg(chip->dev, "Lvl1 upr threshold not violated, ignoring interrupt\n");
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int mbg_tm_probe(struct platform_device *pdev)
+{
+	struct mbg_tm_chip *chip;
+	struct device_node *node = pdev->dev.of_node;
+	u32 res;
+	int ret;
+
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->dev = &pdev->dev;
+
+	mutex_init(&chip->lock);
+
+	chip->map = dev_get_regmap(pdev->dev.parent, NULL);
+	if (!chip->map)
+		return -ENXIO;
+
+	ret = device_property_read_u32(chip->dev, "reg", &res);
+	if (ret < 0)
+		return ret;
+
+	chip->base = res;
+
+	chip->irq = platform_get_irq(pdev, 0);
+	if (chip->irq < 0)
+		return chip->irq;
+
+	chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
+	if (IS_ERR(chip->adc))
+		return dev_err_probe(&pdev->dev, PTR_ERR(chip->adc),
+			       "failed to get adc channel\n");
+
+	chip->tz_dev = devm_thermal_of_zone_register(&pdev->dev, 0,
+						chip, &mbg_tm_ops);
+	if (IS_ERR(chip->tz_dev))
+		return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev),
+			       "failed to register sensor\n");
+
+	return devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
+			mbg_tm_isr, IRQF_ONESHOT, node->name, chip);
+}
+
+static const struct of_device_id mbg_tm_match_table[] = {
+	{ .compatible = "qcom,spmi-pm8775-mbg-tm" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, mbg_tm_match_table);
+
+static struct platform_driver mbg_tm_driver = {
+	.driver = {
+		.name = "qcom-spmi-mbg-tm",
+		.of_match_table = mbg_tm_match_table,
+	},
+	.probe = mbg_tm_probe,
+};
+module_platform_driver(mbg_tm_driver);
+
+MODULE_DESCRIPTION("PMIC MBG Temperature monitor driver");
+MODULE_LICENSE("GPL");

-- 
2.25.1

[PATCH RFC v2 4/5] arm64: dts: qcom: sa8775p-pmics: Add vadc support on SA8775P

[Satya Priya Kakitapalli]

Add support for reading the adc channels of pm8775 on SA8775P platforms.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 94 +++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
index 1369c3d43f866de9d8cd5cd4985241b99c0a0454..e87f95e9ba9f59e3f067af0d5565b8e3ed4b37fc 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
@@ -1,8 +1,10 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
  * Copyright (c) 2023, Linaro Limited
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/spmi/spmi.h>
 
@@ -105,6 +107,29 @@ pmm8654au_0: pmic@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		pmm8654au_0_vadc: adc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <1>;
+
+			channel@0 {
+				reg = <PM8775_ADC5_GEN3_DIE_TEMP(0)>;
+				label = "pmm8654au_0_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			channel@1 {
+				reg = <PM8775_ADC5_GEN3_VPH_PWR(0)>;
+				label = "pmm8654au_0_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pmm8654au_0_temp_alarm: temp-alarm@a00 {
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;
@@ -162,6 +187,29 @@ pmm8654au_1: pmic@2 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		pmm8654au_1_vadc: adc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <1>;
+
+			channel@0 {
+				reg = <PM8775_ADC5_GEN3_DIE_TEMP(2)>;
+				label = "pmm8654au_1_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			channel@1 {
+				reg = <PM8775_ADC5_GEN3_VPH_PWR(2)>;
+				label = "pmm8654au_1_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pmm8654au_1_temp_alarm: temp-alarm@a00 {
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;
@@ -186,6 +234,29 @@ pmm8654au_2: pmic@4 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		pmm8654au_2_vadc: adc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <1>;
+
+			channel@0 {
+				reg = <PM8775_ADC5_GEN3_DIE_TEMP(4)>;
+				label = "pmm8654au_2_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			channel@1 {
+				reg = <PM8775_ADC5_GEN3_VPH_PWR(4)>;
+				label = "pmm8654au_2_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pmm8654au_2_temp_alarm: temp-alarm@a00 {
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;
@@ -210,6 +281,29 @@ pmm8654au_3: pmic@6 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		pmm8654au_3_vadc: adc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <1>;
+
+			channel@0 {
+				reg = <PM8775_ADC5_GEN3_DIE_TEMP(6)>;
+				label = "pmm8654au_3_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			channel@1 {
+				reg = <PM8775_ADC5_GEN3_VPH_PWR(6)>;
+				label = "pmm8654au_3_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pmm8654au_3_temp_alarm: temp-alarm@a00 {
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;

-- 
2.25.1

[PATCH RFC v2 5/5] arm64: dts: qcom: sa8775p-pmics: Add support for MBG TM

[Satya Priya Kakitapalli]

Add support for MBG TEMP peripheral for pm8775 sail pmics on SA8775P.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 116 ++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
index e87f95e9ba9f59e3f067af0d5565b8e3ed4b37fc..eade5784f18629dc9f7ebf0257551bf96bea9a4c 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
@@ -89,6 +89,58 @@ trip1 {
 				};
 			};
 		};
+
+		pm8775-mbg0-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmm8654au_0_mbg_temp>;
+
+			trips {
+				trip0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		pm8775-mbg1-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmm8654au_1_mbg_temp>;
+
+			trips {
+				trip0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		pm8775-mbg2-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmm8654au_2_mbg_temp>;
+
+			trips {
+				trip0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		pm8775-mbg3-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmm8654au_3_mbg_temp>;
+
+			trips {
+				trip0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
 	};
 
 	reboot-mode {
@@ -181,6 +233,22 @@ reboot_reason: reboot-reason@48 {
 		};
 	};
 
+	pmm8654au_sail_0: pmic@1 {
+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmm8654au_0_mbg_temp: temperature-sensor@d700 {
+			compatible = "qcom,spmi-pm8775-mbg-tm";
+			reg = <0xd700>;
+			io-channels = <&pmm8654au_0_vadc PM8775_ADC5_GEN3_DIE_TEMP(0)>;
+			io-channel-names = "thermal";
+			interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
 	pmm8654au_1: pmic@2 {
 		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
 		reg = <0x2 SPMI_USID>;
@@ -228,6 +296,22 @@ pmm8654au_1_gpios: gpio@8800 {
 		};
 	};
 
+	pmm8654au_sail_1: pmic@3 {
+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmm8654au_1_mbg_temp: temperature-sensor@d700 {
+			compatible = "qcom,spmi-pm8775-mbg-tm";
+			reg = <0xd700>;
+			io-channels = <&pmm8654au_1_vadc PM8775_ADC5_GEN3_DIE_TEMP(2)>;
+			io-channel-names = "thermal";
+			interrupts = <0x3 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
 	pmm8654au_2: pmic@4 {
 		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
 		reg = <0x4 SPMI_USID>;
@@ -275,6 +359,22 @@ pmm8654au_2_gpios: gpio@8800 {
 		};
 	};
 
+	pmm8654au_sail_2: pmic@5 {
+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmm8654au_2_mbg_temp: temperature-sensor@d700 {
+			compatible = "qcom,spmi-pm8775-mbg-tm";
+			reg = <0xd700>;
+			io-channels = <&pmm8654au_2_vadc PM8775_ADC5_GEN3_DIE_TEMP(4)>;
+			io-channel-names = "thermal";
+			interrupts = <0x5 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
 	pmm8654au_3: pmic@6 {
 		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
 		reg = <0x6 SPMI_USID>;
@@ -321,4 +421,20 @@ pmm8654au_3_gpios: gpio@8800 {
 			#interrupt-cells = <2>;
 		};
 	};
+
+	pmm8654au_sail_3: pmic@7 {
+		compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
+		reg = <0x7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmm8654au_3_mbg_temp: temperature-sensor@d700 {
+			compatible = "qcom,spmi-pm8775-mbg-tm";
+			reg = <0xd700>;
+			io-channels = <&pmm8654au_3_vadc PM8775_ADC5_GEN3_DIE_TEMP(6)>;
+			io-channel-names = "thermal";
+			interrupts = <0x7 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
+			#thermal-sensor-cells = <0>;
+		};
+	};
 };

-- 
2.25.1

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Rob Herring (Arm)]

On Thu, 12 Dec 2024 21:41:20 +0530, Satya Priya Kakitapalli wrote:
> Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp
> alarm peripheral found on PM8775 pmic.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---
>  .../bindings/thermal/qcom-spmi-mbg-tm.yaml         | 86 ++++++++++++++++++++++
>  .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h           | 41 +++++++++++
>  2 files changed, 127 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
In file included from Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.example.dts:25:
./scripts/dtc/include-prefixes/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h:9:10: fatal error: dt-bindings/iio/adc/qcom,spmi-vadc.h: No such file or directory
    9 | #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1506: dt_binding_check] Error 2
make: *** [Makefile:251: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241212-mbg-v2-support-v2-1-3249a4339b6e@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH RFC v2 2/5] dt-bindings: mfd: qcom,spmi-pmic: Add MBG thermal monitor ref

[Rob Herring (Arm)]

On Thu, 12 Dec 2024 21:41:21 +0530, Satya Priya Kakitapalli wrote:
> Add reference to the newly added MBG thermal monitor bindings.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---
>  Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:


doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241212-mbg-v2-support-v2-2-3249a4339b6e@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Krzysztof Kozlowski]

On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - io-channels
> +  - io-channel-names

Binding looks ok, but this wasn't tested due to unneeded dependency.
Please decouple from dependency, so automation can properly test it.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8775.h>
> +
> +    pmic {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        pmm8654au_0_tz: temperature-sensor@d700 {

Drop label.

> +            compatible = "qcom,spmi-pm8775-mbg-tm";
> +            reg = <0xd700>;
> +            interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
> +            io-channels = <&pm8775_1_adc PM8775_ADC5_GEN3_DIE_TEMP(1)>;
> +            io-channel-names = "thermal";
> +            #thermal-sensor-cells = <0>;
> +        };
> +    };
> +
> +    thermal-zones {
> +        pm8775-mbg0-thermal {

Drop the nodes, not related.

Best regards,
Krzysztof

Re: [PATCH RFC v2 0/5] Add support for MBG Thermal monitoring device

[Krzysztof Kozlowski]

On Thu, Dec 12, 2024 at 09:41:19PM +0530, Satya Priya Kakitapalli wrote:
> Add bindings, driver and DT for the Qualcomm's MBG thermal
> monitoring device.
> 
> Please note that this series is dependent on [1] which adds
> ADC5-GEN3 support.

Where is the changelog? What happened here?

Why this is RFC?

Limited review follows (as this is not yet ready).

Best regards,
Krzysztof

Re: [PATCH RFC v2 2/5] dt-bindings: mfd: qcom,spmi-pmic: Add MBG thermal monitor ref

[Krzysztof Kozlowski]

On Thu, Dec 12, 2024 at 09:41:21PM +0530, Satya Priya Kakitapalli wrote:
> Add reference to the newly added MBG thermal monitor bindings.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>

You must explain the dependencies between in changelog or cover letter,
because you trick now maintainers into applying something which will
lead to broken tree.

Just squash the patch, it is not a separate feature.

Best regards,
Krzysztof

Re: [PATCH RFC v2 0/5] Add support for MBG Thermal monitoring device

[Satya Priya Kakitapalli]

On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
> On Thu, Dec 12, 2024 at 09:41:19PM +0530, Satya Priya Kakitapalli wrote:
>> Add bindings, driver and DT for the Qualcomm's MBG thermal
>> monitoring device.
>>
>> Please note that this series is dependent on [1] which adds
>> ADC5-GEN3 support.
> Where is the changelog? What happened here?


Sorry for missing the change log, please find the summary below:


Changes from v1 to v2:

- Squash the ADC IIO channel bindings(header) and yaml into single patch

- Add new patch [2/5] to add reference to qcom-spmi-mbg-tm.yaml in 
mfd/qcom,spmi-pmic.yaml bindings.

- Use scoped_guard mutex in driver, remove the helper APIs and directly 
use regmap_set/clear_bits() APIs

- Corrected the isr logic to notify the thermal only for lvl1 upper 
threshold violation.  Earlier logic was not handling this fully.

- Update the dt node names and remove the polling delay as it is 0 by 
default.

- Link to v1: 
https://lore.kernel.org/linux-arm-msm/54c3fdd2-f701-4a06-bb3f-41f5a431687a@quicinc.com/


> Why this is RFC?


On v1 I was suggested to mark this as RFC since the dependent changes 
are not yet accepted.


> Limited review follows (as this is not yet ready).
>
> Best regards,
> Krzysztof
>

Re: [PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring

[Konrad Dybcio]

On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote:
> Add driver for the MBG thermal monitoring device. It monitors
> the die temperature, and when there is a level 1 upper threshold
> violation, it receives an interrupt over spmi. The driver reads
> the fault status register and notifies thermal accordingly.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---

[...]

> +static const struct mbg_map_table map_table[] = {

Is this peripheral/pmic-specific?

> +	/* minT	vtemp0	tc */
> +	{ -60000, 4337, 1967 },
> +	{ -40000, 4731, 1964 },
> +	{ -20000, 5124, 1957  },
> +	{ 0,      5515, 1949 },
> +	{ 20000,  5905, 1940 },
> +	{ 40000,  6293, 1930 },
> +	{ 60000,  6679, 1921 },
> +	{ 80000,  7064, 1910 },
> +	{ 100000, 7446, 1896 },
> +	{ 120000, 7825, 1878 },
> +	{ 140000, 8201, 1859 },
> +};
> +
> +static int mbg_tm_get_temp(struct thermal_zone_device *tz, int *temp)
> +{
> +	struct mbg_tm_chip *chip = thermal_zone_device_priv(tz);
> +	int ret, milli_celsius;
> +
> +	if (!temp)
> +		return -EINVAL;
> +
> +	if (chip->last_thres_crossed) {
> +		pr_debug("last_temp: %d\n", chip->last_temp);

Use dev_dbg for consistency with the other debug prints

> +		chip->last_thres_crossed = false;
> +		*temp = chip->last_temp;
> +		return 0;
> +	}
> +
> +	ret = iio_read_channel_processed(chip->adc, &milli_celsius);
> +	if (ret < 0) {
> +		dev_err(chip->dev, "failed to read iio channel %d\n", ret);
> +		return ret;
> +	}
> +
> +	*temp = milli_celsius;
> +
> +	return 0;
> +}
> +
> +static int temp_to_vtemp(int temp)
> +{
> +
> +	int idx, vtemp, tc = 0, t0 = 0, vtemp0 = 0;
> +
> +	for (idx = 0; idx < ARRAY_SIZE(map_table); idx++)
> +		if (temp >= map_table[idx].min_temp &&
> +				temp < (map_table[idx].min_temp + 20000)) {

Please align the two lines, tab width is 8 for kernel code

> +			tc = map_table[idx].tc;
> +			t0 = map_table[idx].min_temp;
> +			vtemp0 = map_table[idx].vtemp0;
> +			break;
> +		}
> +
> +	/*
> +	 * Formula to calculate vtemp(mV) from a given temp
> +	 * vtemp = (temp - minT) * tc + vtemp0
> +	 * tc, t0 and vtemp0 values are mentioned in the map_table array.
> +	 */
> +	vtemp = ((temp - t0) * tc + vtemp0 * 100000) / 1000000;

So you say vtemp = ... and the func is called temp_to_vtemp

> +	return abs(vtemp - MBG_TEMP_DEFAULT_TEMP_MV) / MBG_TEMP_STEP_MV;

But you end up returning a scaled version of it..
Please clarify that in the code


> +}
> +
> +static int mbg_tm_set_trip_temp(struct thermal_zone_device *tz, int low_temp,
> +						int temp)
> +{
> +	struct mbg_tm_chip *chip = thermal_zone_device_priv(tz);
> +	int ret = 0;
> +
> +	guard(mutex)(&chip->lock);
> +
> +	/* The HW has a limitation that the trip set must be above 25C */
> +	if (temp > MBG_MIN_TRIP_TEMP && temp < MBG_MAX_SUPPORTED_TEMP) {
> +		regmap_set_bits(chip->map,
> +			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
> +		ret = regmap_write(chip->map, chip->base + MON2_LVL1_UP_THRESH,
> +						temp_to_vtemp(temp));
> +		if (ret < 0)
> +			return ret;
> +	} else {
> +		dev_dbg(chip->dev, "Set trip b/w 25C and 160C\n");
> +		regmap_clear_bits(chip->map,
> +			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
> +	}
> +
> +	/*
> +	 * Configure the last_temp one degree higher, to ensure the
> +	 * violated temp is returned to thermal framework when it reads
> +	 * temperature for the first time after the violation happens.
> +	 * This is needed to account for the inaccuracy in the conversion
> +	 * formula used which leads to the thermal framework setting back
> +	 * the same thresholds in case the temperature it reads does not
> +	 * show violation.
> +	 */
> +	chip->last_temp = temp + MBG_TEMP_CONSTANT;
> +
> +	return ret;
> +}
> +
> +static const struct thermal_zone_device_ops mbg_tm_ops = {
> +	.get_temp = mbg_tm_get_temp,
> +	.set_trips = mbg_tm_set_trip_temp,
> +};
> +
> +static irqreturn_t mbg_tm_isr(int irq, void *data)
> +{
> +	struct mbg_tm_chip *chip = data;
> +	int ret, val;
> +
> +	scoped_guard(mutex, &chip->lock) {
> +		ret = regmap_read(chip->map,
> +			chip->base + MBG_TEMP_MON2_FAULT_STATUS, &val);
> +		if (ret < 0)
> +			return IRQ_HANDLED;
> +	}
> +
> +	if ((val & MON_FAULT_STATUS_MASK) & MON_FAULT_STATUS_LVL1) {
> +		if ((val & MON_POLARITY_STATUS_MASK) & MON_POLARITY_STATUS_UPR) {

Just checking the last argument to AND in both lines is enough, as
they're both parts of the bitfield

[...]

> +	ret = device_property_read_u32(chip->dev, "reg", &res);
> +	if (ret < 0)
> +		return ret;

return dev_err_probe(dev, ret, "Couldn't read reg property"\n);

> +
> +	chip->base = res;
> +
> +	chip->irq = platform_get_irq(pdev, 0);
> +	if (chip->irq < 0)
> +		return chip->irq;

Similarly here

> +
> +	chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
> +	if (IS_ERR(chip->adc))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(chip->adc),
> +			       "failed to get adc channel\n");
> +
> +	chip->tz_dev = devm_thermal_of_zone_register(&pdev->dev, 0,
> +						chip, &mbg_tm_ops);
> +	if (IS_ERR(chip->tz_dev))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev),
> +			       "failed to register sensor\n");

Please also make the error messages start with an uppercase letter

> +
> +	return devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
> +			mbg_tm_isr, IRQF_ONESHOT, node->name, chip);
> +}
> +
> +static const struct of_device_id mbg_tm_match_table[] = {
> +	{ .compatible = "qcom,spmi-pm8775-mbg-tm" },

I don't think the 'spmi' bit belongs here

Konrad

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Konrad Dybcio]

On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote:
> Add PM8775 ADC5 GEN3 Channel info and bindings for the MBG Temp
> alarm peripheral found on PM8775 pmic.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---
>  .../bindings/thermal/qcom-spmi-mbg-tm.yaml         | 86 ++++++++++++++++++++++
>  .../iio/adc/qcom,spmi-adc5-gen3-pm8775.h           | 41 +++++++++++
>  2 files changed, 127 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..909373eb758e4a8b7c2bbd0022c56ab2e823ca13
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-mbg-tm.yaml
> @@ -0,0 +1,86 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/thermal/qcom-spmi-mbg-tm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. SPMI PMIC MBG Thermal Monitoring
> +
> +maintainers:
> +  - Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> +
> +description:
> +  Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die
> +  temperature and generates an interrupt if the PMIC die temperature is
> +  over a set of programmable temperature thresholds. It allows monitoring
> +  for both hot and cold, LVL1 and LVL2 thresholds, which makes it different
> +  from the existing temp alarm peripheral. The interrupt comes over SPMI
> +  and the MBG's fault status register gives details to understand whether
> +  it is a hot/cold and LVL1/LVL2 violation.
> +
> +allOf:
> +  - $ref: thermal-sensor.yaml#
> +
> +properties:
> +  compatible:
> +    const: qcom,spmi-pm8775-mbg-tm

The bus the chip is connected over shouldn't be part of the compatible

Konrad

Re: [PATCH RFC v2 0/5] Add support for MBG Thermal monitoring device

[Krzysztof Kozlowski]

On 13/12/2024 10:20, Satya Priya Kakitapalli wrote:
>> Why this is RFC?
> 
> 
> On v1 I was suggested to mark this as RFC since the dependent changes 
> are not yet accepted.
> 
Cover letter should explain this, IOW, explain your intentions.

Best regards,
Krzysztof

Re: [PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring

[Jonathan Cameron]

On Thu, 12 Dec 2024 21:41:22 +0530
Satya Priya Kakitapalli <quic_skakitap@quicinc.com> wrote:

> Add driver for the MBG thermal monitoring device. It monitors
> the die temperature, and when there is a level 1 upper threshold
> violation, it receives an interrupt over spmi. The driver reads
> the fault status register and notifies thermal accordingly.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Just a quick comment on consistency of formatting.

> +static int mbg_tm_set_trip_temp(struct thermal_zone_device *tz, int low_temp,
> +						int temp)
> +{
> +	struct mbg_tm_chip *chip = thermal_zone_device_priv(tz);
> +	int ret = 0;
> +
> +	guard(mutex)(&chip->lock);
> +
> +	/* The HW has a limitation that the trip set must be above 25C */
> +	if (temp > MBG_MIN_TRIP_TEMP && temp < MBG_MAX_SUPPORTED_TEMP) {
> +		regmap_set_bits(chip->map,
> +			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
> +		ret = regmap_write(chip->map, chip->base + MON2_LVL1_UP_THRESH,
> +						temp_to_vtemp(temp));
Alignment in this driver should be consistent / tidied up.

I'm not sure on style preferred in thermal, but I'd always default to align
after the opening bracket + wrap at 80 chars unless readability is hurt.


> +		if (ret < 0)
> +			return ret;
> +	} else {
> +		dev_dbg(chip->dev, "Set trip b/w 25C and 160C\n");
> +		regmap_clear_bits(chip->map,
> +			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
> +	}

Re: [PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring

[Satya Priya Kakitapalli]

On 12/13/2024 9:18 PM, Konrad Dybcio wrote:
> On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote:
>> Add driver for the MBG thermal monitoring device. It monitors
>> the die temperature, and when there is a level 1 upper threshold
>> violation, it receives an interrupt over spmi. The driver reads
>> the fault status register and notifies thermal accordingly.
>>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>> ---
> [...]
>
>> +static const struct mbg_map_table map_table[] = {
> Is this peripheral/pmic-specific?


Yes, peripheral specific.


>> +	/* minT	vtemp0	tc */
>> +	{ -60000, 4337, 1967 },
>> +	{ -40000, 4731, 1964 },
>> +	{ -20000, 5124, 1957  },
>> +	{ 0,      5515, 1949 },
>> +	{ 20000,  5905, 1940 },
>> +	{ 40000,  6293, 1930 },
>> +	{ 60000,  6679, 1921 },
>> +	{ 80000,  7064, 1910 },
>> +	{ 100000, 7446, 1896 },
>> +	{ 120000, 7825, 1878 },
>> +	{ 140000, 8201, 1859 },
>> +};
>> +
>> +static int mbg_tm_get_temp(struct thermal_zone_device *tz, int *temp)
>> +{
>> +	struct mbg_tm_chip *chip = thermal_zone_device_priv(tz);
>> +	int ret, milli_celsius;
>> +
>> +	if (!temp)
>> +		return -EINVAL;
>> +
>> +	if (chip->last_thres_crossed) {
>> +		pr_debug("last_temp: %d\n", chip->last_temp);
> Use dev_dbg for consistency with the other debug prints


Okay.


>> +		chip->last_thres_crossed = false;
>> +		*temp = chip->last_temp;
>> +		return 0;
>> +	}
>> +
>> +	ret = iio_read_channel_processed(chip->adc, &milli_celsius);
>> +	if (ret < 0) {
>> +		dev_err(chip->dev, "failed to read iio channel %d\n", ret);
>> +		return ret;
>> +	}
>> +
>> +	*temp = milli_celsius;
>> +
>> +	return 0;
>> +}
>> +
>> +static int temp_to_vtemp(int temp)
>> +{
>> +
>> +	int idx, vtemp, tc = 0, t0 = 0, vtemp0 = 0;
>> +
>> +	for (idx = 0; idx < ARRAY_SIZE(map_table); idx++)
>> +		if (temp >= map_table[idx].min_temp &&
>> +				temp < (map_table[idx].min_temp + 20000)) {
> Please align the two lines, tab width is 8 for kernel code


Okay.


>> +			tc = map_table[idx].tc;
>> +			t0 = map_table[idx].min_temp;
>> +			vtemp0 = map_table[idx].vtemp0;
>> +			break;
>> +		}
>> +
>> +	/*
>> +	 * Formula to calculate vtemp(mV) from a given temp
>> +	 * vtemp = (temp - minT) * tc + vtemp0
>> +	 * tc, t0 and vtemp0 values are mentioned in the map_table array.
>> +	 */
>> +	vtemp = ((temp - t0) * tc + vtemp0 * 100000) / 1000000;
> So you say vtemp = ... and the func is called temp_to_vtemp
>
>> +	return abs(vtemp - MBG_TEMP_DEFAULT_TEMP_MV) / MBG_TEMP_STEP_MV;
> But you end up returning a scaled version of it..
> Please clarify that in the code


Sure, I'll update the function name to temp_to_vtemp_mv and probably add 
a comment in the code.


>
>> +}
>> +
>> +static int mbg_tm_set_trip_temp(struct thermal_zone_device *tz, int low_temp,
>> +						int temp)
>> +{
>> +	struct mbg_tm_chip *chip = thermal_zone_device_priv(tz);
>> +	int ret = 0;
>> +
>> +	guard(mutex)(&chip->lock);
>> +
>> +	/* The HW has a limitation that the trip set must be above 25C */
>> +	if (temp > MBG_MIN_TRIP_TEMP && temp < MBG_MAX_SUPPORTED_TEMP) {
>> +		regmap_set_bits(chip->map,
>> +			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
>> +		ret = regmap_write(chip->map, chip->base + MON2_LVL1_UP_THRESH,
>> +						temp_to_vtemp(temp));
>> +		if (ret < 0)
>> +			return ret;
>> +	} else {
>> +		dev_dbg(chip->dev, "Set trip b/w 25C and 160C\n");
>> +		regmap_clear_bits(chip->map,
>> +			chip->base + MBG_TEMP_MON2_MISC_CFG, MON2_UP_THRESH_EN);
>> +	}
>> +
>> +	/*
>> +	 * Configure the last_temp one degree higher, to ensure the
>> +	 * violated temp is returned to thermal framework when it reads
>> +	 * temperature for the first time after the violation happens.
>> +	 * This is needed to account for the inaccuracy in the conversion
>> +	 * formula used which leads to the thermal framework setting back
>> +	 * the same thresholds in case the temperature it reads does not
>> +	 * show violation.
>> +	 */
>> +	chip->last_temp = temp + MBG_TEMP_CONSTANT;
>> +
>> +	return ret;
>> +}
>> +
>> +static const struct thermal_zone_device_ops mbg_tm_ops = {
>> +	.get_temp = mbg_tm_get_temp,
>> +	.set_trips = mbg_tm_set_trip_temp,
>> +};
>> +
>> +static irqreturn_t mbg_tm_isr(int irq, void *data)
>> +{
>> +	struct mbg_tm_chip *chip = data;
>> +	int ret, val;
>> +
>> +	scoped_guard(mutex, &chip->lock) {
>> +		ret = regmap_read(chip->map,
>> +			chip->base + MBG_TEMP_MON2_FAULT_STATUS, &val);
>> +		if (ret < 0)
>> +			return IRQ_HANDLED;
>> +	}
>> +
>> +	if ((val & MON_FAULT_STATUS_MASK) & MON_FAULT_STATUS_LVL1) {
>> +		if ((val & MON_POLARITY_STATUS_MASK) & MON_POLARITY_STATUS_UPR) {
> Just checking the last argument to AND in both lines is enough, as
> they're both parts of the bitfield


Both the bits of each mask need to be checked in order to proceed 
accordingly, I will update with proper logic in next version.


>
> [...]
>
>> +	ret = device_property_read_u32(chip->dev, "reg", &res);
>> +	if (ret < 0)
>> +		return ret;
> return dev_err_probe(dev, ret, "Couldn't read reg property"\n);
>
>> +
>> +	chip->base = res;
>> +
>> +	chip->irq = platform_get_irq(pdev, 0);
>> +	if (chip->irq < 0)
>> +		return chip->irq;
> Similarly here
>
>> +
>> +	chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
>> +	if (IS_ERR(chip->adc))
>> +		return dev_err_probe(&pdev->dev, PTR_ERR(chip->adc),
>> +			       "failed to get adc channel\n");
>> +
>> +	chip->tz_dev = devm_thermal_of_zone_register(&pdev->dev, 0,
>> +						chip, &mbg_tm_ops);
>> +	if (IS_ERR(chip->tz_dev))
>> +		return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev),
>> +			       "failed to register sensor\n");
> Please also make the error messages start with an uppercase letter
>
>> +
>> +	return devm_request_threaded_irq(&pdev->dev, chip->irq, NULL,
>> +			mbg_tm_isr, IRQF_ONESHOT, node->name, chip);
>> +}
>> +
>> +static const struct of_device_id mbg_tm_match_table[] = {
>> +	{ .compatible = "qcom,spmi-pm8775-mbg-tm" },
> I don't think the 'spmi' bit belongs here


Okay, will update it.


> Konrad

Re: [PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring

[Konrad Dybcio]

On 30.12.2024 10:45 AM, Satya Priya Kakitapalli wrote:
> 
> On 12/13/2024 9:18 PM, Konrad Dybcio wrote:
>> On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote:
>>> Add driver for the MBG thermal monitoring device. It monitors
>>> the die temperature, and when there is a level 1 upper threshold
>>> violation, it receives an interrupt over spmi. The driver reads
>>> the fault status register and notifies thermal accordingly.
>>>
>>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>>> ---
>> [...]
>>
>>> +static const struct mbg_map_table map_table[] = {
>> Is this peripheral/pmic-specific?
> 
> 
> Yes, peripheral specific.

Okay, I asked a question that I don't recall what I meant by.

To be clear, is this table specific to all instances of MBG on
different kinds of PMIC7, or does it only apply to PM8775
specifically?

> 
>>> +    /* minT    vtemp0    tc */
>>> +    { -60000, 4337, 1967 },
>>> +    { -40000, 4731, 1964 },
>>> +    { -20000, 5124, 1957  },
>>> +    { 0,      5515, 1949 },
>>> +    { 20000,  5905, 1940 },
>>> +    { 40000,  6293, 1930 },
>>> +    { 60000,  6679, 1921 },
>>> +    { 80000,  7064, 1910 },
>>> +    { 100000, 7446, 1896 },
>>> +    { 120000, 7825, 1878 },
>>> +    { 140000, 8201, 1859 },
>>> +};

Konrad

Re: [PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring

[Satya Priya Kakitapalli]

On 12/30/2024 7:36 PM, Konrad Dybcio wrote:
> On 30.12.2024 10:45 AM, Satya Priya Kakitapalli wrote:
>> On 12/13/2024 9:18 PM, Konrad Dybcio wrote:
>>> On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote:
>>>> Add driver for the MBG thermal monitoring device. It monitors
>>>> the die temperature, and when there is a level 1 upper threshold
>>>> violation, it receives an interrupt over spmi. The driver reads
>>>> the fault status register and notifies thermal accordingly.
>>>>
>>>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>>>> ---
>>> [...]
>>>
>>>> +static const struct mbg_map_table map_table[] = {
>>> Is this peripheral/pmic-specific?
>>
>> Yes, peripheral specific.
> Okay, I asked a question that I don't recall what I meant by.
>
> To be clear, is this table specific to all instances of MBG on
> different kinds of PMIC7, or does it only apply to PM8775
> specifically?


No it is not specific to PM8775 pmic, it is specific to MBG peripheral.


>>>> +    /* minT    vtemp0    tc */
>>>> +    { -60000, 4337, 1967 },
>>>> +    { -40000, 4731, 1964 },
>>>> +    { -20000, 5124, 1957  },
>>>> +    { 0,      5515, 1949 },
>>>> +    { 20000,  5905, 1940 },
>>>> +    { 40000,  6293, 1930 },
>>>> +    { 60000,  6679, 1921 },
>>>> +    { 80000,  7064, 1910 },
>>>> +    { 100000, 7446, 1896 },
>>>> +    { 120000, 7825, 1878 },
>>>> +    { 140000, 8201, 1859 },
>>>> +};
> Konrad

Re: [PATCH RFC v2 3/5] thermal: qcom: Add support for MBG thermal monitoring

[Konrad Dybcio]

On 16.01.2025 9:05 AM, Satya Priya Kakitapalli wrote:
> 
> On 12/30/2024 7:36 PM, Konrad Dybcio wrote:
>> On 30.12.2024 10:45 AM, Satya Priya Kakitapalli wrote:
>>> On 12/13/2024 9:18 PM, Konrad Dybcio wrote:
>>>> On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote:
>>>>> Add driver for the MBG thermal monitoring device. It monitors
>>>>> the die temperature, and when there is a level 1 upper threshold
>>>>> violation, it receives an interrupt over spmi. The driver reads
>>>>> the fault status register and notifies thermal accordingly.
>>>>>
>>>>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>>>>> ---
>>>> [...]
>>>>
>>>>> +static const struct mbg_map_table map_table[] = {
>>>> Is this peripheral/pmic-specific?
>>>
>>> Yes, peripheral specific.
>> Okay, I asked a question that I don't recall what I meant by.
>>
>> To be clear, is this table specific to all instances of MBG on
>> different kinds of PMIC7, or does it only apply to PM8775
>> specifically?
> 
> 
> No it is not specific to PM8775 pmic, it is specific to MBG peripheral.

OK, that is good, thanks for confirming.

Konrad

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Krzysztof Kozlowski]

On 11/02/2025 12:15, Satya Priya Kakitapalli wrote:
> 
> On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
>> On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - interrupts
>>> +  - io-channels
>>> +  - io-channel-names
>> Binding looks ok, but this wasn't tested due to unneeded dependency.
>> Please decouple from dependency, so automation can properly test it.
> 
> 
> The dependency is needed because this mbg peripheral is present on only 
> targets which have GEN3 ADC5, for which the bindings support is added in 
> the series [1]
> 
> 
> [1] 
> https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/

Sure. Then this cannot be merged due to resulting test failure.

Please don't post new versions before this can be actually tested and
applied.

Best regards,
Krzysztof

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Krzysztof Kozlowski]

On 11/02/2025 12:46, Krzysztof Kozlowski wrote:
> On 11/02/2025 12:15, Satya Priya Kakitapalli wrote:
>>
>> On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
>>> On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
>>>> +
>>>> +required:
>>>> +  - compatible
>>>> +  - reg
>>>> +  - interrupts
>>>> +  - io-channels
>>>> +  - io-channel-names
>>> Binding looks ok, but this wasn't tested due to unneeded dependency.
>>> Please decouple from dependency, so automation can properly test it.
>>
>>
>> The dependency is needed because this mbg peripheral is present on only 
>> targets which have GEN3 ADC5, for which the bindings support is added in 
>> the series [1]
>>
>>
>> [1] 
>> https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/
> 
> Sure. Then this cannot be merged due to resulting test failure.
> 
> Please don't post new versions before this can be actually tested and
> applied.

Heh, you responded *after two months*, to an old email so even previous
discussion is gone from my inbox.

Best regards,
Krzysztof

Re: [PATCH RFC v2 5/5] arm64: dts: qcom: sa8775p-pmics: Add support for MBG TM

[Konrad Dybcio]

On 12.12.2024 5:11 PM, Satya Priya Kakitapalli wrote:
> Add support for MBG TEMP peripheral for pm8775 sail pmics on SA8775P.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 116 ++++++++++++++++++++++++++++
>  1 file changed, 116 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
> index e87f95e9ba9f59e3f067af0d5565b8e3ed4b37fc..eade5784f18629dc9f7ebf0257551bf96bea9a4c 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi
> @@ -89,6 +89,58 @@ trip1 {
>  				};
>  			};
>  		};
> +
> +		pm8775-mbg0-thermal {
> +			polling-delay-passive = <100>;
> +			thermal-sensors = <&pmm8654au_0_mbg_temp>;
> +
> +			trips {
> +				trip0 {
> +					temperature = <115000>;
> +					hysteresis = <5000>;
> +					type = "passive";

These could possibly be 'critical' if 115C is the TjMAX or near it

Konrad

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Dmitry Baryshkov]

On Tue, Feb 11, 2025 at 12:50:12PM +0100, Krzysztof Kozlowski wrote:
> On 11/02/2025 12:46, Krzysztof Kozlowski wrote:
> > On 11/02/2025 12:15, Satya Priya Kakitapalli wrote:
> >>
> >> On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
> >>> On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
> >>>> +
> >>>> +required:
> >>>> +  - compatible
> >>>> +  - reg
> >>>> +  - interrupts
> >>>> +  - io-channels
> >>>> +  - io-channel-names
> >>> Binding looks ok, but this wasn't tested due to unneeded dependency.
> >>> Please decouple from dependency, so automation can properly test it.
> >>
> >>
> >> The dependency is needed because this mbg peripheral is present on only 
> >> targets which have GEN3 ADC5, for which the bindings support is added in 
> >> the series [1]
> >>
> >>
> >> [1] 
> >> https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/
> > 
> > Sure. Then this cannot be merged due to resulting test failure.
> > 
> > Please don't post new versions before this can be actually tested and
> > applied.
> 
> Heh, you responded *after two months*, to an old email so even previous
> discussion is gone from my inbox.

Are you responding to your own email?

-- 
With best wishes
Dmitry

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Krzysztof Kozlowski]

On 12/02/2025 00:57, Dmitry Baryshkov wrote:
> On Tue, Feb 11, 2025 at 12:50:12PM +0100, Krzysztof Kozlowski wrote:
>> On 11/02/2025 12:46, Krzysztof Kozlowski wrote:
>>> On 11/02/2025 12:15, Satya Priya Kakitapalli wrote:
>>>>
>>>> On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
>>>>> On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
>>>>>> +
>>>>>> +required:
>>>>>> +  - compatible
>>>>>> +  - reg
>>>>>> +  - interrupts
>>>>>> +  - io-channels
>>>>>> +  - io-channel-names
>>>>> Binding looks ok, but this wasn't tested due to unneeded dependency.
>>>>> Please decouple from dependency, so automation can properly test it.
>>>>
>>>>
>>>> The dependency is needed because this mbg peripheral is present on only 
>>>> targets which have GEN3 ADC5, for which the bindings support is added in 
>>>> the series [1]
>>>>
>>>>
>>>> [1] 
>>>> https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/
>>>
>>> Sure. Then this cannot be merged due to resulting test failure.
>>>
>>> Please don't post new versions before this can be actually tested and
>>> applied.
>>
>> Heh, you responded *after two months*, to an old email so even previous
>> discussion is gone from my inbox.
> 
> Are you responding to your own email?

Look at the timeline of these emails. Satya responded after two months
with some comment. I responded now. Then I noticed that it is talk about
something two months old, so I responded again. Two responses from me,
that's correct.

I recently got way too many such 2-month old clarifications.

That's indeed right of the contributor to respond in their own pace, I
am also sometimes slow, but really there should be some limit. It's
putting unnecessary burden on reviewers as now I should dig some old
discussion.
Best regards,
Krzysztof

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Satya Priya Kakitapalli]

On 2/11/2025 5:20 PM, Krzysztof Kozlowski wrote:
> On 11/02/2025 12:46, Krzysztof Kozlowski wrote:
>> On 11/02/2025 12:15, Satya Priya Kakitapalli wrote:
>>> On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
>>>> On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
>>>>> +
>>>>> +required:
>>>>> +  - compatible
>>>>> +  - reg
>>>>> +  - interrupts
>>>>> +  - io-channels
>>>>> +  - io-channel-names
>>>> Binding looks ok, but this wasn't tested due to unneeded dependency.
>>>> Please decouple from dependency, so automation can properly test it.
>>>
>>> The dependency is needed because this mbg peripheral is present on only
>>> targets which have GEN3 ADC5, for which the bindings support is added in
>>> the series [1]
>>>
>>>
>>> [1]
>>> https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/
>> Sure. Then this cannot be merged due to resulting test failure.
>>
>> Please don't post new versions before this can be actually tested and
>> applied.
> Heh, you responded *after two months*, to an old email so even previous
> discussion is gone from my inbox.


Sorry about that, I initially misunderstood it was regarding the b4 deps 
I created. I wanted to confirm before posting new version yesterday, 
hence clarified about the dependency.


> Best regards,
> Krzysztof

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Krzysztof Kozlowski]

On 12/02/2025 07:24, Satya Priya Kakitapalli wrote:
> 
> On 2/11/2025 5:20 PM, Krzysztof Kozlowski wrote:
>> On 11/02/2025 12:46, Krzysztof Kozlowski wrote:
>>> On 11/02/2025 12:15, Satya Priya Kakitapalli wrote:
>>>> On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
>>>>> On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
>>>>>> +
>>>>>> +required:
>>>>>> +  - compatible
>>>>>> +  - reg
>>>>>> +  - interrupts
>>>>>> +  - io-channels
>>>>>> +  - io-channel-names
>>>>> Binding looks ok, but this wasn't tested due to unneeded dependency.
>>>>> Please decouple from dependency, so automation can properly test it.
>>>>
>>>> The dependency is needed because this mbg peripheral is present on only
>>>> targets which have GEN3 ADC5, for which the bindings support is added in
>>>> the series [1]
>>>>
>>>>
>>>> [1]
>>>> https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/
>>> Sure. Then this cannot be merged due to resulting test failure.
>>>
>>> Please don't post new versions before this can be actually tested and
>>> applied.
>> Heh, you responded *after two months*, to an old email so even previous
>> discussion is gone from my inbox.
> 
> 
> Sorry about that, I initially misunderstood it was regarding the b4 deps 
> I created. I wanted to confirm before posting new version yesterday, 
> hence clarified about the dependency.


Please correct me if I understood:
After two months you responded dependency is needed. Dependency means
this cannot be merged. You want to confirm if you can post new version.

In that case depends on the dependency. If it is still there, it won't
be possible to merge it, right? Or maybe it is not there, but it is not
us who should guess it but you should tell us.

Best regards,
Krzysztof

Re: [PATCH RFC v2 1/5] dt-bindings: thermal: Add MBG thermal monitor support

[Dmitry Baryshkov]

On Wed, Feb 12, 2025 at 07:06:56AM +0100, Krzysztof Kozlowski wrote:
> On 12/02/2025 00:57, Dmitry Baryshkov wrote:
> > On Tue, Feb 11, 2025 at 12:50:12PM +0100, Krzysztof Kozlowski wrote:
> >> On 11/02/2025 12:46, Krzysztof Kozlowski wrote:
> >>> On 11/02/2025 12:15, Satya Priya Kakitapalli wrote:
> >>>>
> >>>> On 12/13/2024 2:08 PM, Krzysztof Kozlowski wrote:
> >>>>> On Thu, Dec 12, 2024 at 09:41:20PM +0530, Satya Priya Kakitapalli wrote:
> >>>>>> +
> >>>>>> +required:
> >>>>>> +  - compatible
> >>>>>> +  - reg
> >>>>>> +  - interrupts
> >>>>>> +  - io-channels
> >>>>>> +  - io-channel-names
> >>>>> Binding looks ok, but this wasn't tested due to unneeded dependency.
> >>>>> Please decouple from dependency, so automation can properly test it.
> >>>>
> >>>>
> >>>> The dependency is needed because this mbg peripheral is present on only 
> >>>> targets which have GEN3 ADC5, for which the bindings support is added in 
> >>>> the series [1]
> >>>>
> >>>>
> >>>> [1] 
> >>>> https://lore.kernel.org/linux-arm-msm/c4ca0a4c-e421-4cf6-b073-8e9019400f4c@quicinc.com/
> >>>
> >>> Sure. Then this cannot be merged due to resulting test failure.
> >>>
> >>> Please don't post new versions before this can be actually tested and
> >>> applied.
> >>
> >> Heh, you responded *after two months*, to an old email so even previous
> >> discussion is gone from my inbox.
> > 
> > Are you responding to your own email?
> 
> Look at the timeline of these emails. Satya responded after two months
> with some comment. I responded now. Then I noticed that it is talk about
> something two months old, so I responded again. Two responses from me,
> that's correct.

I see, Satya's email didn't get to lore.kernel.org, so it wasn't fetched
by lei.

> I recently got way too many such 2-month old clarifications.
> 
> That's indeed right of the contributor to respond in their own pace, I
> am also sometimes slow, but really there should be some limit. It's
> putting unnecessary burden on reviewers as now I should dig some old
> discussion.

-- 
With best wishes
Dmitry