From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63D3C2E9EA3; Mon, 8 Sep 2025 21:40:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757367615; cv=none; b=U+AUMTXKLbyS2NHEQOhj2/5y+9YslT7Mxu6C1JS15r8sQc3M73ZUeXMePB4JtQmZNcNsFtBFLe7eatEJ3tWmD+z+SMPNmO4XcNgJ2jIzLxBA4eZVxFrm8SejegS06+AlQvz0Ve/2bs5Qt7RyGoLPNQ9ZHJmuoOwolOcVrimLqPY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757367615; c=relaxed/simple; bh=3DsTDs878uk2gOW7XGdvfuQ443cB/EwWbkkbr3wotVI=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=EkFVdPCcmE7gSbNmry4BiBYzKORG+Qkfyw68gSUe6JvDuQfsxU95K8g2a7yBBBJZUN0UX9pawe0mHeHBZ7te/ElbT4HbgpVyFFhow/OQkXZo30sKmeJ45UXtMomdWJlWiJ3WluBldNP5SJn+NauF+t6Z9nw1V4DUILqfj/69kqM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VG5JY9JK; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VG5JY9JK" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 588Le7wl3878309; Mon, 8 Sep 2025 16:40:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757367607; bh=Mo2EFkzOaChPuvJidrt2tQqO/I5DDfDOd/qxOfVZ3Nk=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=VG5JY9JKGvbSfigMkJ1Ng1EGEa0XjeiPKmqSGSrvSAQuPfDCTgemWX/1BmT4xwexn nSTuUn7Dv6IKX+XV/QVkZK1kq3SebifpKlTK/auVS/Uy6NL7glAU4r/TszA/p2/d8H QsEbhCf4DWvQrnfiBEk2dMSWO+3K9wSeFsl+0/eQ= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 588Le7L12683429 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 16:40:07 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 16:40:06 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 16:40:06 -0500 Received: from [128.247.81.19] (uda0506412.dhcp.ti.com [128.247.81.19]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 588Le6T11545093; Mon, 8 Sep 2025 16:40:06 -0500 Message-ID: Date: Mon, 8 Sep 2025 16:40:06 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/4] arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS To: Akashdeep Kaur , , , , , , , , , , , , , , CC: References: <20250905051448.2836237-1-a-kaur@ti.com> <20250905051448.2836237-3-a-kaur@ti.com> Content-Language: en-US From: Kendall Willis In-Reply-To: <20250905051448.2836237-3-a-kaur@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 9/5/25 00:14, Akashdeep Kaur wrote: > After the SoC has entered the DeepSleep low power mode, USB1 can be > used to wakeup the SoC based on USB events triggered by USB devices. > This requires that the pin corresponding to the Type-A connector > remains pulled up even after the SoC has entered the DeepSleep low power > mode. > For that, either DeepSleep pullup configuration can be selected or the pin > can have the same configuration that it had when SoC was in active mode. > But, in order for DeepSleep configuration to take effect, the DeepSleep > control bit has to be enabled. > Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, > as the DeepSleep control bit is not set and the active configuration is > sufficient to keep the pin pulled up. This simplifies the setup and removes > redundant configuration. > > This reverts commit 527f884d2d94981016e181dcbd4c4b5bf597c0ad. > > Reviewed-by: Dhruva Gole > Signed-off-by: Akashdeep Kaur Verified USB disconnect, USB connect, and USB remote wakeup on SK-AM62B-P1. Tested-by: Kendall Willis > --- > arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi > index 13e1d36123d5..d3bed23134ca 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi > @@ -249,7 +249,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ > > main_usb1_pins_default: main-usb1-default-pins { > pinctrl-single,pins = < > - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */ > + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ > >; > }; >