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I’d like to ask if you have any comments on the latest patch? > > On 3/25/2026 7:21 PM, Jun Guo wrote: > > Enable DMANSECCTRL.INTREN_ANYCHINTR during probe so channel > > interrupts are propagated when integrators wire DMA-350 channels > > onto a shared IRQ line. Your tag is wrong dmaegine: arm-dma350: enable ANYCH ... > > > > Signed-off-by: Jun Guo > > --- > > drivers/dma/arm-dma350.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c > > index 84220fa83029..09403aca8bb0 100644 > > --- a/drivers/dma/arm-dma350.c > > +++ b/drivers/dma/arm-dma350.c > > @@ -13,6 +13,11 @@ > > #include "dmaengine.h" > > #include "virt-dma.h" extra empty line between header file and macro > > +#define DMANSECCTRL 0x200 > > + > > +#define NSEC_CTRL 0x0c why need two layer regiser define, your use DMANSECCTRL + NSEC_CTRL， why not use one macro for 0x20c Frank > > +#define INTREN_ANYCHINTR_EN BIT(0) > > + > > #define DMAINFO 0x0f00 > > #define DMA_BUILDCFG0 0xb0 > > @@ -582,6 +587,10 @@ static int d350_probe(struct platform_device *pdev) > > dmac->dma.device_issue_pending = d350_issue_pending; > > INIT_LIST_HEAD(&dmac->dma.channels); > > + reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL); > > + writel_relaxed(reg | INTREN_ANYCHINTR_EN, > > + base + DMANSECCTRL + NSEC_CTRL); > > + > > /* Would be nice to have per-channel caps for this... */ > > memset = true; > > for (int i = 0; i < nchan; i++) { >