Re: [PATCH 04/13] clk: amlogic: Add basic clock driver

Chuan Liu
2026-04-08T14:32:37Z

Hi Krzysztof (& ALL),
Thanks for review.

On 2/9/2026 9:17 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 09/02/2026 06:48, Chuan Liu via B4 Relay wrote:
>> From: Chuan Liu <chuan.liu@amlogic.com>
>>
>> Implement core clock driver for Amlogic SoC platforms, supporting
>
> So how did all existing Amlogic SoC platforms work so far without basic
> clock driver? Really, how?
>
> You are suppose to grow existing code, not add your completely new
> "basic" driver just because you have it that way in downstream.
>

Firstly, apologies for the delayed response. I had intended to
consolidate the V1 review feedback and come back with a clearer plan for
V2 changes. In the meantime, Martin has provided many detailed and
valuable suggestions - much appreciated.

The original goal of optimizing the HW based on A9 and introducing a new
clock driver is to reduce unnecessary complexity in the driver. On A9,
we optimized the Clock/PLL controller HW to simplify driver performance,
complexity, memory footprint, and reusability. Improvements on the HW
side can also help drive corresponding enhancements in the driver:
- Performance: Encapsulates sub-clock functions, reducing call paths
- Complexity: Standardized register bits eliminate a large number of
bit definitions (~1/3 of original code is defined register bit [1])
- Memory: Object-oriented design avoids copy/paste for repeated clocks
- Reusability: Same controller works across SoCs without driver
changes (or with minimal changes)

The old meson driver required compromises to unify legacy controller
characteristics and driver styles. On A9, we want a fresh start.

> Best regards,
> Krzysztof

--
Best regards,
Chuan