From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: William Qiu <william.qiu@starfivetech.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org
Cc: "Emil Renner Berthing" <kernel@esmil.dk>,
"Rob Herring" <robh+dt@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Hal Feng" <hal.feng@starfivetech.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v7 1/4] dt-bindings: pwm: Add OpenCores PWM module
Date: Fri, 10 Nov 2023 13:24:16 +0100 [thread overview]
Message-ID: <afce202d-6234-4c5f-9018-facd9a56b5eb@linaro.org> (raw)
In-Reply-To: <20231110062039.103339-2-william.qiu@starfivetech.com>
On 10/11/2023 07:20, William Qiu wrote:
> Add documentation to describe OpenCores Pulse Width Modulation
> controller driver.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../bindings/pwm/opencores,pwm.yaml | 56 +++++++++++++++++++
> 1 file changed, 56 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> new file mode 100644
> index 000000000000..8f776bbc1112
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: OpenCores PWM controller
> +
> +maintainers:
> + - William Qiu <william.qiu@starfivetech.com>
> +
> +description:
> + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode, the PTC core
> + generates binary signal with user-programmable low and high periods. All PTC counters and
> + registers are 32-bit.
Wrap at 80 (as Coding Style asks)
> +
> +allOf:
> + - $ref: pwm.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - starfive,jh7100-pwm
> + - starfive,jh7110-pwm
> + - const: opencores,pwm
That's a very, very generic compatible. Are you sure, 100% sure, that
all designs from OpenCores from now till next 100 years will be 100%
compatible?
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-11-10 12:24 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-10 6:20 [PATCH v7 0/4] StarFive's Pulse Width Modulation driver support William Qiu
2023-11-10 6:20 ` [PATCH v7 1/4] dt-bindings: pwm: Add OpenCores PWM module William Qiu
2023-11-10 12:24 ` Krzysztof Kozlowski [this message]
2023-11-13 9:42 ` William Qiu
2023-11-13 20:07 ` Krzysztof Kozlowski
2023-11-13 20:17 ` Conor Dooley
2023-11-22 7:03 ` William Qiu
2023-11-22 17:36 ` Conor Dooley
2023-11-24 7:38 ` William Qiu
2023-11-24 12:44 ` Conor Dooley
2023-11-10 12:24 ` Krzysztof Kozlowski
2023-11-13 9:43 ` William Qiu
2023-11-10 6:20 ` [PATCH v7 2/4] pwm: opencores: Add PWM driver support William Qiu
2023-11-10 12:27 ` Krzysztof Kozlowski
2023-11-13 9:47 ` William Qiu
2023-11-10 6:20 ` [PATCH v7 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration William Qiu
2023-11-10 6:20 ` [PATCH v7 4/4] riscv: dts: starfive: jh7100: " William Qiu
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